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JPS5457839A - Display memory control system - Google Patents

Display memory control system

Info

Publication number
JPS5457839A
JPS5457839A JP12421677A JP12421677A JPS5457839A JP S5457839 A JPS5457839 A JP S5457839A JP 12421677 A JP12421677 A JP 12421677A JP 12421677 A JP12421677 A JP 12421677A JP S5457839 A JPS5457839 A JP S5457839A
Authority
JP
Japan
Prior art keywords
memory
read
addressing
data transfer
refreshing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12421677A
Other languages
Japanese (ja)
Inventor
Shoji Onuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12421677A priority Critical patent/JPS5457839A/en
Publication of JPS5457839A publication Critical patent/JPS5457839A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make efficient data transfer between a random access memory and other devices without flicker on a screen by transferring data with an external device within a display period without failing in refresh operation at every fixed time.
CONSTITUTION: A read address for refreshing is assigned 12, and read and write addresses for data transfer are assigned 13. During a period more than at least one memory cycle time of random access memory 11, the 1st and 2nd addressing parts 12 and 13 are selected 14 alternatively and memory 11 is accessed and controlled on the basis of the addressing of either 1st or 2nd addressing part 12 or 13 selected by selection part 14. In this case, read operation for refreshing is done in the one- memory cycle of memory 11, and read and write operation for data transfer in the remaining at least one-memory cycle during a display period for one character for display data read out from memory 11
COPYRIGHT: (C)1979,JPO&Japio
JP12421677A 1977-10-17 1977-10-17 Display memory control system Pending JPS5457839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12421677A JPS5457839A (en) 1977-10-17 1977-10-17 Display memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12421677A JPS5457839A (en) 1977-10-17 1977-10-17 Display memory control system

Publications (1)

Publication Number Publication Date
JPS5457839A true JPS5457839A (en) 1979-05-10

Family

ID=14879860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12421677A Pending JPS5457839A (en) 1977-10-17 1977-10-17 Display memory control system

Country Status (1)

Country Link
JP (1) JPS5457839A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60140383A (en) * 1983-12-28 1985-07-25 富士通株式会社 Output control for display unit
JPS63228191A (en) * 1987-03-17 1988-09-22 ジーイー横河メディカルシステム株式会社 Image display control circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60140383A (en) * 1983-12-28 1985-07-25 富士通株式会社 Output control for display unit
JPH0235987B2 (en) * 1983-12-28 1990-08-14 Fujitsu Ltd
JPS63228191A (en) * 1987-03-17 1988-09-22 ジーイー横河メディカルシステム株式会社 Image display control circuit

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