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EP0283927B1 - Adaptateur d'affichage - Google Patents

Adaptateur d'affichage Download PDF

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Publication number
EP0283927B1
EP0283927B1 EP19880104226 EP88104226A EP0283927B1 EP 0283927 B1 EP0283927 B1 EP 0283927B1 EP 19880104226 EP19880104226 EP 19880104226 EP 88104226 A EP88104226 A EP 88104226A EP 0283927 B1 EP0283927 B1 EP 0283927B1
Authority
EP
European Patent Office
Prior art keywords
data
display
image
adapter
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19880104226
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German (de)
English (en)
Other versions
EP0283927A2 (fr
EP0283927A3 (en
Inventor
Roy Bernard Harrison
Paul William Norris
Roger Timothy Wood
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
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Filing date
Publication date
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Publication of EP0283927A2 publication Critical patent/EP0283927A2/fr
Publication of EP0283927A3 publication Critical patent/EP0283927A3/en
Application granted granted Critical
Publication of EP0283927B1 publication Critical patent/EP0283927B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Definitions

  • the present invention relates to a display adapter for connecting the system bus of a workstation to a display means having a scanned display screen and to a workstation comprising such an adapter.
  • workstation is a general term applied to computing equipment and includes both stand alone units such as a personal computer and units which are used in a host connect mode such as a terminal or a personal computer provided with a terminal emulator.
  • the heart of a workstation is a central processing unit such as a microprocessor.
  • the processor is responsible for carrying a large range of different management tasks in addition to the processing of the user programs.
  • One management task which has been carried out by the processor in prior workstations is the formatting of image data in preparation for display.
  • the display of a workstation it is common for the display of a workstation to be a raster scanned display device such as a cathode ray tube device (CRT) which requires a refresh buffer.
  • CRT cathode ray tube device
  • the image data for display is normally stored in the display buffer in accordance with the scanning cycle for the display.
  • the data for the picture elements (pels) to be displayed is stored in a linear fashion in the display buffer.
  • the display buffer is in practice a part of the workstation's RAM.
  • a display adapter in accordance with the present invention for connecting the system bus of a workstation to a display means having a scanned display screen
  • the display adapter comprising input means for receiving positioning data specifying an area on the screen within which an image is to be displayed and for receiving a stream of data items representing the image, individual data items in the received stream defining respective pels of the image and the stream being ordered to define the image line-by-line and within each line, pel-by-pel; a display buffer to store, in an order corresponding to the display scanning sequence, data defining the pels to be displayed on the display screen; addressing logic adapted to compute, from the positioning data, individual storage locations in the display buffer to be addressed for individual data items in the received stream in order that the data for the individual pels of the image are stored in the display buffer in an order corresponding to the display scanning sequence and in an order that the image is displayed correctly on the display screen; characterised in that the input means comprises register means connectable to the system bus
  • the addressing logic comprises counter means connected to the register means for receiving the initial screen position information contained therein, arithmetic logic connected to the counter means for receiving the instantaneous values of information contained therein and for generating display buffer address signals therefrom and control logic which is connected to the control storage and, in response to the size and orientation data stored therein, causes the counter means to be loaded from the register means and/or the content of the counter means to be adjusted to identify the screen location for each successive data item, causes the arithmetic logic to perform appropriate arithmetic operations on instantaneous values contained in the counter means so as to generate display buffer addresses for successive data items in the received stream, and causes the data for the individual pels of the image to be stored in appropriate locations in the display buffer using the display buffer addresses so generated such that the image is displayed on the screen within said area.
  • Some processors for example the 80286 processor manufactured by the Intel Corporation, are provided with block move instructions which are significantly faster for moving a block than are the corresponding series of individual instructions.
  • the block move instructions cannot be used if the order of the data within the block has to be changed by the processor and consequently they cannot be used to move a block of image data arranged in perceived display order into a display buffer.
  • a workstation with a display adapter according to the invention does allow the block move instructions to be used.
  • a stream of image data can be sent from the workstation RAM to the display adapter using a processor block move operation in the same way that blocks of information can be transferred to an I/O device such as direct access storage devices (DASDs).
  • the display adapter can either process the stream of image data directly as it arrives, or, if the display adapter is additionally provided with an image buffer for the temporary storage of the stream, the processing of the stream can be performed subsequently.
  • Providing a workstation with a display adapter according to the present invention enables performance to be improved. Firstly, it enables faster updating of displayed images. This is a result, primarily, of the fact that the workstation processor no longer has to calculate display buffer addresses. In processors in which fast block move operations to a single address or series of addresses are possible, further improvements in the speed of updating can be achieved because these block moves can be exploited. Performance is also improved because the display buffer need not be contained within the processor address space due to the display adapter being responsible for addressing the individual the display buffer locations and consequently, processor address space is saved for other uses.
  • the display adapter is preferably implemented as special purpose hard-wired logic to take advantage of the speed of such logic.
  • the present invention does not, however, exclude the possibility of implementing the present adapter with a high speed microprocessor and storage elements and appropriate code.
  • the display adapter includes a display buffer 36 which is not addressed directly by the processor.
  • the display device can, however access the display buffer in order to fetch the data corresponding to the individual picture elements on the screen (38, Figure 2A).
  • the data are fetched in synchronism with the scanning of the display screen. To facilitate this the information in the display buffer is organised in accordance with the scanning sequence of the display refresh circuitry.
  • Figure 2A illustrates the display screen as perceived.
  • the screen has "Y" lines of "X" pels each. As shown the lines of the screen are numbered from 0 to Y-1 starting from the top and moving down the screen. The pels in each row are likewise shown numbered, from left to right, 0 to X-1.
  • the display buffer comprises a single unit and is organised on 8 bit bytes.
  • Each pel is represented by 4 bits of information defining the intensity and/or colour of the pel.
  • the buffer could be organised in the form of a plurality of parallel bit planes, each comprising one bit per pel, whereby the combination of the bit planes defines the complete image and whereby the complete pel information for a location on the screen is defined by the combination of the information in the corresponding position in each of the bit planes.
  • a different number of bits might be also be chosen.
  • the display screen is refreshed in this embodiment using an interleaved scanning technique as is often the case in the art so that the scanning of even numbered rows alternates with the scanning of odd numbered rows.
  • the image data for the individual pels of the display screen shown in Figure 2A are stored as shown in Figure 2B, with the data relating to the even numbered rows stored in a first sequence from a base address 361 of the refresh buffer and the data relating to the odd numbered rows stored in a second sequence starting at an offset address 362 at or after the end of the first sequence.
  • the data relating to each of the sixteen pels will not normally be generated in the workstation in the same order as that in which the data is stored in the display buffer. Commonly the data will be generated as a string or sequence 42 of data items, in which the individual pels of the image are defined line-by-line, and within each line, pel-by-pel.
  • Figure 2C illustrates a string in which the image is defined row-by-row, and within each row, pel-by-pel.
  • the first four data items relate to the pels on a first row (b)
  • the second four relate to the four pels on the adjacent second row (b+1)
  • the adapter comprises a control unit 44 which is connected to the address bus 16 and to the control bus 18. Associated with the control unit is control storage 46 which is connected to the data bus 14 for the receipt of initialisation data from the workstation RAM. Also connected to the data bus for the receipt of initialisation data from the workstation RAM are first and second registers 48 and 50. A first input 52 of a two input multiplexer 54 is also connected to the data bus for the receipt of image data from the workstation RAM. The second input 56 of the multiplexer is connected to an external source of data (not shown), either directly, or via a data gearbox as will be explained later with reference to Figure 4.
  • the output 57 of the multiplexer is connected to the data port 68 of the display buffer 38.
  • the display adapter also comprises first and second counters 49 and 51 connected, respectively, to the first and second registers for receiving the count stored therein.
  • An arithmetic logic unit 58 has first, 60, and second, 62, inputs connected, respectively, to the first and second counters.
  • the output 64 of the arithmetic unit is connected to the address input of the display buffer 38.
  • a driver 69 is connected between the data port of the display buffer and the data bus and is used for the transfer of data in the buffer to the bus.
  • the control unit is connected via control inputs C to the control storage, the first and the second registers, the first and second counters, the multiplexer, the arithmetic logic unit and the driver.
  • the image is to be displayed upright within an area having its upper left corner at a screen position b,a, where b is the vertical displacement in pels from the top of the screen and a is the horizontal displacement in pels from the left hand side of the screen.
  • the processor first initialises the display adapter by sending positioning data to the adapter over the data bus.
  • the positioning data comprises initial screen position information which is sent to the first and second registers and size, orientation and data stream format information which is sent to the control storage.
  • the initial screen position information comprises the "x" and "y" values ("a” and "b") for the screen position of one corner of the area (eg. the top left hand corner) in which the image is to be displayed.
  • the area size information defines the length of the horizontal and vertical sides of a rectangular area in which the image is to be displayed in terms of a numbers of pels.
  • the orientation information effectively defines which corner of the rectangular area is identified by the "x" and "y” values stored in the first and second registers.
  • the orientation information defines whether successive image items in the stream are to be displayed at increasing or decreasing y and x values (ie. x increasing / decreasing, y increasing / decreasing) and whether the image data is ordered row-by-row or column-by-column (ie.
  • the data stream format information identifies the format of the stream of image data items to be received (ie. the number of bits per data item and/or the number of data items per byte).
  • the adapter assumes that each data item comprises the complete definition of a pel (ie. for all the constituent bit planes).
  • This information will have been available to the processor in RAM as a result of the generation or selection of the image for display.
  • control logic also requires organisation data defining the organisation of the display buffer in order to be able to generate the display buffer addresses for a stream of incoming data items.
  • the organisation data are loaded into the control storage by the processor. This can be either done at the same time as the initialisation data is supplied, or it can be done at some earlier time.
  • the organisation data comprise the base address of the display buffer, (ie. the address from which the even numbered lines of pels are stored - 361, Figure 2B), the number of pels per byte, the total number of pels per line on the screen, the total number of scan lines on the screen and the address from which the odd numbered scan lines are stored (362, Figure 2B).
  • the control logic includes logic for determining the particular operations to be performed in the display adapter on the basis of the initialisation data, including the particular arithmetic operations to be performed by the arithmetic logic.
  • the offset address is the base address plus an offset.
  • the image data can then be sent by the processor as a stream of data at high speed from the workstation RAM via the data bus to a single address (ie. the input 52 of the multiplexer 54). This is done by the processor using a single block move instruction.
  • the control unit 44 contains interlock mechanisms of a conventional type, as are provided in other adapters, for controlling the exchange of information with the host. By means of these mechanisms it is possible for the host to transfer the data as a block (ie. as an uninterrupted string or sequence) when both the processor and the adapter are ready.
  • the display adapter is configured as hard logic, it is able to process the information in real time as the stream of image data comes over the bus from the RAM.
  • the image data received at the multiplexer 54 is directed to the appropriate locations in the display buffer under the control of the control unit 44.
  • the control logic causes the content of first and second counters to be automatically updated for each data item received in the sequence of data items and controls the arithmetic logic to perform appropriate arithmetic operations.
  • the updating of the counters and the operation of the arithmetic logic is synchronised by the control logic with the receipt of successive data items in the data stream as they are received so that the data items may be stored directly in the appropriate display buffer locations.
  • Figure 6 is a flow diagram giving an overview of the operations performed by the display adapter in generating the display buffer addresses for storing the successive data items. The steps outlined in Figure 6 are illustrated in the following with reference to the example shown in Figures 2).
  • IN STEP 80 the initial screen displacement value, b, for the y ordinate (identified as being the major ordinate in the initialisation data and stored in the second register 50) is loaded into the second counter 51.
  • IN STEP 82 the initial screen displacement value, a, for the x (ie. the remaining) ordinate is loaded into the first counter 49.
  • the control logic causes the arithmetic logic to calculate the address of the location in the display buffer for the data item to be displayed at the screen displacement values currently in the first and second counters.
  • the control logic determines from the horizontal length of the rectangle (ie. the horizontal size) whether there are any more display buffer addresses to be calculated for the current row of pels. This is done by maintaining a count in the control logic of the number of pels processed in the current row. If there are, the control logic increments the first counter as the initialisation data specified "x increasing" (It would have been decremented if the initialisation data had specified "x decreasing").
  • control logic then returns (via loop 88) to step 84 and causes the arithmetic logic to calculate the address for the second data item using the formulae indicated above. If there are no more pels in the current row of the image, the logic proceeds by path 90. IN STEP 92 the control logic determines from the vertical length of the rectangle (ie. the vertical size) whether there are any more rows to be processed for the image. This is done by maintaining a count in the control logic of the number of rows processed for the current image. If there are, the control logic increments the second counter as the initialisation data specified "y increasing" (It would have been decremented if the initialisation data had specified "y decreasing").
  • control logic then returns (via loop 94) to step 82 and causes the initial screen displacement value, a, for the x ordinate to be loaded into the first counter. If there are no more rows to be processed the control logic then exits via the path 96 and the transfer of the image data stream is complete.
  • the second input 56 of the multiplexer is connected to an external source of data.
  • the procedure for receiving image data from an external source is essentially the same as that for receiving image data from the data bus.
  • the initialisation data would still be provided over the data bus by the processor, but in this case the source would be identified as that connected to the input 56 of the multiplexer.
  • the alternative source could be a video source such as a video camera with a digital interface. It could be an image data stream output from, or for, another display adapter with a different scanning rate.
  • the adapter therefore allows emulation of existing display adapters. This is a useful facility as it provides compatibility with existing workstation systems.
  • connection to the alternative video source could be via a direct path as in Figure 3 if the display adapter is able to cope with the video rates of all of the external sources which might be connected to it. If, however, it is intended to connect video sources having very high video data rates, it is preferable to employ a data gearbox 70 as shown in Figure 4.
  • the gearbox will have a reduction ratio which is variable under the control of the control logic.
  • the purpose of the data gearbox is to select only every Nth pel of the image data received from the external video source.
  • the control logic controls the reduction gearbox and the other elements of the adapter to alter only 1 in N pels on each scan of the incoming image data in such a manner that the complete incoming image is captured every Nth scan. This technique has been used successfully to capture the output of an external display adapter running at many times the pel drawing rate of the present adapter.
  • the adapter shown in Figure 3 had a driver connected between the data port of the display buffer and the workstation bus.
  • this driver can be used to save a screen, or part of a screen of data in the workstation memory, after, for example, compiling a screen of data from a number of constituent images.
  • the provision of the driver also means that it is possible to capture image data from an external source by reading a stream of image data from the external source into the display buffer and then transferring that data to the workstation RAM.
  • Figure 5 illustrates an alternative version of the display adapter shown in Figure 3 which enables a stream of image data to be received at very high burst rates which exceed the display buffer addressing capability (or pel drawing rate) of the display adapter.
  • the alternative display adapter is additionally provided with an image buffer 72 which is connected between the multiplexer and the display buffer in the image data path.
  • the control logic is arranged to read the image data received via the multiplexer.
  • the provision of the image buffer also allows the image data transfer rate to be increased in certain circumstances as it means that space and/or data is/are always available and as a consequence processor wait states can be saved.
  • the ability to buffer the data in the image buffer in this way is a result of the control logic rather than the processor addressing the individual locations.
  • the version of adapter shown in Figure 5 could additionally be provided with a data gearbox as shown in the Figure 4 version.
  • the adapter could be arranged to only accept a single input data format.
  • control logic could be so configured that constant data stream format information (eg. the number of data items per byte) would be incorporated in the logic and consequently this information would not need to be provided by the processor with the initialisation information.
  • the image data for each of a number of bit planes one after another.
  • Each data item would comprise a single bit and the complete image would be formed from the combination of the information for each of the bit planes.
  • the adapter could be configured to accept the input information in this form by causing the contents of appropriate display buffer locations to be modified by, rather than replaced by the data items in the incoming data stream.
  • the adapter could alternatively be provided with an output multiplexer so that image data from the screen could be supplied to the data bus of the workstation, or alternatively to an external device.
  • the area displayed on the screen is rectangular.
  • the adapter could also be provided with a facility to display images which were not rectangular by incorporating masking logic in the adapter. In simple terms this could be achieved transferring mask boundary information from the workstation RAM to the control storage and subsequently transferring image data for a rectangular area as described in the preceding description. In this case, however, the control logic would cause the data items relating to screen positions outside the mask boundary to be discarded so that only that part of the image within the boundary would be written to the buffer and be displayed.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)

Claims (8)

  1. Adaptateur vidéo pour relier le bus système (12) d'un poste de travail à un dispositif d'affichage et de visualisation (34) équipé d'un écran vidéo à balayage,l'adaptateur vidéo comprenant :
    un dispositif d'entrée pour recevoir des données de positionnement définissant une zone d'écran dans laquelle une image doit être affichée et pour recevoir un flux (42) d'éléments d'information représentant l'image, les éléments d'information individuels dans le flux reçu définissant les pixels respectifs de l'image, et le flux (42) étant ordonné pour définir l'image ligne-par-ligne et, dans chaque ligne, pixel-par-pixel;
    une mémoire-tampon vidéo (38) pour mémoriser, dans un ordre correspondant à la séquence de balayage d'écran, des données définissant les pixels à afficher sur l'écran vidéo;
    une logique d'adressage (44, 49, 51, 58) adaptée pour pouvoir calculer, à partir des données de positionnement, des emplacements de mémoire individuels dans la mémoire-tampon vidéo à adresser pour les éléments d'informations individuels du flux reçu (42), en sorte que les données pour les pixels individuels de l'image soient enregistrées dans la mémoire-tampon dans un ordre correspondant à la séquence de balayage d'écran, et en sorte que l'image soit affichée correctement sur l'écran vidéo;
    caractérisé en ce que le dispositif d'entrée comprend :
    un dispositif de registres (48, 50) connectables au bus système pour recevoir les informations sur la position initiale à l'écran;
    une mémoire de commande (46) connectable au bus système pour recevoir les informations sur la taille et l'orientation qui, en combinaison avec les informations sur la position initiale à l'écran, forment les données de positionnement qui définissent la zone d'écran dans laquelle l'image doit être affichée; et
    un dispositif de porte (54) connectable au bus système pour recevoir le flux (42) d'éléments d'information représentant une image à afficher dans cette zone, une sortie du dispositif de porte étant connectée à la mémoire-tampon vidéo.
  2. Adaptateur vidéo selon la revendication 1, caractérisé, de plus, en ce que la logique d'adressage comprend :
    un dispositif de comptage (49, 51) relié au dispositif de registres (48, 50) pour recevoir les informations sur la position initiale à l'écran contenues dans celui-ci;
    une unité de calcul (58) reliée au dispositif de comptage pour recevoir les valeurs instantanées des informations qu'il contient et pour générer des signaux d'adresses de mémoire-tampon vidéo, et
    une logique de commande (44) qui est reliée à la mémoire de commande (46) et qui, en réponse aux informations sur la taille et l'orientation qu'elle contient :
    - génère le chargement du dispositif de comptage (49, 51) à partir du dispositif de registres (48, 50) et/ou l'ajustement du contenu du dispositif de comptage (49, 51), en synchronisme avec la réception des éléments d'information successifs du flux reçu, pour identifier l'emplacement pour chaque élément d'information successif;
    - génère l'exécution par l'unité de calcul (58) des opérations arithmétiques adéquates sur les valeurs instantanées contenues dans le dispositif de comptage, afin de générer des adresses de mémoire-tampon vidéo pour les éléments d'information successifs du flux reçu; et
    - génère l'enregistrement des pixels individuels de l'image dans des emplacements appropriés de la mémoire-tampon vidéo (38), en utilisant les adresses de mémoire-tampon vidéo ainsi générées en sorte que l'image soit affichée à l'écran dans ladite zone.
  3. Adaptateur vidéo selon la revendication 1 ou la revendication 2, dans lequel le dispositif de porte comprend un multiplexeur à entrées multiples (54), dont une première entrée (52) est connectable au bus système (12, 14) d'un poste de travail pour recevoir un flux de données vidéo provenant de la mémoire RAM du poste de travail, dont une seconde entrée (56) est connectable à une autre source vidéo (via 37) extérieure au poste de travail, et dont la sortie est reliée au port d'entrée/sortie de la mémoire-tampon vidéo.
  4. Adaptateur vidéo selon la revendication 3, comprenant, de plus, un démultiplicateur de données (70) connectable à l'autre source vidéo pour sélectionner seulement chaque Nième pixel des images vidéo reçues de l'autre source vidéo, la sortie du démultiplicateur de données étant reliée à la seconde entrée (56) du multiplexeur (54), et l'entrée de commande (c) du démultiplicateur (70) étant connectée à la logique de commande (44), permettant ainsi, s'il y a lieu, de réduire le débit de données de l'autre source vidéo, sous le contrôle de la logique de commande (44), au niveau du débit de données acceptable par l'adaptateur vidéo.
  5. Adaptateur vidéo selon l'une quelconque des revendications précédentes, comprenant, de plus, une mémoire-tampon d'image (72) pour mémoriser temporairement le flux de données vidéo reçu, ladite mémoire-tampon vidéo (72) étant connectée entre le dispositif de porte (54) et la mémoire-tampon vidéo (38), et reliée, de plus, au dispositif de commande (44) va une entrée de commande (c).
  6. Adaptateur vidéo selon l'une quelconque des revendications précédentes, comprenant, de plus, un circuit d'attaque (69) dont l'entrée est connectée au port d'entrée/sortie (68) de la mémoire-tampon vidéo (38), et dont la sortie est connectable au bus système (12, 14), pour permettre le transfert, en cours d'exploitation, des données vidéo de la mémoire-tampon vidéo (38) au bus système.
  7. Poste de travail comprenant une unité centrale de traitement (10), une mémoire à accès direct (mémoire RAM) (20), un bus système (12), un dispositif d'affichage et de visualisation (34) équipé d'un écran vidéo à balayage, et un adaptateur vidéo (32) selon l'une quelconque des revendications précédentes connecté entre le bus système et le dispositif d'affichage et de visualisation.
  8. Poste de travail selon la revendication 7, dans lequel le poste de travail est configuré en sorte que l'adaptateur vidéo (32) soit relié au processeur via l'un des ports d'entrée-sortie du processeur, et en sorte que le flux de données vidéo puisse être transmis par la mémoire RAM du poste de travail en réponse à une opération de déplacement par bloc du processeur.
EP19880104226 1987-03-27 1988-03-17 Adaptateur d'affichage Expired - Lifetime EP0283927B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8707409 1987-03-27
GB8707409A GB2202718B (en) 1987-03-27 1987-03-27 Display adapter

Publications (3)

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EP0283927A2 EP0283927A2 (fr) 1988-09-28
EP0283927A3 EP0283927A3 (en) 1990-09-19
EP0283927B1 true EP0283927B1 (fr) 1993-12-01

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EP19880104226 Expired - Lifetime EP0283927B1 (fr) 1987-03-27 1988-03-17 Adaptateur d'affichage

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EP (1) EP0283927B1 (fr)
JP (1) JPS63250688A (fr)
DE (1) DE3885925T2 (fr)
GB (1) GB2202718B (fr)

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JPH01310390A (ja) * 1988-06-09 1989-12-14 Oki Electric Ind Co Ltd フレーム・メモリ制御方式
US5517612A (en) * 1993-11-12 1996-05-14 International Business Machines Corporation Device for scaling real-time image frames in multi-media workstations
FR2789779B1 (fr) * 1999-02-11 2001-04-20 Bull Cp8 Procede de traitement securise d'un element logique sensible dans un registre memoire, et module de securite mettant en oeuvre ce procede

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JPS5952286A (ja) * 1982-09-20 1984-03-26 株式会社東芝 ビデオｒａｍ書込み制御方式
JPH067304B2 (ja) * 1982-12-10 1994-01-26 株式会社日立製作所 図形処理装置
US4679038A (en) * 1983-07-18 1987-07-07 International Business Machines Corporation Band buffer display system
JPS6211380A (ja) * 1985-07-09 1987-01-20 Iizeru:Kk 画像信号変換方法

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Publication number Publication date
GB2202718B (en) 1991-09-18
DE3885925D1 (de) 1994-01-13
EP0283927A2 (fr) 1988-09-28
JPS63250688A (ja) 1988-10-18
GB8707409D0 (en) 1987-04-29
EP0283927A3 (en) 1990-09-19
GB2202718A (en) 1988-09-28
DE3885925T2 (de) 1994-05-19

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