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EP0206328A2 - Dispositif de commande d'un appareil d'affichage à balayage à trame - Google Patents

Dispositif de commande d'un appareil d'affichage à balayage à trame Download PDF

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Publication number
EP0206328A2
EP0206328A2 EP86108650A EP86108650A EP0206328A2 EP 0206328 A2 EP0206328 A2 EP 0206328A2 EP 86108650 A EP86108650 A EP 86108650A EP 86108650 A EP86108650 A EP 86108650A EP 0206328 A2 EP0206328 A2 EP 0206328A2
Authority
EP
European Patent Office
Prior art keywords
address
display
area
signal
storing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP86108650A
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German (de)
English (en)
Other versions
EP0206328A3 (en
EP0206328B1 (fr
Inventor
Nobuyuki Oki Electric Industry Co. Ltd. Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
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Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to AT86108650T priority Critical patent/ATE90469T1/de
Publication of EP0206328A2 publication Critical patent/EP0206328A2/fr
Publication of EP0206328A3 publication Critical patent/EP0206328A3/en
Application granted granted Critical
Publication of EP0206328B1 publication Critical patent/EP0206328B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen

Definitions

  • the present invention relates to a control circuit of a raster scanning display unit capable of simultaneouly displaying a plurality of independent display informations on a single display screen.
  • a control circuit of a display unit of this type is known is for example Japanese Laid-Open Patent Publication No. 60-22184. Let us describe here the control circuit with reference to Fig. 1.
  • Fig. 1 is an illustration partly depicting a control circuit of a display unit.
  • designa_ted at 1 is a CRT controller
  • 2 is a video memory for storing display data
  • 3 is a parallel/serial converter for converting paralled data to serial data, from which a VIDEO signal is delivered.
  • Designated at 4 is a dot clock generator circuit with which the above-described VIDEO signal is synchronized.
  • An output signal from the frequency divider 111 is hereafter called an address clock (in addition, x dot data is enterd into one address of the video memory 2).
  • an address clock in addition, x dot data is enterd into one address of the video memory 2.
  • a frequency divider for generating one pulse at each y address clock with use of an address clock provided from the frequency divider circuit 111 as an input signal.
  • An output signal from the frequency divider 112 is hereafter called a raster clock (in addition, x.y dot data is displayed per one raster).
  • a CPU sets address data to the counter 108.
  • An address being set here is a head address N1 of a write area.
  • the CPU switches the mode register 110 to a write mode, An output signal from the counter is delivered to an address line 6 while the mode register 110 is operated in the write mode, and hence the above-described head address is supplied to the video memory 2.
  • display data is provided to a data line 8, while a write signal provided to a control line 7, both from a circuit (not shown) of the CRT controller 1.
  • the counter 108 is incremented by +1 to permit the display data to be written into the next address.
  • address data is again set to the counter 108.
  • the address being set here is the head address N2 of the next writer area.
  • display data B is likewise written into the video memory 2. Display data A, B,...H are written in succession into the video memory 2 in this way.
  • the mode register 110 is switched to a read mode.
  • An output signal from the counter 106 is delivered onto the address line while the mode register 110 is operated in the read mode.
  • a read signal is provided onto the control line 7 from the circuit (not shown) of the CRT controller 1.
  • Any display data is hereby read from the video memory 2, and delivered onto the data line 8.
  • the above data is concerted to serial data through the parallel/serial converter 3 to provide a VIDEO signal. Issued one address display data (x dot) from the parallel/serial converter 3 as the VIDEO signal, the frequency divider 111 provides one pulse.
  • the counter 106 is incremented by +1.
  • any display data is read from the next address (N1+1) of the video memory 2.
  • a control circuit of a raster scanning display unit according to the present invention has:
  • FIG. 3 Blocks designated by the numerals 1 to 4 in Fig. 3 are the same as those shown in Fig. 1.
  • designated at 5 is an address converting part, whose details are shown in Fig. 4.
  • Fig. 5(a) depicts a display state on the screen, while Fig. 5(b) shows a storage state of display data in the video memory 2.
  • A designates an area of displaying display data A'; B1 an area of displaying display data B1'; H an area of displaying display data H'.
  • Na shows a head address of the area in which the display data A' is stored.
  • Nb shows a headaddress of the area in which the display data B' is stored.
  • Na1 designates a head address of an area where displays are superposed.
  • Nb1 is a head address of an area where the superposed diplay data B'1 is stored.
  • the area B1 where superposition of displays is effected is designated by four parameters: a parameter (e) for showing a vertical position; a parameter (c) for showing a height; a parameter (b) for showing a width; and a parameter (d) for showing a horizontal position.
  • the parameters (c) and (e) are represented by raster numbers, while the parameters (b) and (d) by corresponding address numbers of the video memory 2.
  • the registers 51, 52, 53, and 54 respectively hold complements of the parameters (e), (c), (d), and (b).
  • Fig. 4 designated at 55 and 56 are selectors,and 57, 58, 59 and 60 are counters, for which one corresponding to TI-made SN 74163 for example is employ_ed.
  • the counters 57 and 58 comprise a combination of a prescribed number of counters.
  • Designated at 61, 62, 63, and 64 are inverters, 65, 66 are two-input NOR gates,67 is a three-input AND gate, 68 is a selector, 69 is an adder, 70 is a register which holds a difference (Nb1-Na1) between the Nb1 and Na1 of Fig.
  • "HL” is a high level signal
  • "SYNC” is a vertical synchronization signal of the display unit
  • "DATA” is a data signal from a CPU (not shown)
  • "CLK1” is the raster clock being an output signal from the frequency divider circuit 112 of Fig. 1
  • CLK2 is the address clock being an output signal from the frequency divider circuit 111 of Fig. 1
  • MDISP is a signal to instruct displays to be superposed, which is availabel from the CPU not shown
  • "ADD” is an output signal from the selector 109 of Fig. 1
  • "VADD" is an address signal of the video memory 2.
  • the MDISP signal is set to "1" for effecting superposed display.
  • complements of the parameters (e), (c), (d), and (b) are set to the registers 51,52, 53, and 54 (The data is available from the CPU not shown).
  • an output signal from the register 51 is supplied to an input terminal D of the counter 57 via the selector 55.
  • the VSYNC signal is supplied to a load terminal L of the counter 57 via the inverter 61 and the two-input NOR gate 65, so that data supplied to the data input terminal D is loaded to the counter 57 in synchronism with the CLK1.
  • a "0" signal is delivered from output terminals Qc, Qd of the counter 59 and a "0" signal is delivered from the three-input AND gate 67.
  • the selector 68 allows an ADD signal to pass therethrough.
  • the counter 57 is counted up one by one in synchronism with the CLK1.
  • a signal "1" is provided from a carry terminal CA of the counter 57, and a signal "0" (load signal) is supplied to the load terminal L of the counter 57 via the two-input NOR gate 65. Since the VSYNC signal gets “0" only upon starting display and otherwise "1", an ouput signal from the register 52 has been supplied to the data input terminal D of the counter 57 via the selector 55. Accordingly, data held in the register 52 is loaded into the counter 57 by the load signal in synchronism with the CLK1.
  • a signal "1" from the carry terminal CA of the counter 57 is supplied to a count enable terminal T of the counter 59, whereby the counter 59 is incremented by +1 in synchro_nism with the CLK1.
  • a signal "1" is delivered from the output terminal of the counter 59.
  • the counter 57 again counts up the CLK1 in synchronism therewith one by one.
  • a signal "1" is delivered from the carry terminal CA of the counter 57, and is supplied to the count enable terminal T of the counter 59.
  • the counter 59 is incremented by +1 in synchronism with the CLK1.
  • signals "1", "0” are respectively delivered from the output terminals Qc, Qd of the counter 59.
  • Delivered the signal "1" from the output terminal Qc of the counter 59 a "0" signal is supplied to an enable terminal D of the counter 59 via the inverter 63 for stopping count operation thereafter.
  • the signals "1", "0” are delivered without interruption respectively from the output terminals Qc, Qd.
  • the output signal from the output terminal Qc becomes "0” after the VSYNC signal becomes "0", i.e., after the first display is finished and the next display is started.
  • the selector 68 is adapted to permit only an ADD signal to pass therethrough.
  • the counter 58 counts up one by one in synchronism with the CLK2 by a value of the parameter (d), a "1" signal is provided from the carry terminal CA of the counter 58, and thereby a "0" signal (load signal) is supplied to the load terminal L of the counter 58 via the two-input NOR gate 66.
  • the output signal from the register 54 has been supplied to the data input terminal D of the counter 58 via the selector 56. Accordingly, the data held in the register 54 is loaded to the counter 58 owing to the load signal in synchronism with the CLK2.
  • the signal "1" from the carry terminal CA of the counter 58 is also supplied to the count enable terminal T, whereby the counter 60 is updated by +1 in synchronism with the CLK2.
  • a signal "1" is delivered from the output terminal Qd of the counter 60.
  • the counter 58 again counts up one by one in syunchronism with the CLK2.
  • a signal "1" is provided from the carry terminal CA of the counter 58, and thereby a signal "1” is supplied to the enable terminal T of the counter 60.
  • the counter 60 is updated by "1" in synchromism with the CLK2.
  • signals "1", "0" are delivered respectively from the output terminals Qc, Qd of the counter 60.
  • a signal "0" is supplied to the enable terminal P of the counter 60 via the inverter 64 for stopping the count operation therafter.
  • signals "1", "0” are delivered without interruption respectively from the output terminals Qc, Qd.
  • the output signal from the output terminal Qc gets “0” after the CLK1 signal becomes “0", i.e., when the operation transfers to the next raster.
  • the MDISP signal is "1" as described above. Consequently, an output from the three-input AND gate 67 is "0" within a range of a dotted chain line of Fig. 5(a), and otherwise "1".
  • an ADD signal passes through the selector 68 in the area outside the single dot-chain line within the display areaA, while only the output signal from the adder 69 passes through the selector 68 within the single dot-chain line.
  • the display data A' is displayed in the area outside the single dot chain line in the display area A of Fig. 5(a), while the display data B' displayed within the single dot chain line.
  • new data is set to the registers 51, 53, and 70 prior to storing the display.
  • the data includes the vertical positional information (parameter(e)), horizontal positional information (parameter(d)), and the difference (Na1-Na2) between the Nb1 and Na2 of Fig. 6(b).
  • Na' is set to the register 101 a of Fig.1 as a display starting address prior to starting the display. Moreover a difference (Na-Na') between Na and Na' is estimated and added into the contents of the register 70 (a+Na-Na'). Refer to Fig. 8 thereon.
  • New data is set in the registers 52, 54 prior to starting the display.
  • the data is the height information (parameter(c))and the width information(parameter(b)) as described before.
  • Fig. 9 designated at 500 is an address converting part, and 501,502, 503, and 504 are respectively registers. These registers serve to hold address information of the video memory 2. Let us describe here the address information with reference to Fig.10.
  • Fig. 10(a) shows a display state on the screen
  • Fig. 10(b) a storage state of display data in the video memory 2.
  • A is an area to display the display data A'
  • B1 is an area to display the display data B1'
  • H is an area to display the display data H'
  • Na is a head address of the area having is the display data A' stored therein
  • Nbl likewise a head address of the area having the display data B' stored therein
  • Na1 is a head address of the area where superposed display is effected
  • Na2 is a final address of a first raster of the area where superposed display is effected
  • Na3 is a final address of the area where superposed display is effected
  • Na1 is a head address of the area where the superposing display data B1' is stored.
  • the register 501 holds the above address Na1, while the register 502 holds the next address (Na3+1) of the above address Na3. Likewise, the register 503 holds the
  • Fig. 9. Designated at 505 is a register for holding an address number of the raster of the display data A' of Fig. 10(b), 506, 507, 508 and 509 are respectively a comparator, 510, 511, and 512 are a selector, 513, 514, and 515 are an adder, 516, 517 are a register, 518, 519 are a latch, and 520 is a three-input AND gate having the same function as that of the three-input gate 67 of Fig. 4.
  • the MDISP signal is set to "1" to effect the superposed display.
  • the Na1, Na3, Na2, Nb1-Na1, and y are respectively set to the registers 501, 502, 503, 504, and 505.
  • the Na1 and Na2 are respectively set to the registers 516, 517 in synchronism with the CLK2 (raster clock). This is done every time the CLK2 arrives.
  • the latch 518 has been reset, and the selectors 510, 511 has allowed output signals from the resisters 501, 503 to pass therethrough. Changed the ADD signal to the Na1, a coincidence signal is delivered from the comparator 506 to set the latch 518, whereby a signal "1" is provided from the latch 518.
  • a coincidence signal is delivered also from the comparator 508 to set the latch 519, whereby a signal "1" is provided from the latch 519.
  • the selector 512 allows an output signal from the adder 511 to pass therethrough, whereb$the VDD signal gets Nb1 to permit the display data B1 1 to be displayed on the display area B1.
  • the CLK2 is supplied to the registers 516, 517.
  • an output signal (Na1+y) from the adder 514 is set to the register 517.
  • the selectors 510, 511 respectively allow the output signals from the adders 513, 514 to pass therethrough.
  • Changed there the add signal to (Na1+y) the latch 519 is again set to permit the display data B1' to be displayed.
  • changed the ADD signal to (Na2+1+y) the latch 519 is set to permit the display data A' to be displayed.
  • the ADD signal finally gets Na3+1.
  • a coincidence signal is issued from the comparator 507 to reset the latch 518.
  • the display data A' is displayed on the display area A thereafter.
  • the contents of the registers 51, 52, 53, 54 and 70 may be changed every time the VSYNC signal is issued. For example, where only the display location is changed as shown by the arrow 11 of Fig. 11, the contents of the registers 51, 53, and 70 may be changed. Namely, the parameters (e), (d), and (a) may be changed. In addition, when the display data is changed as shown by the arrow 12 of the figure leaving the display location as it is, only the contents of the register 70, i.e., only the parameter (a) may be changed. Moreover, when the display data to be superposed is changed as shown by the arrow 13, the contents of the register 70 i.e., the parameter (a) may be changed. (but, in that case, the contents of the register 101 a of Fig. 1 must be changed in order from Na to Na') (2) When employing the address converting part 500 of Fig. 9.
  • the contents of the registers 501, 502, 503, and 504 may be changed every time the VSYNC signal is issued. For example, when only the display location as shown in arrow ⁇ 1 of Fig. 11 is changed, the contents of the registers 501, 502, 503, and 504 may be changed. In addition, when the display data is changed as shown by the arrow 12 leaving the display location as it is, only the contents of the register 504 may be changed. Moreover, when the display data to be superposed is changed as shown by the arrow 13, only the contents of the register 504 may be changed (but, in that case, the contents of the register 101 of Fig. 1 must be changed in order from Na to Na').

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of El Displays (AREA)
  • Lifting Devices For Agricultural Implements (AREA)
  • Forklifts And Lifting Vehicles (AREA)
  • Soil Working Implements (AREA)
  • Digital Computer Display Output (AREA)
EP86108650A 1985-06-25 1986-06-25 Dispositif de commande d'un appareil d'affichage à balayage à trame Expired - Lifetime EP0206328B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT86108650T ATE90469T1 (de) 1985-06-25 1986-06-25 Steuergeraet fuer eine nach dem rasterverfahren arbeitende anzeigeeinheit.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60136838A JPS61295594A (ja) 1985-06-25 1985-06-25 表示装置の制御方式
JP136838/85 1985-06-25

Publications (3)

Publication Number Publication Date
EP0206328A2 true EP0206328A2 (fr) 1986-12-30
EP0206328A3 EP0206328A3 (en) 1990-05-02
EP0206328B1 EP0206328B1 (fr) 1993-06-09

Family

ID=15184683

Family Applications (1)

Application Number Title Priority Date Filing Date
EP86108650A Expired - Lifetime EP0206328B1 (fr) 1985-06-25 1986-06-25 Dispositif de commande d'un appareil d'affichage à balayage à trame

Country Status (4)

Country Link
EP (1) EP0206328B1 (fr)
JP (1) JPS61295594A (fr)
AT (1) ATE90469T1 (fr)
DE (1) DE3688540T2 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0274439A2 (fr) * 1987-01-07 1988-07-13 Brother Kogyo Kabushiki Kaisha Système de visualisation pour plusieurs zones de visualisation sur un écran
EP0590807A2 (fr) * 1992-10-01 1994-04-06 Hudson Soft Co., Ltd. Appareil de traitement de données de sons et d'images
US5623315A (en) * 1992-09-30 1997-04-22 Hudson Soft Co., Ltd. Computer system for processing sound data
EP2096836A1 (fr) 2008-02-26 2009-09-02 Funai Electric Co., Ltd. Système de distribution d'informations

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63130791U (fr) * 1987-02-17 1988-08-26
JPH01193796A (ja) * 1988-01-29 1989-08-03 Hitachi Ltd 表示制御装置
JPH0213997A (ja) * 1988-07-01 1990-01-18 Matsushita Electric Ind Co Ltd 画像表示制御装置
JPH0285482U (fr) * 1988-12-20 1990-07-04
JP4742508B2 (ja) * 2003-03-31 2011-08-10 セイコーエプソン株式会社 画像表示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984001655A1 (fr) * 1982-10-07 1984-04-26 Western Electric Co Generation dynamique et recouvrement de fenetres graphiques pour multiples zones actives d'implantation de programmes
GB2141908A (en) * 1983-05-25 1985-01-03 Westinghouse Electric Corp Multi-level raster scan display arrangement
GB2144952A (en) * 1983-07-08 1985-03-13 Sharp Kk Multiwindow display circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984001655A1 (fr) * 1982-10-07 1984-04-26 Western Electric Co Generation dynamique et recouvrement de fenetres graphiques pour multiples zones actives d'implantation de programmes
GB2141908A (en) * 1983-05-25 1985-01-03 Westinghouse Electric Corp Multi-level raster scan display arrangement
GB2144952A (en) * 1983-07-08 1985-03-13 Sharp Kk Multiwindow display circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ACM TRANSACTIONS ON GRAPHICS, vol. 2, no. 2, April 1983, pages 135-160, New York, US; R. PIKE: "Graphics in overlapping bitmap layers" *

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0274439A2 (fr) * 1987-01-07 1988-07-13 Brother Kogyo Kabushiki Kaisha Système de visualisation pour plusieurs zones de visualisation sur un écran
EP0274439A3 (en) * 1987-01-07 1989-07-19 Brother Kogyo Kabushiki Kaisha Display system for plural display areas on one screen
US4903013A (en) * 1987-01-07 1990-02-20 Brother Kogyo Kabushiki Kaisha Display system for plural display areas on one screen
US5623315A (en) * 1992-09-30 1997-04-22 Hudson Soft Co., Ltd. Computer system for processing sound data
US5692099A (en) * 1992-09-30 1997-11-25 Hudson Soft Co., Ltd. Computer system including recovery function of ADPCM sound data
US5694518A (en) * 1992-09-30 1997-12-02 Hudson Soft Co., Ltd. Computer system including ADPCM decoder being able to produce sound from middle
US5831681A (en) * 1992-09-30 1998-11-03 Hudson Soft Co., Ltd. Computer system for processing sound data and image data in synchronization with each other
US5845242A (en) * 1992-09-30 1998-12-01 Hudson Soft Co., Ltd. Computer system for processing image and sound data
US6453286B1 (en) 1992-09-30 2002-09-17 Hudson Soft Co., Ltd. Computer system for processing image and sound data using ADPCM stereo coding
EP0590807A2 (fr) * 1992-10-01 1994-04-06 Hudson Soft Co., Ltd. Appareil de traitement de données de sons et d'images
EP0590807A3 (fr) * 1992-10-01 1996-06-05 Hudson Soft Co., Ltd. Appareil de traitement de données de sons et d'images
EP2096836A1 (fr) 2008-02-26 2009-09-02 Funai Electric Co., Ltd. Système de distribution d'informations

Also Published As

Publication number Publication date
EP0206328A3 (en) 1990-05-02
ATE90469T1 (de) 1993-06-15
DE3688540T2 (de) 1993-10-07
DE3688540D1 (de) 1993-07-15
EP0206328B1 (fr) 1993-06-09
JPS61295594A (ja) 1986-12-26

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