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EP0206328B1 - Dispositif de commande d'un appareil d'affichage à balayage à trame - Google Patents

Dispositif de commande d'un appareil d'affichage à balayage à trame Download PDF

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Publication number
EP0206328B1
EP0206328B1 EP86108650A EP86108650A EP0206328B1 EP 0206328 B1 EP0206328 B1 EP 0206328B1 EP 86108650 A EP86108650 A EP 86108650A EP 86108650 A EP86108650 A EP 86108650A EP 0206328 B1 EP0206328 B1 EP 0206328B1
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EP
European Patent Office
Prior art keywords
address
signal
area
display
storing
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EP86108650A
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German (de)
English (en)
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EP0206328A2 (fr
EP0206328A3 (en
Inventor
Nobuyuki Oki Electric Industry Co. Ltd. Sato
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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Priority to AT86108650T priority Critical patent/ATE90469T1/de
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Publication of EP0206328A3 publication Critical patent/EP0206328A3/en
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Publication of EP0206328B1 publication Critical patent/EP0206328B1/fr
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen

Definitions

  • the present invention relates to a control circuit of a raster scanning display unit according to the preamble of claim 1.
  • a control circuit of a display unit of this type is known is for example Japanese Laid-Open Patent Publication No. 60-22184. Let us describe here the control circuit with reference to Fig. 1.
  • Fig. 1 is an illustration partly depicting a control circuit of a display unit.
  • a CRT controller designated at 1 is a CRT controller
  • 2 is a video memory for storing display data
  • 3 is a parallel/serial converter for converting paralled data to serial data, from which a VIDEO signal is delivered.
  • Designated at 4 is a dot clock generator circuit with which the above-described VIDEO signal is synchronized.
  • a CRT controller 1 in detail.
  • Designated at 101a, 101b, ...101h are a register, respectively, each of which holds a display start address.
  • Designated at 102a, 102b, ...102h are a registr, respectively, each of which holds the number of rasters to be displayed.
  • Designated at 103 and 104 are respectively a selector for outputting a desired one among a plurality of input signals
  • 105 is a counter for designating which input signal is outputted to the selecters 103 and 104
  • 106 is a counter for providing an address signal of a video memory 2
  • 107 is a counter for counting a raster signal
  • 108 is a counter for providing an address signal of the video memory 2
  • 109 is selector for providing an address signal of the video memory 2
  • 110 is a mode register for holding two modes of a write mode where display data is written in the video memory 2 and a read mode where display data is read from the video memory
  • 111 is a frequency divider for generating one pulse at every x dot clock with use of a dot clock provided from a dot clock generator circuit 4 as an input signal.
  • An output signal from the frequency divider 111 is hereafter called an address clock (in addition, x dot data is enterd into one address of the video memory 2).
  • an address clock in addition, x dot data is enterd into one address of the video memory 2.
  • a frequency divider for generating one pulse at each y address clock with use of an address clock provided from the frequency divider circuit 111 as an input signal.
  • An output signal from the frequency divider 112 is hereafter called a raster clock (in addition, x.y dot data is displayed per one raster).
  • a CPU sets address data to the counter 108.
  • An address being set here is a head address N1 of a write area.
  • the CPU switches the mode register 110 to a write mode, An output signal from the counter is delivered to an address line 6 while the mode register 110 is operated in the write mode, and hence the above-described head address is supplied to the video memory 2.
  • display data is provided to a data line 8, while a write signal provided to a control line 7, both from a circuit (not shown) of the CRT controller 1.
  • the counter 108 is incremented by +1 to permit the display data to be written into the next address.
  • address data is again set to the counter 108.
  • the address being set here is the head address N2 of the next writer area.
  • display data B is likewise written into the video memory 2.
  • Display data A, B,...H are written in succession into the video memory 2 in this way.
  • the CPU sets display start addresses N1, N2, ...Nm to the registers 101a, 101b,...101h; respectively.
  • raster numbers n1, n2, ..., nm to be displayed are set to be registers 102a, 102b,...102h.
  • the counter 105 is reset to permit an output signal from the register 101a to be delivered from the selector 107, while an output signal from the register 102a to be delivered from the selector 104, and these outputs are set to the respective counters 106, 107,
  • N, and n1 shown in Fig. 2(a) are respectively set to the counters 106 and 107.
  • the mode register 110 is switched to a read mode.
  • An output signal from the counter 106 is delivered onto the address line while the mode register 110 is operated in the read mode.
  • a read signal is provided onto the control line 7 from the circuit (not shown) of the CRT controller 1.
  • Any display data is hereby read from the video memory 2, and delivered onto the data line 8.
  • the above data is converted to serial data through the parallel/serial converter 3 to provide a VIDEO signal. Issued one address display data (x dot) from the parallel/serial converter 3 as the VIDEO signal, the frequency divider 111 provides one pulse.
  • the counter 106 is incremented by +1.
  • any display data is read from the next address (N1+1) of the video memory 2.
  • Document GB 21 44 952 A describes a multiwindow display circuit of a raster scanning display unit. It comprises a picture information memory, conventional address counters for generating a read address of the picture information memory in synchronism with an address clock and an address converter provided between the picture information memory and the address counters.
  • the address converter includes a judging part for judging whether or not the area concerned is a window where a superposed display is effected.
  • Bias registers are provided for storing a difference between a head storage address of superposing display data and a head storage address of superposed display data. Further a full adder for adding an output signal from bias registers to an output signal from said address counter is provided.
  • FIG. 3 Blocks designated by the numerals 1 to 4 in Fig. 3 are the same as those shown in Fig. 1.
  • designated at 5 is an address converting part, whose details are shown in Fig. 4.
  • Fig. 5(a) depicts a display state on the screen, while Fig. 5(b) shows a storage state of display data in the video memory 2.
  • A designates an area of displaying display data A'; B1 an area of displaying display data B1'; H an area of displaying display data H'.
  • Na shows a head address of the area in which the display data A' is stored.
  • Nb shows a headaddress of the area in which the display data B' is stored.
  • Na1 designates a head address of an area where displays are superposed.
  • Nb1 is a head address of an area where the superposed diplay data B'1 is stored.
  • the area B1 where superposition of displays is effected is designated by four parameters: a parameter (e) for showing a vertical position; a parameter (c) for showing a height; a parameter (b) for showing a width; and a parameter (d) for showing a horizontal position.
  • the parameters (c) and (e) are represented by raster numbers, while the parameters (b) and (d) by corresponding address numbers of the video memory 2.
  • the registers 51, 52, 53, and 54 respectively hold complements of the parameters (e), (c), (d), and (b).
  • Fig. 4 designated at 55 and 56 are selectors, and 57, 58, 59 and 60 are counters, for which one corresponding to TI-made SN 74163 for example is employed.
  • the counters 57 and 58 comprise a combination of a prescribed number of counters.
  • Designated at 61, 62, 63, and 64 are inverters, 65, 66 are two-input NOR gates, 67 is a three-input AND gate, 68 is a selector, 69 is an adder, 70 is a register which holds a difference (Nb1-Na1) between the Nb1 and Na1 of Fig.
  • "HL” is a high level signal
  • "SYNC” is a vertical synchronization signal of the display unit
  • "DATA” is a data signal from a CPU (not shown)
  • "CLK1” is the raster clock being an output signal from the frequency divider circuit 112 of Fig. 1
  • CLK2 is the address clock being an output signal from the frequency divider circuit 111 of Fig. 1
  • MDISP is a signal to instruct displays to be superposed, which is availabel from the CPU not shown
  • "ADD” is an output signal from the selector 109 of Fig. 1
  • "VADD" is an address signal of the video memory 2.
  • Fig. 9 designated at 500 is an address converting part, and 501,502, 503, and 504 are respectively registers. These registers serve to hold address information of the video memory 2. Let us describe here the address information with reference to Fig.10.
  • Fig. 10(a) shows a display state on the screen
  • Fig. 10(b) a storage state of display data in the video memory 2.
  • A is an area to display the display data A'
  • B1 is an area to display the display data B1'
  • H is an area to display the display data H'
  • Na is a head address of the area having the display data A' stored therein
  • Nb is likewise a head address of the area having the display data B' stored therein
  • Na1 is a head address of the area where superposed display is effected
  • Na2 is a final address of a first raster of the area where superposed display is effected
  • Na3 is a final address of the area where superposed display is effected
  • Nb1 is a head address of the area where the superposing display data B1' is stored.
  • the register 501 holds the above address Na1, while the register 502 holds the next address (Na3+1) of the above address Na3. Likewise, the register 503 holds
  • Fig. 9. Designated at 505 is a register for holding an address clock number of the raster of the display data A' of Fig. 10(b), 506, 507, 508 and 509 are respectively a comparator, 510, 511, and 512 are a selector, 513, 514, and 515 are an adder, 516, 517 are a register, 518, 519 are a latch, and 520 is a three-input AND gate having the same function as that of the three-input gate 67 of Fig. 4.
  • the MDISP signal is set to "1" to effect the superposed display.
  • the Na1, Na3, Na2, Nb1-Na1, and y are respectively set to the registers 501, 502, 503, 504, and 505.
  • the Na1 and Na2 are respectively set to the registers 516, 517 in synchronism with the CLK2 (raster clock). This is done every time the CLK2 arrives.
  • the latch 518 has been reset, and the selectors 510, 511 has allowed output signals from the resisters 501, 503 to pass therethrough. Changed the ADD signal to the Na1, a coincidence signal is delivered from the comparator 506 to set the latch 518, whereby a signal "1" is provided from the latch 518.
  • a coincidence signal is delivered also from the comparator 508 to set the latch 519, whereby a signal "1" is provided from the latch 519.
  • the selector 512 allows an output signal from the adder 515 to pass there through, whereby the VADD signal gets Nb1 to permit the display data B1' to be displayed on the display area B1.
  • the CLK2 is supplied to the registers 516, 517.
  • an output signal (Na1+y) from the adder 514 is set to the register 517.
  • the selectors 510, 511 respectively allow the output signals from the adders 513, 514 to pass therethrough.
  • Changed there the add signal to (Na1+y) the latch 519 is again set to permit the display data B1' to be displayed.
  • changed the ADD signal to ( Na2+1+y ) the latch 519 is set to permit the display data A' to be displayed.
  • the ADD signal finally gets Na3+1.
  • a coincidence signal is issued from the comparator 507 to reset the latch 518.
  • the display data A' is displayed on the display area A thereafter.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of El Displays (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Soil Working Implements (AREA)
  • Lifting Devices For Agricultural Implements (AREA)
  • Forklifts And Lifting Vehicles (AREA)
  • Digital Computer Display Output (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)

Claims (1)

  1. Circuit de commande d'une unité d'affichage à balayage de trame comportant :
    (1) une mémoire vidéo (2) pour le stockage de données d'affichage ;
    (2) une partie (1) de génération d'adresse de lecture destinée à générer une adresse de lecture de la mémoire vidéo (2) en synchronisme avec un signal d'horloge d'adresse ; et
    (3) une partie (5,500) de conversion d'adresse placée entre la mémoire vidéo (2) et la partie (1) de génération d'adresse de lecture, comprenant :
    (a) une partie d'estimation destinée à estimer si la zone concernée est ou non une zone où un affichage superposé est effectué,
    (b) un moyen à mémoire (70,504) destiné à stocker une différence entre une adresse de stockage de tête de données d'affichage en superposition et une adresse de stockage de tête de données d'affichage superposé,
    (c) un additionneur (69,515) destiné à additionner un signal de sortie dudit moyen à mémoire à un signal de sortie de ladite partie de génération d'adresse de lecture ; caractérisé par
    (d) un moyen sélecteur (68,512) utilisant un signal de sortie de ladite partie de génération d'adresse de lecture et un signal de sortie dudit additionneur (69,515) en tant que signaux d'entrée, et délivrant l'un desdits signaux d'entrée, dans lequel le moyen sélecteur délivre le signal de sortie disponible à partir dudit additionneur (69,515) lorsque la zone concernée est une zone où un affichage superposé est effectué ; et ladite partie de jugement étant constituée :
    (aa) d'un premier moyen à mémoire (501) destiné à stocker une adresse de tête N1 d'une zone prescrite dans laquelle des données d'affichage superposé sont stockées ;
    (ab) un deuxième moyen à mémoire (502) destiné à stocker une valeur N3 donnée en additionnant 1 à une adresse finale de ladite zone prescrite ;
    (ac) un troisième moyen à mémoire (503) destiné à stocker, lorsqu'une largeur d'une zone où un affichage superposé est effectué, est réduite au nombre de signaux d'horloge d'adresse qui est b, une valeur N2=N1+b
    Figure imgb0004
     donnée par l'addition dudit b à ladite adresse de tête N1 ;
    (ad) un quatrième moyen à mémoire (505) destiné à stocker une valeur Y représentant la largeur d'une trame sur un nombre correspondant de signaux d'horloge d'adresse ;
    (ae) un moyen à bascule (518), ledit moyen à bascule étant instauré lorsqu'une adresse provenant de la partie de génération d'adresse de lecture atteint ladite valeur N1, et étant restauré lorsqu'elle atteint N3 ;
    (af) un cinquième moyen à mémoire (516) destiné à stocker ladite valeur N1 lorsque ledit moyen à bascule (518) est restauré, et à stocker une valeur donnée en additionnant y à la valeur de sortie du cinquième moyen à mémoire (516) à chaque fois qu'un signal d'horloge de trame est délivré après que ledit moyen à bascule (518) a été instauré ;
    (ag) un sixième moyen à mémoire (517) destiné à stocker ladite valeur N2 lorsque ledit moyen à bascule (518) est instauré, et à stocker une valeur donnée en additionnant y à la valeur de sortie du sixième moyen à mémoire (517) à chaque fois qu'un signal d'horloge de trame est délivré après que ledit moyen à bascule a été instauré ;
    (ah) un premier comparateur (508) destiné à comparer un signal de sortie dudit cinquième moyen à mémoire à un signal d'adresse provenant de ladite partie de génération d'adresse de lecture ;
    (ai) un second comparateur (509) destiné à comparer un signal de sortie dudit sixième moyen à mémoire à un signal d'adresse provenant de ladite partie de génération d'adresse de lecture ;
    (aj) un second moyen à bascule (519), ledit second moyen à bascule étant instauré par un signal de coïncidence provenant dudit premier comparateur alors qu'il est restauré par un signal de coïncidence provenant dudit second comparateur ; et
    (ak) un moyen de désignation destiné à désigner que la zone concernée est une zone où un affichage superposé est effectué lorsque lesdits deux moyens à bascule sont tous deux instaurés.
EP86108650A 1985-06-25 1986-06-25 Dispositif de commande d'un appareil d'affichage à balayage à trame Expired - Lifetime EP0206328B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT86108650T ATE90469T1 (de) 1985-06-25 1986-06-25 Steuergeraet fuer eine nach dem rasterverfahren arbeitende anzeigeeinheit.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP136838/85 1985-06-25
JP60136838A JPS61295594A (ja) 1985-06-25 1985-06-25 表示装置の制御方式

Publications (3)

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EP0206328A2 EP0206328A2 (fr) 1986-12-30
EP0206328A3 EP0206328A3 (en) 1990-05-02
EP0206328B1 true EP0206328B1 (fr) 1993-06-09

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EP86108650A Expired - Lifetime EP0206328B1 (fr) 1985-06-25 1986-06-25 Dispositif de commande d'un appareil d'affichage à balayage à trame

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EP (1) EP0206328B1 (fr)
JP (1) JPS61295594A (fr)
AT (1) ATE90469T1 (fr)
DE (1) DE3688540T2 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63169687A (ja) * 1987-01-07 1988-07-13 ブラザー工業株式会社 表示装置
JPS63130791U (fr) * 1987-02-17 1988-08-26
JPH01193796A (ja) * 1988-01-29 1989-08-03 Hitachi Ltd 表示制御装置
JPH0213997A (ja) * 1988-07-01 1990-01-18 Matsushita Electric Ind Co Ltd 画像表示制御装置
JPH0285482U (fr) * 1988-12-20 1990-07-04
DE69328399T2 (de) * 1992-09-30 2000-10-19 Hudson Soft Co. Ltd., Sapporo Sprachdaten-Verarbeitung
US5459485A (en) * 1992-10-01 1995-10-17 Hudson Soft Co., Ltd. Image and sound processing apparatus
JP4742508B2 (ja) * 2003-03-31 2011-08-10 セイコーエプソン株式会社 画像表示装置
JP2009206601A (ja) 2008-02-26 2009-09-10 Funai Electric Co Ltd 情報配信システム

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4555775B1 (en) * 1982-10-07 1995-12-05 Bell Telephone Labor Inc Dynamic generation and overlaying of graphic windows for multiple active program storage areas
US4554538A (en) * 1983-05-25 1985-11-19 Westinghouse Electric Corp. Multi-level raster scan display system
US4780710A (en) * 1983-07-08 1988-10-25 Sharp Kabushiki Kaisha Multiwindow display circuit

Also Published As

Publication number Publication date
EP0206328A2 (fr) 1986-12-30
EP0206328A3 (en) 1990-05-02
JPS61295594A (ja) 1986-12-26
DE3688540T2 (de) 1993-10-07
ATE90469T1 (de) 1993-06-15
DE3688540D1 (de) 1993-07-15

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