DE69724742D1 - Speicherfeldprüfschaltung mit Fehlermeldung - Google Patents
Speicherfeldprüfschaltung mit FehlermeldungInfo
- Publication number
- DE69724742D1 DE69724742D1 DE69724742T DE69724742T DE69724742D1 DE 69724742 D1 DE69724742 D1 DE 69724742D1 DE 69724742 T DE69724742 T DE 69724742T DE 69724742 T DE69724742 T DE 69724742T DE 69724742 D1 DE69724742 D1 DE 69724742D1
- Authority
- DE
- Germany
- Prior art keywords
- failure signal
- test circuit
- output line
- circuit
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/40—Response verification devices using compression techniques
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US3205696P | 1996-11-27 | 1996-11-27 | |
| US32056P | 1996-11-27 | ||
| US3185196P | 1996-12-05 | 1996-12-05 | |
| US31851P | 1996-12-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69724742D1 true DE69724742D1 (de) | 2003-10-16 |
| DE69724742T2 DE69724742T2 (de) | 2004-08-05 |
Family
ID=26707691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69724742T Expired - Lifetime DE69724742T2 (de) | 1996-11-27 | 1997-11-26 | Speicherfeldprüfschaltung mit Fehlermeldung |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5946245A (de) |
| EP (1) | EP0845788B1 (de) |
| JP (2) | JP4002646B2 (de) |
| DE (1) | DE69724742T2 (de) |
| TW (1) | TW360791B (de) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6014759A (en) | 1997-06-13 | 2000-01-11 | Micron Technology, Inc. | Method and apparatus for transferring test data from a memory array |
| US6044429A (en) | 1997-07-10 | 2000-03-28 | Micron Technology, Inc. | Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths |
| JPH11265597A (ja) * | 1998-01-16 | 1999-09-28 | Mitsubishi Electric Corp | 半導体集積回路装置 |
| US6405280B1 (en) | 1998-06-05 | 2002-06-11 | Micron Technology, Inc. | Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence |
| KR100359157B1 (ko) | 1998-12-30 | 2003-01-24 | 주식회사 하이닉스반도체 | 라이트 명령어 레이턴시회로 및 그 제어방법 |
| KR100318266B1 (ko) * | 1999-06-28 | 2001-12-24 | 박종섭 | 출력 데이터 압축방법 및 패킷명령어 구동형 메모리소자 |
| KR100318263B1 (ko) | 1999-06-28 | 2001-12-24 | 박종섭 | 패킷명령어 구동형 메모리소자 |
| US6735729B1 (en) * | 1999-08-18 | 2004-05-11 | Micron Technology, Inc | Compression circuit for testing a memory device |
| US6259639B1 (en) * | 2000-02-16 | 2001-07-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device capable of repairing defective parts in a large-scale memory |
| US6904552B2 (en) * | 2001-03-15 | 2005-06-07 | Micron Technolgy, Inc. | Circuit and method for test and repair |
| US20020133769A1 (en) * | 2001-03-15 | 2002-09-19 | Cowles Timothy B. | Circuit and method for test and repair |
| US6876591B2 (en) * | 2001-04-25 | 2005-04-05 | Koninklijke Philips Electronics N.V. | Integrated circuit with self-test device for an embedded non-volatile memory and related test method |
| DE10148521B4 (de) * | 2001-10-01 | 2010-01-28 | Qimonda Ag | Integrierter Speicher sowie Verfahren zum Betrieb eines integrierten Speichers und eines Speichersystems mit mehreren integrierten Speichern |
| US7055076B2 (en) * | 2002-08-28 | 2006-05-30 | Micron Technology, Inc. | Output data compression scheme using tri-state |
| DE102005011893B3 (de) * | 2005-03-15 | 2006-09-21 | Infineon Technologies Ag | Halbleiterspeicherbauelement und Verfahren zum Prüfen von Halbleiterspeicherbauelementen mit eingeschränktem Speicherbereich (Partial-Good-Memorys) |
| US7630259B1 (en) * | 2007-12-18 | 2009-12-08 | Lattice Semiconductor Corporation | Programmable logic device with built in self test |
| US8516185B2 (en) * | 2009-07-16 | 2013-08-20 | Netlist, Inc. | System and method utilizing distributed byte-wise buffers on a memory module |
| US8422324B2 (en) * | 2011-08-26 | 2013-04-16 | Nanya Technology Corp. | Method and apparatus for sending test mode signals |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4878209A (en) * | 1988-03-17 | 1989-10-31 | International Business Machines Corporation | Macro performance test |
| JPH0684398A (ja) * | 1992-05-27 | 1994-03-25 | Nec Corp | 半導体メモリ装置 |
| JP3400824B2 (ja) * | 1992-11-06 | 2003-04-28 | 三菱電機株式会社 | 半導体記憶装置 |
| JPH06275098A (ja) * | 1993-03-24 | 1994-09-30 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP3346827B2 (ja) * | 1993-05-25 | 2002-11-18 | 三菱電機株式会社 | 同期型半導体記憶装置 |
| JPH0816486A (ja) * | 1994-06-29 | 1996-01-19 | Hitachi Ltd | 欠陥救済用ｌｓｉとメモリ装置 |
| JP2833563B2 (ja) * | 1996-01-23 | 1998-12-09 | 日本電気株式会社 | 半導体記憶装置 |
| US5812472A (en) * | 1997-07-16 | 1998-09-22 | Tanisys Technology, Inc. | Nested loop method of identifying synchronous memories |
-
1997
- 1997-11-26 DE DE69724742T patent/DE69724742T2/de not_active Expired - Lifetime
- 1997-11-26 EP EP97120774A patent/EP0845788B1/de not_active Expired - Lifetime
- 1997-11-26 US US08/980,098 patent/US5946245A/en not_active Expired - Lifetime
- 1997-11-27 JP JP32623397A patent/JP4002646B2/ja not_active Expired - Lifetime
-
1998
- 1998-02-09 TW TW086118005A patent/TW360791B/zh not_active IP Right Cessation
-
2007
- 2007-04-04 JP JP2007098602A patent/JP2007188633A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JP4002646B2 (ja) | 2007-11-07 |
| JPH10188600A (ja) | 1998-07-21 |
| DE69724742T2 (de) | 2004-08-05 |
| EP0845788A2 (de) | 1998-06-03 |
| US5946245A (en) | 1999-08-31 |
| EP0845788A3 (de) | 1999-06-09 |
| JP2007188633A (ja) | 2007-07-26 |
| EP0845788B1 (de) | 2003-09-10 |
| TW360791B (en) | 1999-06-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |