DE69129445D1 - Integrierte halbleiterschaltungsanordnung - Google Patents

Integrierte halbleiterschaltungsanordnung

Info

Publication number: DE69129445D1
Authority: DE; Germany
Prior art keywords: circuit arrangement; semiconductor circuit; integrated semiconductor; integrated; arrangement
Prior art date: 1990-07-23
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

DE69129445T

Other languages

English (en)

Other versions

DE69129445T2 (de

Inventor

Minoru Sasaki

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Seiko Epson Corp

Original Assignee

Seiko Epson Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1990-07-23

Filing date

1991-07-19

Publication date

1998-06-25

1991-07-19 Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp

1998-06-25 Publication of DE69129445D1 publication Critical patent/DE69129445D1/de

1998-11-26 Application granted granted Critical

1998-11-26 Publication of DE69129445T2 publication Critical patent/DE69129445T2/de

2011-07-20 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Classifications

- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/211—Design considerations for internal polarisation
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts

DE69129445T 1990-07-23 1991-07-19 Integrierte halbleiterschaltungsanordnung Expired - Fee Related DE69129445T2 (de)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
JP19423790		1990-07-23
PCT/JP1991/000970 WO1992002043A1 (fr)	1990-07-23	1991-07-19	Dispositif a circuits integres a semi-conducteurs

Publications (2)

Publication Number	Publication Date
DE69129445D1 true DE69129445D1 (de)	1998-06-25
DE69129445T2 DE69129445T2 (de)	1998-11-26

Family

ID=16321260

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE69129445T Expired - Fee Related DE69129445T2 (de)	1990-07-23	1991-07-19	Integrierte halbleiterschaltungsanordnung

Country Status (6)

Country	Link
US (1)	US5378925A (de)
EP (1)	EP0493615B1 (de)
JP (1)	JP3182762B2 (de)
KR (1)	KR100247267B1 (de)
DE (1)	DE69129445T2 (de)
WO (1)	WO1992002043A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JP4027438B2 (ja)	1995-05-25	2007-12-26	三菱電機株式会社	半導体装置
KR0172426B1 (ko) *	1995-12-21	1999-03-30	김광호	반도체 메모리장치
US5808900A (en) *	1996-04-30	1998-09-15	Lsi Logic Corporation	Memory having direct strap connection to power supply
JPH1092857A (ja)	1996-09-10	1998-04-10	Mitsubishi Electric Corp	半導体パッケージ
US6344667B1 (en) *	1998-03-02	2002-02-05	Kabushiki Kaisha Toshiba	Wiring board with reduced radiation of undesired electromagnetic waves
DE19906382A1 (de)	1999-02-16	2000-08-24	Siemens Ag	Halbleiterspeicher mit Speicherbänken
JP3913927B2 (ja) *	1999-04-19	2007-05-09	富士通株式会社	半導体集積回路装置
KR100715970B1 (ko) *	2001-03-08	2007-05-08	삼성전자주식회사	메모리 모듈
US6598216B2 (en)	2001-08-08	2003-07-22	International Business Machines Corporation	Method for enhancing a power bus in I/O regions of an ASIC device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS5840344B2 (ja) *	1980-06-10	1983-09-05	富士通株式会社	半導体記憶装置
JPS60182742A (ja) *	1984-02-29	1985-09-18	Fujitsu Ltd	集積回路
JPS61241964A (ja) *	1985-04-19	1986-10-28	Hitachi Ltd	半導体装置
JPS6344742A (ja) *	1986-08-12	1988-02-25	Fujitsu Ltd	半導体装置
JPS63199444A (ja) *	1987-02-16	1988-08-17	Oki Electric Ind Co Ltd	標準セル方式半導体装置
JPS63188949U (de) *	1987-05-27	1988-12-05
JP2606845B2 (ja) *	1987-06-19	1997-05-07	富士通株式会社	半導体集積回路
JPH02268439A (ja) *	1989-04-10	1990-11-02	Hitachi Ltd	半導体集積回路装置

1991
- 1991-07-19 EP EP91913084A patent/EP0493615B1/de not_active Expired - Lifetime
- 1991-07-19 JP JP51285391A patent/JP3182762B2/ja not_active Expired - Fee Related
- 1991-07-19 DE DE69129445T patent/DE69129445T2/de not_active Expired - Fee Related
- 1991-07-19 US US07/842,352 patent/US5378925A/en not_active Expired - Lifetime
- 1991-07-19 WO PCT/JP1991/000970 patent/WO1992002043A1/ja active IP Right Grant
- 1991-07-19 KR KR1019920700623A patent/KR100247267B1/ko not_active IP Right Cessation

Also Published As

Publication number	Publication date
JP3182762B2 (ja)	2001-07-03
EP0493615A1 (de)	1992-07-08
EP0493615A4 (de)	1994-02-16
WO1992002043A1 (fr)	1992-02-06
KR100247267B1 (ko)	2000-03-15
US5378925A (en)	1995-01-03
DE69129445T2 (de)	1998-11-26
EP0493615B1 (de)	1998-05-20
KR920702552A (ko)	1992-09-04

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Legal Events

Date	Code	Title	Description
1999-06-17	8364	No opposition during term of opposition
2009-06-04	8339	Ceased/non-payment of the annual fee