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DE69327357D1 - Integrierte Halbleiterschaltungsanordnung - Google Patents

Integrierte Halbleiterschaltungsanordnung

Info

Publication number
DE69327357D1
DE69327357D1 DE69327357T DE69327357T DE69327357D1 DE 69327357 D1 DE69327357 D1 DE 69327357D1 DE 69327357 T DE69327357 T DE 69327357T DE 69327357 T DE69327357 T DE 69327357T DE 69327357 D1 DE69327357 D1 DE 69327357D1
Authority
DE
Germany
Prior art keywords
circuit arrangement
semiconductor circuit
integrated semiconductor
integrated
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69327357T
Other languages
English (en)
Other versions
DE69327357T2 (de
Inventor
Izumi Sakai
Yukinori Uchino
Yasunori Tanaka
Toshiaki Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69327357D1 publication Critical patent/DE69327357D1/de
Publication of DE69327357T2 publication Critical patent/DE69327357T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/211—Design considerations for internal polarisation
    • H10D89/213—Design considerations for internal polarisation in field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/998—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE69327357T 1992-03-31 1993-03-31 Integrierte Halbleiterschaltungsanordnung Expired - Fee Related DE69327357T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10595792 1992-03-31
JP35362692A JP3228583B2 (ja) 1992-03-31 1992-12-14 半導体集積回路装置

Publications (2)

Publication Number Publication Date
DE69327357D1 true DE69327357D1 (de) 2000-01-27
DE69327357T2 DE69327357T2 (de) 2000-06-08

Family

ID=26446179

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69327357T Expired - Fee Related DE69327357T2 (de) 1992-03-31 1993-03-31 Integrierte Halbleiterschaltungsanordnung

Country Status (5)

Country Link
US (1) US5347150A (de)
EP (1) EP0563921B1 (de)
JP (1) JP3228583B2 (de)
KR (1) KR970004454B1 (de)
DE (1) DE69327357T2 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2822781B2 (ja) * 1992-06-11 1998-11-11 三菱電機株式会社 マスタスライス方式半導体集積回路装置
US5691218A (en) * 1993-07-01 1997-11-25 Lsi Logic Corporation Method of fabricating a programmable polysilicon gate array base cell structure
US5552333A (en) * 1994-09-16 1996-09-03 Lsi Logic Corporation Method for designing low profile variable width input/output cells
JP3520659B2 (ja) * 1995-03-30 2004-04-19 セイコーエプソン株式会社 複数の電源電圧で駆動されるゲートアレイ及びそれを用いた電子機器
US5751015A (en) 1995-11-17 1998-05-12 Micron Technology, Inc. Semiconductor reliability test chip
JP3434398B2 (ja) * 1995-11-28 2003-08-04 三菱電機株式会社 半導体装置
JP3294490B2 (ja) * 1995-11-29 2002-06-24 株式会社日立製作所 Ｂｇａ型半導体装置
US6734545B1 (en) * 1995-11-29 2004-05-11 Hitachi, Ltd. BGA type semiconductor device and electronic equipment using the same
US5760428A (en) * 1996-01-25 1998-06-02 Lsi Logic Corporation Variable width low profile gate array input/output architecture
US5698873A (en) * 1996-03-08 1997-12-16 Lsi Logic Corporation High density gate array base cell architecture
US5862390A (en) * 1996-03-15 1999-01-19 S3 Incorporated Mixed voltage, multi-rail, high drive, low noise, adjustable slew rate input/output buffer
US6147511A (en) 1996-05-28 2000-11-14 Altera Corporation Overvoltage-tolerant interface for integrated circuits
US6414518B1 (en) * 1996-05-28 2002-07-02 Altera Corporation Circuitry for a low internal voltage integrated circuit
JP3962441B2 (ja) * 1996-09-24 2007-08-22 富士通株式会社 半導体装置
US5880605A (en) * 1996-11-12 1999-03-09 Lsi Logic Corporation Low-power 5 volt tolerant input buffer
DE59813458D1 (de) 1997-05-15 2006-05-11 Infineon Technologies Ag Integrierte cmos-schaltungsanordnung und verfahren zu deren herstellung
TW360962B (en) * 1998-02-16 1999-06-11 Faraday Tech Corp Chip with hybrid input/output slot structure
US6114731A (en) * 1998-03-27 2000-09-05 Adaptec, Inc. Low capacitance ESD structure having a source inside a well and the bottom portion of the drain inside a substrate
US6078068A (en) * 1998-07-15 2000-06-20 Adaptec, Inc. Electrostatic discharge protection bus/die edge seal
US6242814B1 (en) * 1998-07-31 2001-06-05 Lsi Logic Corporation Universal I/O pad structure for in-line or staggered wire bonding or arrayed flip-chip assembly
US6111310A (en) * 1998-09-30 2000-08-29 Lsi Logic Corporation Radially-increasing core power bus grid architecture
JP3236583B2 (ja) * 1999-06-24 2001-12-10 ローム株式会社 半導体集積回路装置
US6979908B1 (en) * 2000-01-11 2005-12-27 Texas Instruments Incorporated Input/output architecture for integrated circuits with efficient positioning of integrated circuit elements
JP4071914B2 (ja) * 2000-02-25 2008-04-02 沖電気工業株式会社 半導体素子及びこれを用いた半導体装置
US20050285281A1 (en) * 2004-06-29 2005-12-29 Simmons Asher L Pad-limited integrated circuit
EP1638145A1 (de) 2004-09-20 2006-03-22 Infineon Technologies AG Schaltbarer integrierter Versorgungsring
JP2007027314A (ja) * 2005-07-14 2007-02-01 Nec Electronics Corp 半導体集積回路装置
KR100798896B1 (ko) * 2007-06-07 2008-01-29 주식회사 실리콘웍스 반도체 칩의 패드 배치 구조
JP2015053399A (ja) * 2013-09-06 2015-03-19 株式会社東芝 集積回路装置
JP7093020B2 (ja) * 2017-05-15 2022-06-29 株式会社ソシオネクスト 半導体集積回路装置
CN109690769B (zh) * 2018-11-01 2019-12-10 长江存储科技有限责任公司 集成电路静电放电总线结构和相关方法
US10809789B1 (en) * 2019-07-17 2020-10-20 Dell Products L.P. Peripheral component protection in information handling systems

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3916430A (en) * 1973-03-14 1975-10-28 Rca Corp System for eliminating substrate bias effect in field effect transistor circuits
JPS61264747A (ja) * 1985-05-20 1986-11-22 Matsushita Electronics Corp 半導体装置
JPS62128544A (ja) * 1985-11-29 1987-06-10 Nec Corp ゲ−トアレイ型半導体集積回路装置
JPS62261144A (ja) * 1986-05-07 1987-11-13 Mitsubishi Electric Corp 半導体集積回路
JPH0262063A (ja) * 1988-08-26 1990-03-01 Nec Corp 半導体集積回路
JPH02152254A (ja) * 1988-12-02 1990-06-12 Mitsubishi Electric Corp 半導体集積回路装置
JPH02170461A (ja) * 1988-12-22 1990-07-02 Nec Corp 半導体集積回路装置

Also Published As

Publication number Publication date
JPH05335502A (ja) 1993-12-17
KR970004454B1 (ko) 1997-03-27
US5347150A (en) 1994-09-13
KR930020662A (ko) 1993-10-20
DE69327357T2 (de) 2000-06-08
EP0563921A2 (de) 1993-10-06
JP3228583B2 (ja) 2001-11-12
EP0563921B1 (de) 1999-12-22
EP0563921A3 (de) 1994-05-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee