DE69128334D1 - Integrierte Schaltung und Verfahren zu deren Herstellung - Google Patents
Integrierte Schaltung und Verfahren zu deren HerstellungInfo
- Publication number
- DE69128334D1 DE69128334D1 DE69128334T DE69128334T DE69128334D1 DE 69128334 D1 DE69128334 D1 DE 69128334D1 DE 69128334 T DE69128334 T DE 69128334T DE 69128334 T DE69128334 T DE 69128334T DE 69128334 D1 DE69128334 D1 DE 69128334D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacture
- integrated circuit
- integrated
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/5328—Conductive materials containing conductive organic materials or pastes, e.g. conductive adhesives, inks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
- H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
- H01B1/06—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors mainly consisting of other non-metallic substances
- H01B1/12—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors mainly consisting of other non-metallic substances organic substances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
- H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
- H01B1/06—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors mainly consisting of other non-metallic substances
- H01B1/12—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors mainly consisting of other non-metallic substances organic substances
- H01B1/124—Intrinsically conductive polymers
- H01B1/128—Intrinsically conductive polymers comprising six-membered aromatic rings in the main chain, e.g. polyanilines, polyphenylenes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/485—Adaptation of interconnections, e.g. engineering charges, repair techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
- H01L23/5254—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/032—Materials
- H05K2201/0329—Intrinsically conductive polymer [ICP]; Semiconductive polymer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
- H05K2203/107—Using laser light
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1136—Conversion of insulating material into conductive material, e.g. by pyrolysis
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/105—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by conversion of non-conductive material on or in the support into conductive material, e.g. by using an energy beam
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Formation Of Insulating Films (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/590,259 US5689428A (en) | 1990-09-28 | 1990-09-28 | Integrated circuits, transistors, data processing systems, printed wiring boards, digital computers, smart power devices, and processes of manufacture |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69128334D1 true DE69128334D1 (de) | 1998-01-15 |
DE69128334T2 DE69128334T2 (de) | 1998-08-06 |
Family
ID=24361519
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69128334T Expired - Fee Related DE69128334T2 (de) | 1990-09-28 | 1991-09-27 | Integrierte Schaltung und Verfahren zu deren Herstellung |
Country Status (5)
Country | Link |
---|---|
US (2) | US5689428A (de) |
EP (1) | EP0478368B1 (de) |
JP (1) | JP3396488B2 (de) |
KR (1) | KR100270414B1 (de) |
DE (1) | DE69128334T2 (de) |
Families Citing this family (29)
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EP0615257B1 (de) * | 1993-03-09 | 1999-06-02 | Koninklijke Philips Electronics N.V. | Methode zur Herstellung eines Verbundstoffes mit einer Metallschicht auf einer leitfähigen Polymerschicht |
EP0615256B1 (de) * | 1993-03-09 | 1998-09-23 | Koninklijke Philips Electronics N.V. | Herstellungsverfahren eines Musters von einem elektrisch leitfähigen Polymer auf einer Substratoberfläche und Metallisierung eines solchen Musters |
US5567550A (en) * | 1993-03-25 | 1996-10-22 | Texas Instruments Incorporated | Method of making a mask for making integrated circuits |
DE69433124T2 (de) | 1993-11-05 | 2004-05-27 | Intergraph Corp., Huntsville | Befehlsspeicher mit assoziativem Kreuzschienenschalter |
JP3503787B2 (ja) * | 1996-01-22 | 2004-03-08 | 貢 英 | 薄膜の形成方法 |
US5870176A (en) * | 1996-06-19 | 1999-02-09 | Sandia Corporation | Maskless lithography |
JP2002504240A (ja) * | 1997-06-12 | 2002-02-05 | ゼットフォリエ ビー.ブイ. | その表面に対し垂直な一方向の導電性をもつ基板を含む装置、及び該装置を製造する方法 |
WO1999010929A2 (en) * | 1997-08-22 | 1999-03-04 | Koninklijke Philips Electronics N.V. | A method of providing a vertical interconnect between thin film microelectronic devices |
CN1187793C (zh) * | 1998-01-28 | 2005-02-02 | 薄膜电子有限公司 | 制作导电或半导电三维结构的方法和擦除该结构的方法 |
US6323067B1 (en) * | 1999-01-28 | 2001-11-27 | Infineon Technologies North America Corp. | Light absorption layer for laser blown fuses |
US6486051B1 (en) * | 1999-03-17 | 2002-11-26 | Intel Corporation | Method for relieving bond stress in an under-bond-pad resistor |
JP2003513475A (ja) | 1999-11-02 | 2003-04-08 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 薄膜超小型電子装置間の垂直相互接続を形成する方法及びそのような垂直相互接続を備えた製品 |
US6521972B1 (en) * | 2000-09-28 | 2003-02-18 | Eic Corporation | RF power transistor having low parasitic impedance input feed structure |
DE10048243A1 (de) * | 2000-09-29 | 2002-04-18 | Bosch Gmbh Robert | Substrat mit geglätteter Oberfläche und Verfahren zu seiner Herstellung |
US6864118B2 (en) * | 2002-01-28 | 2005-03-08 | Hewlett-Packard Development Company, L.P. | Electronic devices containing organic semiconductor materials |
EP1470449A1 (de) * | 2002-01-31 | 2004-10-27 | Scandinavian Micro Biodevices A/S | Verfahren zur verbindung von einem bauteil an einer mikrostruktur durch lichtbestrahlung |
US6784017B2 (en) * | 2002-08-12 | 2004-08-31 | Precision Dynamics Corporation | Method of creating a high performance organic semiconductor device |
US6890050B2 (en) * | 2002-08-20 | 2005-05-10 | Palo Alto Research Center Incorporated | Method for the printing of homogeneous electronic material with a multi-ejector print head |
US6924661B2 (en) | 2003-02-10 | 2005-08-02 | International Business Machines Corporation | Power switch circuit sizing technique |
US7701323B1 (en) * | 2003-05-30 | 2010-04-20 | Interconnect Portfolio Llc | Low profile discrete electronic components and applications of same |
JP4106438B2 (ja) * | 2003-06-20 | 2008-06-25 | 独立行政法人産業技術総合研究所 | 多層微細配線インターポーザおよびその製造方法 |
US7012013B1 (en) * | 2003-12-03 | 2006-03-14 | Advanced Micro Devices, Inc. | Dielectric pattern formation for organic electronic devices |
US7203036B2 (en) * | 2004-07-30 | 2007-04-10 | Hitachi Global Storage Technologies Netherlands B.V. | Planar extraordinary magnetoresistance sensor |
JP4705771B2 (ja) * | 2004-08-30 | 2011-06-22 | 三菱電機株式会社 | 半導体装置の製造方法 |
JP4655891B2 (ja) * | 2005-11-02 | 2011-03-23 | ソニー株式会社 | 通信用半導体チップ、キャリブレーション方法、並びにプログラム |
US7488950B2 (en) * | 2006-06-05 | 2009-02-10 | Blaise Laurent Mouttet | Crosswire sensor |
CN104094403B (zh) * | 2011-12-23 | 2017-03-22 | 英特尔公司 | 具有使用者可选值的工艺可调式电阻器 |
JP6715508B2 (ja) * | 2016-03-09 | 2020-07-01 | 国立大学法人静岡大学 | 金属微細構造体の製造方法 |
EP3723459A1 (de) | 2019-04-10 | 2020-10-14 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Komponententräger mit hoher passiver intermodulationsleistung (pim) |
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US5567550A (en) * | 1993-03-25 | 1996-10-22 | Texas Instruments Incorporated | Method of making a mask for making integrated circuits |
-
1990
- 1990-09-28 US US07/590,259 patent/US5689428A/en not_active Expired - Lifetime
-
1991
- 1991-09-27 DE DE69128334T patent/DE69128334T2/de not_active Expired - Fee Related
- 1991-09-27 EP EP91308860A patent/EP0478368B1/de not_active Expired - Lifetime
- 1991-09-27 KR KR1019910016882A patent/KR100270414B1/ko not_active IP Right Cessation
- 1991-09-30 JP JP25209291A patent/JP3396488B2/ja not_active Expired - Fee Related
-
1995
- 1995-06-07 US US08/485,412 patent/US6246102B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR100270414B1 (ko) | 2000-11-01 |
EP0478368B1 (de) | 1997-12-03 |
US5689428A (en) | 1997-11-18 |
JP3396488B2 (ja) | 2003-04-14 |
JPH06204221A (ja) | 1994-07-22 |
EP0478368A1 (de) | 1992-04-01 |
DE69128334T2 (de) | 1998-08-06 |
KR920007195A (ko) | 1992-04-28 |
US6246102B1 (en) | 2001-06-12 |
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