DE69123719D1 - Zweifache Speicherzelle mit verbesserter Informationsübertragungsschaltung - Google Patents
Zweifache Speicherzelle mit verbesserter InformationsübertragungsschaltungInfo
- Publication number
- DE69123719D1 DE69123719D1 DE69123719T DE69123719T DE69123719D1 DE 69123719 D1 DE69123719 D1 DE 69123719D1 DE 69123719 T DE69123719 T DE 69123719T DE 69123719 T DE69123719 T DE 69123719T DE 69123719 D1 DE69123719 D1 DE 69123719D1
- Authority
- DE
- Germany
- Prior art keywords
- memory cell
- information transmission
- transmission circuit
- improved information
- double memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/661,555 US5053996A (en) | 1991-02-26 | 1991-02-26 | Dual state memory storage cell with improved data transfer circuitry |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69123719D1 true DE69123719D1 (de) | 1997-01-30 |
| DE69123719T2 DE69123719T2 (de) | 1997-05-22 |
Family
ID=24654104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69123719T Expired - Fee Related DE69123719T2 (de) | 1991-02-26 | 1991-05-31 | Zweifache Speicherzelle mit verbesserter Informationsübertragungsschaltung |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5053996A (de) |
| EP (1) | EP0501057B1 (de) |
| JP (1) | JPH04278292A (de) |
| DE (1) | DE69123719T2 (de) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5361033A (en) * | 1991-07-25 | 1994-11-01 | Texas Instruments Incorporated | On chip bi-stable power-spike detection circuit |
| US5581501A (en) * | 1995-08-17 | 1996-12-03 | Altera Corporation | Nonvolatile SRAM cells and cell arrays |
| US6005806A (en) | 1996-03-14 | 1999-12-21 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
| US6018476A (en) * | 1996-09-16 | 2000-01-25 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
| US6044010A (en) * | 1998-10-05 | 2000-03-28 | National Semiconductor Corporation | Five transistor SRAM cell |
| KR100406760B1 (ko) * | 2001-11-16 | 2003-11-21 | 신코엠 주식회사 | 반도체 메모리 장치 |
| US7109751B1 (en) | 2004-06-02 | 2006-09-19 | Xilinx, Inc. | Methods of implementing phase shift mask compliant static memory cell circuits |
| US7053652B1 (en) * | 2004-06-02 | 2006-05-30 | Xilinx, Inc. | Static memory cell circuit with single bit line and set/reset write function |
| US7071737B2 (en) * | 2004-07-13 | 2006-07-04 | Kabushiki Kaisha Toshiba | Systems and methods for controlling timing in a circuit |
| US7034577B2 (en) * | 2004-07-30 | 2006-04-25 | Kabushiki Kaisha Toshiba | Variable timing circuit |
| US7009871B1 (en) * | 2004-08-18 | 2006-03-07 | Kabushiki Kaisha Toshiba | Stable memory cell |
| JP4456129B2 (ja) * | 2007-01-31 | 2010-04-28 | シャープ株式会社 | 半導体装置および液晶表示装置および電子機器 |
| KR101569540B1 (ko) * | 2008-01-07 | 2015-11-16 | 코에키자이단호우진 신산교소우조우 겐큐키코 | 반도체 메모리 및 프로그램 |
| JP5311309B2 (ja) * | 2009-03-30 | 2013-10-09 | 国立大学法人神戸大学 | 共有キャッシュメモリとそのキャッシュ間のデータ転送方法 |
| JP5256534B2 (ja) * | 2009-03-30 | 2013-08-07 | 国立大学法人神戸大学 | 半導体メモリのメモリセル間のデータコピー方法 |
| JP5397843B2 (ja) * | 2009-08-18 | 2014-01-22 | 国立大学法人神戸大学 | キャッシュメモリとそのモード切替方法 |
| US8362807B2 (en) * | 2010-10-13 | 2013-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Offset compensation for sense amplifiers |
| US8542551B2 (en) | 2011-07-29 | 2013-09-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Circuit and method for reducing leakage current |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62291168A (ja) * | 1986-06-11 | 1987-12-17 | Seiko Instr & Electronics Ltd | 不揮発性ｒａｍ |
| US4873665A (en) * | 1988-06-07 | 1989-10-10 | Dallas Semiconductor Corporation | Dual storage cell memory including data transfer circuits |
| US5031146A (en) * | 1988-12-22 | 1991-07-09 | Digital Equipment Corporation | Memory apparatus for multiple processor systems |
-
1991
- 1991-02-26 US US07/661,555 patent/US5053996A/en not_active Expired - Lifetime
- 1991-05-31 EP EP91304952A patent/EP0501057B1/de not_active Expired - Lifetime
- 1991-05-31 DE DE69123719T patent/DE69123719T2/de not_active Expired - Fee Related
- 1991-07-11 JP JP3171385A patent/JPH04278292A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US5053996A (en) | 1991-10-01 |
| DE69123719T2 (de) | 1997-05-22 |
| EP0501057A3 (en) | 1993-08-11 |
| JPH04278292A (ja) | 1992-10-02 |
| EP0501057A2 (de) | 1992-09-02 |
| EP0501057B1 (de) | 1996-12-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |