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DE3883064D1 - Festwertspeicherschaltung. - Google Patents

Festwertspeicherschaltung.

Info

Publication number
DE3883064D1
DE3883064D1 DE8888107527T DE3883064T DE3883064D1 DE 3883064 D1 DE3883064 D1 DE 3883064D1 DE 8888107527 T DE8888107527 T DE 8888107527T DE 3883064 T DE3883064 T DE 3883064T DE 3883064 D1 DE3883064 D1 DE 3883064D1
Authority
DE
Germany
Prior art keywords
memory circuit
fixed memory
fixed
circuit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888107527T
Other languages
English (en)
Other versions
DE3883064T2 (de
Inventor
Yuji Tsuchimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3883064D1 publication Critical patent/DE3883064D1/de
Publication of DE3883064T2 publication Critical patent/DE3883064T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
DE88107527T 1987-05-12 1988-05-10 Festwertspeicherschaltung. Expired - Fee Related DE3883064T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62115314A JPS63279498A (ja) 1987-05-12 1987-05-12 リ−ド・オンリ・メモリ回路

Publications (2)

Publication Number Publication Date
DE3883064D1 true DE3883064D1 (de) 1993-09-16
DE3883064T2 DE3883064T2 (de) 1994-03-10

Family

ID=14659548

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88107527T Expired - Fee Related DE3883064T2 (de) 1987-05-12 1988-05-10 Festwertspeicherschaltung.

Country Status (4)

Country Link
US (1) US4920516A (de)
EP (1) EP0291025B1 (de)
JP (1) JPS63279498A (de)
DE (1) DE3883064T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2573657B2 (ja) * 1988-06-01 1997-01-22 日本電気株式会社 読出専用半導体記憶装置
US5511032A (en) * 1994-05-17 1996-04-23 Waferscale Integration, Inc. Source pre-charge system in a memory array
US5673218A (en) 1996-03-05 1997-09-30 Shepard; Daniel R. Dual-addressed rectifier storage device
JP3123968B2 (ja) * 1998-02-04 2001-01-15 九州日本電気株式会社 半導体記憶装置
US6956757B2 (en) * 2000-06-22 2005-10-18 Contour Semiconductor, Inc. Low cost high density rectifier matrix memory
US7042779B2 (en) * 2004-01-23 2006-05-09 Agere Systems Inc. Method and apparatus for reducing leakage current in a read only memory device using pre-charged sub-arrays
JP4907916B2 (ja) * 2005-07-22 2012-04-04 オンセミコンダクター・トレーディング・リミテッド メモリ
US7646622B2 (en) * 2006-03-23 2010-01-12 Toshiba America Research, Inc. Memory based computation systems and methods of using the same
US7813157B2 (en) * 2007-10-29 2010-10-12 Contour Semiconductor, Inc. Non-linear conductor memory
US20090225621A1 (en) * 2008-03-05 2009-09-10 Shepard Daniel R Split decoder storage array and methods of forming the same
WO2009149061A2 (en) * 2008-06-02 2009-12-10 Contour Semiconductor, Inc. Diode decoder array with non-sequential layout and methods of forming the same
US8325556B2 (en) * 2008-10-07 2012-12-04 Contour Semiconductor, Inc. Sequencing decoder circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60224198A (ja) * 1984-04-23 1985-11-08 Nec Corp プログラマブル半導体集積回路
EP0179351B1 (de) * 1984-10-11 1992-10-07 Hitachi, Ltd. Halbleiterspeicher
US4651302A (en) * 1984-11-23 1987-03-17 International Business Machines Corporation Read only memory including an isolation network connected between the array of memory cells and the output sense amplifier whereby reading speed is enhanced
JPS62214597A (ja) * 1986-03-17 1987-09-21 Fujitsu Ltd 不揮発性メモリ回路
US4819212A (en) * 1986-05-31 1989-04-04 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device with readout test circuitry

Also Published As

Publication number Publication date
JPS63279498A (ja) 1988-11-16
EP0291025B1 (de) 1993-08-11
DE3883064T2 (de) 1994-03-10
EP0291025A2 (de) 1988-11-17
US4920516A (en) 1990-04-24
EP0291025A3 (en) 1990-08-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee