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DE69015879D1 - Verfahren zur Herstellung einer oberflächenmontierbaren Leiterplatte. - Google Patents

Verfahren zur Herstellung einer oberflächenmontierbaren Leiterplatte.

Info

Publication number
DE69015879D1
DE69015879D1 DE69015879T DE69015879T DE69015879D1 DE 69015879 D1 DE69015879 D1 DE 69015879D1 DE 69015879 T DE69015879 T DE 69015879T DE 69015879 T DE69015879 T DE 69015879T DE 69015879 D1 DE69015879 D1 DE 69015879D1
Authority
DE
Germany
Prior art keywords
manufacturing
circuit board
surface mount
mount circuit
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69015879T
Other languages
English (en)
Other versions
DE69015879T2 (de
Inventor
Harumi Tashiro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69015879D1 publication Critical patent/DE69015879D1/de
Application granted granted Critical
Publication of DE69015879T2 publication Critical patent/DE69015879T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10969—Metallic case or integral heatsink of component electrically connected to a pad on PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0228—Cutting, sawing, milling or shearing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/17—Post-manufacturing processes
    • H05K2203/175—Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Die Bonding (AREA)
DE69015879T 1989-05-22 1990-05-21 Verfahren zur Herstellung einer oberflächenmontierbaren Leiterplatte. Expired - Fee Related DE69015879T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1128038A JPH02306690A (ja) 1989-05-22 1989-05-22 表面実装用配線基板の製造方法

Publications (2)

Publication Number Publication Date
DE69015879D1 true DE69015879D1 (de) 1995-02-23
DE69015879T2 DE69015879T2 (de) 1995-05-04

Family

ID=14974977

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69015879T Expired - Fee Related DE69015879T2 (de) 1989-05-22 1990-05-21 Verfahren zur Herstellung einer oberflächenmontierbaren Leiterplatte.

Country Status (5)

Country Link
US (1) US5042147A (de)
EP (1) EP0399768B1 (de)
JP (1) JPH02306690A (de)
KR (1) KR920007120B1 (de)
DE (1) DE69015879T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE9202077L (sv) * 1992-07-06 1994-01-07 Ellemtel Utvecklings Ab Komponentmodul
US5977618A (en) 1992-07-24 1999-11-02 Tessera, Inc. Semiconductor connection components and methods with releasable lead support
US5915752A (en) * 1992-07-24 1999-06-29 Tessera, Inc. Method of making connections to a semiconductor chip assembly
US5367763A (en) * 1993-09-30 1994-11-29 Atmel Corporation TAB testing of area array interconnected chips
KR0145768B1 (ko) * 1994-08-16 1998-08-01 김광호 리드 프레임과 그를 이용한 반도체 패키지 제조방법
CN1103179C (zh) 1995-09-18 2003-03-12 德塞拉股份有限公司 微电子连接元件以及包含该元件的组件
US5724717A (en) * 1996-08-09 1998-03-10 The Whitaker Corporation Method of making an electrical article
JPH11135898A (ja) * 1997-10-31 1999-05-21 Asahi Optical Co Ltd プリント配線基板
JP3468179B2 (ja) * 1999-11-25 2003-11-17 株式会社村田製作所 表面実装部品
KR100389314B1 (ko) * 2001-07-18 2003-06-25 엘지전자 주식회사 도금인입선 없는 인쇄회로기판의 제조방법
JP4484444B2 (ja) * 2003-04-11 2010-06-16 三洋電機株式会社 回路装置の製造方法
JP2013030712A (ja) * 2011-07-29 2013-02-07 Toshiba Corp 半導体モジュールおよび半導体モジュールの製造方法
US10754439B2 (en) * 2018-06-29 2020-08-25 Intel Corporation Selectively displaced keys for input and output

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1483570A (de) * 1965-06-23 1967-09-06
US3614832A (en) * 1966-03-09 1971-10-26 Ibm Decal connectors and methods of forming decal connections to solid state devices
NL7101602A (de) * 1971-02-05 1972-08-08
US3781596A (en) * 1972-07-07 1973-12-25 R Galli Semiconductor chip carriers and strips thereof
US3838984A (en) * 1973-04-16 1974-10-01 Sperry Rand Corp Flexible carrier and interconnect for uncased ic chips
US3996603A (en) * 1974-10-18 1976-12-07 Motorola, Inc. RF power semiconductor package and method of manufacture
JPS5559795A (en) * 1978-10-30 1980-05-06 Nippon Electric Co Printed circuit board and method of manufacturing same
JPS5822767B2 (ja) * 1978-12-29 1983-05-11 富士ゼロックス株式会社 和文タイプライタ
DE3430290A1 (de) * 1984-08-17 1986-02-27 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zur selektiven metallisierung
DE3704547A1 (de) * 1987-02-13 1988-08-25 Bbc Brown Boveri & Cie Verfahren zur herstellung von loetpads und bondpads auf duennschichthybridschaltungen
JPH01108798A (ja) * 1987-10-21 1989-04-26 Nec Corp プリント配線板の製造方法

Also Published As

Publication number Publication date
EP0399768A3 (de) 1991-07-17
EP0399768A2 (de) 1990-11-28
KR920007120B1 (ko) 1992-08-24
EP0399768B1 (de) 1995-01-11
KR900019545A (ko) 1990-12-24
DE69015879T2 (de) 1995-05-04
JPH02306690A (ja) 1990-12-20
US5042147A (en) 1991-08-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee