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DE60105168D1 - Automatische Abtastprüfung von komplexen integrierten Schaltungen - Google Patents

Automatische Abtastprüfung von komplexen integrierten Schaltungen

Info

Publication number
DE60105168D1
DE60105168D1 DE60105168T DE60105168T DE60105168D1 DE 60105168 D1 DE60105168 D1 DE 60105168D1 DE 60105168 T DE60105168 T DE 60105168T DE 60105168 T DE60105168 T DE 60105168T DE 60105168 D1 DE60105168 D1 DE 60105168D1
Authority
DE
Germany
Prior art keywords
scan
circuit elements
domain
interconnected
configuration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60105168T
Other languages
English (en)
Other versions
DE60105168T2 (de
Inventor
Benoit Antoine Bailliet
Didier Lecain
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE60105168D1 publication Critical patent/DE60105168D1/de
Publication of DE60105168T2 publication Critical patent/DE60105168T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE60105168T 2001-10-10 2001-10-10 Automatische Abtastprüfung von komplexen integrierten Schaltungen Expired - Fee Related DE60105168T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP01402617A EP1302776B1 (de) 2001-10-10 2001-10-10 Automatische Abtastprüfung von komplexen integrierten Schaltungen

Publications (2)

Publication Number Publication Date
DE60105168D1 true DE60105168D1 (de) 2004-09-30
DE60105168T2 DE60105168T2 (de) 2005-01-27

Family

ID=8182919

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60105168T Expired - Fee Related DE60105168T2 (de) 2001-10-10 2001-10-10 Automatische Abtastprüfung von komplexen integrierten Schaltungen

Country Status (7)

Country Link
US (1) US20050039093A1 (de)
EP (1) EP1302776B1 (de)
JP (1) JP2005505781A (de)
KR (1) KR20040050908A (de)
AT (1) ATE274705T1 (de)
DE (1) DE60105168T2 (de)
WO (1) WO2003034083A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100395557C (zh) * 2005-03-04 2008-06-18 清华大学 采用加权扫描选通信号的基于扫描的自测试结构的自测试方法
US20130275824A1 (en) * 2012-04-12 2013-10-17 Lsi Corporation Scan-based capture and shift of interface functional signal values in conjunction with built-in self-test
GB2520506B (en) 2013-11-21 2020-07-29 Advanced Risc Mach Ltd Partial Scan Cell
CN106226678B (zh) * 2016-07-15 2019-02-15 中国人民解放军国防科学技术大学 一种基于并行施加测试激励的低功耗扫描测试方法及装置
US20240103066A1 (en) * 2022-09-27 2024-03-28 Infineon Technologies Ag Circuit and method for testing a circuit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4710931A (en) * 1985-10-23 1987-12-01 Texas Instruments Incorporated Partitioned scan-testing system
US5696771A (en) * 1996-05-17 1997-12-09 Synopsys, Inc. Method and apparatus for performing partial unscan and near full scan within design for test applications
CA2225879C (en) * 1997-12-29 2001-05-01 Jean-Francois Cote Clock skew management method and apparatus

Also Published As

Publication number Publication date
WO2003034083A2 (en) 2003-04-24
EP1302776B1 (de) 2004-08-25
DE60105168T2 (de) 2005-01-27
JP2005505781A (ja) 2005-02-24
KR20040050908A (ko) 2004-06-17
EP1302776A1 (de) 2003-04-16
WO2003034083A3 (en) 2003-12-24
ATE274705T1 (de) 2004-09-15
US20050039093A1 (en) 2005-02-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEX., US

8339 Ceased/non-payment of the annual fee