DE60039094D1 - Halbleiterbauelement mit transparentem verbindungsbereich für silizidanwendungen und deren hestellungsverfahren - Google Patents
Halbleiterbauelement mit transparentem verbindungsbereich für silizidanwendungen und deren hestellungsverfahrenInfo
- Publication number
- DE60039094D1 DE60039094D1 DE60039094T DE60039094T DE60039094D1 DE 60039094 D1 DE60039094 D1 DE 60039094D1 DE 60039094 T DE60039094 T DE 60039094T DE 60039094 T DE60039094 T DE 60039094T DE 60039094 D1 DE60039094 D1 DE 60039094D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor component
- holding method
- connection range
- transparent connection
- silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/05—Accumulators with non-aqueous electrolyte
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/57—Protection from inspection, reverse engineering or tampering
- H01L23/576—Protection from inspection, reverse engineering or tampering using active circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/271,737 US6326675B1 (en) | 1999-03-18 | 1999-03-18 | Semiconductor device with transparent link area for silicide applications and fabrication thereof |
PCT/US2000/006346 WO2000055889A1 (en) | 1999-03-18 | 2000-03-10 | Semiconductor device with transparent link area for silicide applications and fabrication thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60039094D1 true DE60039094D1 (de) | 2008-07-17 |
Family
ID=23036861
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60039094T Expired - Lifetime DE60039094D1 (de) | 1999-03-18 | 2000-03-10 | Halbleiterbauelement mit transparentem verbindungsbereich für silizidanwendungen und deren hestellungsverfahren |
Country Status (8)
Country | Link |
---|---|
US (2) | US6326675B1 (de) |
EP (1) | EP1082757B1 (de) |
JP (1) | JP2002539636A (de) |
KR (1) | KR100723076B1 (de) |
CN (1) | CN1197124C (de) |
AU (1) | AU3737800A (de) |
DE (1) | DE60039094D1 (de) |
WO (1) | WO2000055889A1 (de) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6117762A (en) | 1999-04-23 | 2000-09-12 | Hrl Laboratories, Llc | Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering |
US6396368B1 (en) | 1999-11-10 | 2002-05-28 | Hrl Laboratories, Llc | CMOS-compatible MEM switches and method of making |
US7217977B2 (en) | 2004-04-19 | 2007-05-15 | Hrl Laboratories, Llc | Covert transformation of transistor properties as a circuit protection method |
US6815816B1 (en) * | 2000-10-25 | 2004-11-09 | Hrl Laboratories, Llc | Implanted hidden interconnections in a semiconductor device for preventing reverse engineering |
US7294935B2 (en) * | 2001-01-24 | 2007-11-13 | Hrl Laboratories, Llc | Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide |
US6791191B2 (en) | 2001-01-24 | 2004-09-14 | Hrl Laboratories, Llc | Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations |
US6740942B2 (en) * | 2001-06-15 | 2004-05-25 | Hrl Laboratories, Llc. | Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact |
US6774413B2 (en) | 2001-06-15 | 2004-08-10 | Hrl Laboratories, Llc | Integrated circuit structure with programmable connector/isolator |
US6897535B2 (en) * | 2002-05-14 | 2005-05-24 | Hrl Laboratories, Llc | Integrated circuit with reverse engineering protection |
US7049667B2 (en) * | 2002-09-27 | 2006-05-23 | Hrl Laboratories, Llc | Conductive channel pseudo block process and circuit to inhibit reverse engineering |
US6979606B2 (en) | 2002-11-22 | 2005-12-27 | Hrl Laboratories, Llc | Use of silicon block process step to camouflage a false transistor |
AU2003293540A1 (en) | 2002-12-13 | 2004-07-09 | Raytheon Company | Integrated circuit modification using well implants |
KR20050011317A (ko) * | 2003-07-22 | 2005-01-29 | 삼성전자주식회사 | 리버스 엔지니어링 방지수단을 구비하는 반도체 집적회로및 이의 리버스 엔지니어링 방지방법 |
JP4795247B2 (ja) | 2003-11-26 | 2011-10-19 | エレクトロニクス アンド テレコミュニケーションズ リサーチ インスチチュート | デジタルアイテムの使用に応じるイベント報告のためのデータ構造、並びにこれを利用したイベント報告システム及びその方法 |
US7242063B1 (en) | 2004-06-29 | 2007-07-10 | Hrl Laboratories, Llc | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable |
US6955931B1 (en) * | 2005-02-10 | 2005-10-18 | Advanced Micro Devices, Inc. | Method for detecting silicide encroachment of a gate electrode in a semiconductor arrangement |
US8168487B2 (en) | 2006-09-28 | 2012-05-01 | Hrl Laboratories, Llc | Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer |
US8017514B2 (en) * | 2008-05-05 | 2011-09-13 | International Business Machines Corporation | Optically transparent wires for secure circuits and methods of making same |
US9287879B2 (en) * | 2011-06-07 | 2016-03-15 | Verisiti, Inc. | Semiconductor device having features to prevent reverse engineering |
JP2023003045A (ja) * | 2021-06-23 | 2023-01-11 | 吉川工業アールエフセミコン株式会社 | 半導体装置 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4268911A (en) | 1979-06-21 | 1981-05-19 | Fairchild Camera And Instrument Corp. | ROM Program security circuits |
US4603381A (en) | 1982-06-30 | 1986-07-29 | Texas Instruments Incorporated | Use of implant process for programming ROM type processor for encryption |
JPS59207652A (ja) * | 1983-05-11 | 1984-11-24 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US5010032A (en) | 1985-05-01 | 1991-04-23 | Texas Instruments Incorporated | Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects |
US4885617A (en) * | 1986-11-18 | 1989-12-05 | Siemens Aktiengesellschaft | Metal-oxide semiconductor (MOS) field effect transistor having extremely shallow source/drain zones and silicide terminal zones, and a process for producing the transistor circuit |
US4843026A (en) | 1987-09-24 | 1989-06-27 | Intel Corporation | Architecture modification for improved ROM security |
US4766516A (en) | 1987-09-24 | 1988-08-23 | Hughes Aircraft Company | Method and apparatus for securing integrated circuits from unauthorized copying and use |
JPH022142A (ja) * | 1988-06-13 | 1990-01-08 | Mitsubishi Electric Corp | 電界効果トランジスタ及びその製造方法 |
FR2658951B1 (fr) * | 1990-02-23 | 1992-05-07 | Bonis Maurice | Procede de fabrication d'un circuit integre pour filiere analogique rapide utilisant des lignes d'interconnexions locales en siliciure. |
US5236857A (en) | 1991-10-30 | 1993-08-17 | Texas Instruments Incorporated | Resistor structure and process |
WO1993009567A1 (en) | 1991-10-31 | 1993-05-13 | Vlsi Technology, Inc. | Auxiliary gate lightly doped drain (agldd) structure with dielectric sidewalls |
JPH11500268A (ja) | 1995-02-16 | 1999-01-06 | ペラグリン セミコンダクター コーポレイション | 集積回路用抵抗負荷及びその作成方法、及びsram |
US5780920A (en) | 1995-10-06 | 1998-07-14 | Micron Technology, Inc. | Method of forming a resistor and integrated circuitry having a resistor construction |
US5661085A (en) | 1996-06-17 | 1997-08-26 | Chartered Semiconductor Manufacturing Pte, Ltd. | Method for forming a low contact leakage and low contact resistance integrated circuit device electrode |
US5804470A (en) | 1996-10-23 | 1998-09-08 | Advanced Micro Devices, Inc. | Method of making a selective epitaxial growth circuit load element |
US5834356A (en) | 1997-06-27 | 1998-11-10 | Vlsi Technology, Inc. | Method of making high resistive structures in salicided process semiconductor devices |
-
1999
- 1999-03-18 US US09/271,737 patent/US6326675B1/en not_active Expired - Lifetime
-
2000
- 2000-03-10 EP EP00916243A patent/EP1082757B1/de not_active Expired - Lifetime
- 2000-03-10 WO PCT/US2000/006346 patent/WO2000055889A1/en active IP Right Grant
- 2000-03-10 JP JP2000606036A patent/JP2002539636A/ja not_active Withdrawn
- 2000-03-10 AU AU37378/00A patent/AU3737800A/en not_active Abandoned
- 2000-03-10 CN CNB008003556A patent/CN1197124C/zh not_active Expired - Fee Related
- 2000-03-10 KR KR1020007012909A patent/KR100723076B1/ko not_active Expired - Fee Related
- 2000-03-10 DE DE60039094T patent/DE60039094D1/de not_active Expired - Lifetime
-
2001
- 2001-07-24 US US09/912,194 patent/US6410413B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
CN1296638A (zh) | 2001-05-23 |
US6410413B2 (en) | 2002-06-25 |
EP1082757A1 (de) | 2001-03-14 |
JP2002539636A (ja) | 2002-11-19 |
CN1197124C (zh) | 2005-04-13 |
KR100723076B1 (ko) | 2007-05-29 |
KR20010043694A (ko) | 2001-05-25 |
EP1082757B1 (de) | 2008-06-04 |
WO2000055889A1 (en) | 2000-09-21 |
AU3737800A (en) | 2000-10-04 |
US6326675B1 (en) | 2001-12-04 |
US20010041431A1 (en) | 2001-11-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8328 | Change in the person/name/address of the agent |
Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN |
|
8364 | No opposition during term of opposition |