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DE3781607D1 - Statische ram-speicheranordnungen. - Google Patents

Statische ram-speicheranordnungen.

Info

Publication number
DE3781607D1
DE3781607D1 DE8787305719T DE3781607T DE3781607D1 DE 3781607 D1 DE3781607 D1 DE 3781607D1 DE 8787305719 T DE8787305719 T DE 8787305719T DE 3781607 T DE3781607 T DE 3781607T DE 3781607 D1 DE3781607 D1 DE 3781607D1
Authority
DE
Germany
Prior art keywords
ram memory
static ram
memory arrangements
arrangements
static
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787305719T
Other languages
English (en)
Other versions
DE3781607T2 (de
Inventor
Hitoshi Taniguchi
Keisuke Ishio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of DE3781607D1 publication Critical patent/DE3781607D1/de
Application granted granted Critical
Publication of DE3781607T2 publication Critical patent/DE3781607T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
DE8787305719T 1986-06-30 1987-06-26 Statische ram-speicheranordnungen. Expired - Fee Related DE3781607T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61153311A JPS639097A (ja) 1986-06-30 1986-06-30 スタテイツクｒａｍ

Publications (2)

Publication Number Publication Date
DE3781607D1 true DE3781607D1 (de) 1992-10-15
DE3781607T2 DE3781607T2 (de) 1993-03-25

Family

ID=15559711

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787305719T Expired - Fee Related DE3781607T2 (de) 1986-06-30 1987-06-26 Statische ram-speicheranordnungen.

Country Status (5)

Country Link
US (1) US5034924A (de)
EP (1) EP0251734B1 (de)
JP (1) JPS639097A (de)
KR (1) KR880000969A (de)
DE (1) DE3781607T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4928268A (en) * 1989-04-21 1990-05-22 Motorola, Inc. Memory using distributed data line loading
US5197029A (en) * 1991-02-07 1993-03-23 Texas Instruments Incorporated Common-line connection for integrated memory array
JP3057836B2 (ja) * 1991-08-19 2000-07-04 日本電気株式会社 半導体記憶装置
FR2694826B1 (fr) * 1992-08-13 1994-09-16 Thomson Composants Militaires Circuit intégré de mémoire avec protection contre des perturbations.
US5710742A (en) * 1995-05-12 1998-01-20 International Business Machines Corporation High density two port SRAM cell for low voltage CMOS applications

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57130286A (en) * 1981-02-06 1982-08-12 Fujitsu Ltd Static semiconductor memory
JPS6061985A (ja) * 1983-09-14 1985-04-09 Mitsubishi Electric Corp 半導体記憶装置
US4791613A (en) * 1983-09-21 1988-12-13 Inmos Corporation Bit line and column circuitry used in a semiconductor memory
GB2160046B (en) * 1984-04-20 1987-12-23 Hitachi Ltd Semiconductor memory device
US4730279A (en) * 1985-03-30 1988-03-08 Kabushiki Kaisha Toshiba Static semiconductor memory device
US4636991A (en) * 1985-08-16 1987-01-13 Motorola, Inc. Summation of address transition signals
US4621315A (en) * 1985-09-03 1986-11-04 Motorola, Inc. Recirculating MOS charge pump

Also Published As

Publication number Publication date
DE3781607T2 (de) 1993-03-25
EP0251734A3 (en) 1989-07-12
EP0251734A2 (de) 1988-01-07
KR880000969A (ko) 1988-03-30
EP0251734B1 (de) 1992-09-09
JPS639097A (ja) 1988-01-14
US5034924A (en) 1991-07-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee