DE1424427B2 - DIGITAL BINARY CONTROL PROTECTED AGAINST INTERNAL FAULTS - Google Patents

Description

The invention relates to an internal object initially posed and thus avoids the

Error-protected digital-binary control with min- Disadvantages of known memories. '- ■' ■■

at least one logic element with a half

conductor arrangement in which the semiconductor arrangement with th known memories still has the advantage that an alternating voltage serving as a clock signal or it is largely insensitive to the outside pulsed voltage is applied, such, acting disturbances. So it’s going to be a mistake the value "L" of the digital-binary control signal avoided circuits of this type, an impulse sequence is assigned and the logical further expedient details and applications

Element one for this control signal permeable training possibilities of the Spei coupling element according to the invention is connected downstream to which either an io chers result from the description of in further logic element or an actuator in the exemplary embodiments shown in the drawing is closed, according to patent 1,125,069 of the invention. In the exemplary embodiments, the

Chosen in controls with contactless logical element-capacitor coupling. It shows There are memories in many places. This F i g. 1 a memory according to the invention with do-

are destroyed by a memory signal in memory position 15,

brought. They then give an output signal, F i g. 2 a memory according to FIG. 1 with a white

when the memory signal disappears. The memory has more direct, antivalent output and something different can be triggered by another signal, a delete signal, deletion,

brought back into the original position. FIG. 3 shows a further development of the memory

will. Such contactless memories are shown in FIG. 20 FIG. 2 with dominant storage behavior, general from contactless active switching F i g. 4 the well-known circuit diagram of a single-channel

elements, in particular made of transistors, on-press control,

built. F i g. 5 the use of a preferred embodiment

In many controls, a high level of security is provided by the memory according to the invention required, e.g. B. in a press control. With a 25 a press control.

A defect in the control should not affect the operating In F i g. 1 are an OR-NOT gate 1 as well

personnel dangerous condition occur. The well-known AND-NOT gate 2 darten DC voltage-controlled memory that z. B. made out. The output of the AND-NOT gate 2, at least two series-connected contact, ie the output stage, is via a capacitor-less, active switching elements having gates 30 14, instead of which an inductive one is built in principle and in which the output of the output transformer can occur, on the input of the OR gate to the input gate in the manner of a NOT gate 1, ie the input stage, is fed back in the manner of self-holding, have not fed back to a self-holding. To the potential long level of security. Is z. B. the active shift is a diode 20. The gate of the switching element in the output gate is defective, z. B. conductive, 35 F i g. 1, or also the other figures, have active ones, then the output gate has a working signal and switching elements, in particular transistors. It may trigger tax measures, although other multilayer elements, e.g. B. that no input-side DC voltage storage signal, four-layer triode are used, that is, no control signal is applied. To input d of the OR-NOT gate 1

The invention is based on the object of switching off a contactless or alternating voltage, ie, as a clock signal, ge memory of the type described above, for the 40 as a memory control signal, a pulse-shaped input control specified. The gate 1 is to be formed only for the so that at the output of the output gate or the fed in pulsed or alternating voltage at the complementary output no inadmissible signal permeable capacitor 7 as well as a rectifier appears when the memory or an element thereof 9 with the input a of the AND-NOT gate 2 has become defective. tied together. The diode 8 is used to raise the potential

The solution to this problem is achieved with one of the pulses, the rectifier 9 in conjunction with Initially specified control according to the invention that the smoothing capacitor 10 for rectifying the by that to create a memory a first, impulses.

OR element serving as input stage and a 50 At input b of AND-NOT gate 2, the second AND element serving as output stage is also fed the clock signal, via a first coupling element and a rectifier

circuit are connected in series and that the input e of the OR-NOT gate 1 input-output stage is fed via a further coupling element to the. If the cancellation signal is also fed back to a pulse input stage and both stages are fed by an alternating voltage or voltage, it can be acted upon by the clock signal. a capacitor 3 or inductive or galvanic

With this memory, the active switching element will be nically coupled. A diode 4 is used here one stage defective, e.g. B. blocking or conductive, can again to increase the potential, the rectifier 5 in no output signal occur, since then no clock connection with the smoothing capacitor 6 for signal is transmitted. A DC voltage is 60 rectification of the cancellation signal, through the coupling link, ζ. B. by a capacitor. The output of the AND-NOT gate 2 is a

tor or inductive transformer, blocked. Capacitor 15 for DC voltage-free acceptance

Since the storage is connected downstream by feeding in the pulsed output signal. The abgenom-shaped or alternating voltage, d. H. of the clock pulse or alternating voltage signals, occurs, in the idle state no 65 is rectified again, so that after-output signal on, because this following elements via a coupling member, z. B. more gates or a Stellvon the output of the output stage is removed or an amplifier is used in terms of DC voltage. The memory according to the invention thus solves the can be made.

The operation of the memory according to the invention is as follows: If the clock signal is present at the input d of the OR-NOT gate 1 and at the input b of the AND-NOT gate 2, then after a small delay time, essentially given by the capacitor 10, appears at the input α of the AND-NOT gate 2 DC voltage signal. As a result, a clock signal occurs at the output of the AND-NOT gate 2 which is 180 ° out of phase with the clock signal fed in at the input b and which is fed back via the capacitor 14 to the input c of the OR-NOT gate 1. If the memory signal at input d of the OR-NOT gate 1 disappears, the clock signal continues to be fed in via the feedback. The clock signal remains at the output of AND-NOT gate 2, that is, the memory is set. Is z. B. the AND-NOT gate 2 is defective, no clock signal can be transmitted. There is no voltage behind the capacitor 15 and the downstream element cannot be controlled. If the OR-NOT gate 1 is defective, no pulses are transmitted either, and there is no DC voltage signal at the input α of the AND-NOT gate 2, that is, the one AND condition for the AND-NOT gate 2 is missing .

The memory is erased when a DC voltage signal is present at the input e of the OR-NOT gate 1, which, as explained, can also be obtained from the clock signal. Then the output signal of the OR-NOT gate 1 is always "0" and does not change with an applied clock signal. As a result, the DC voltage signal also disappears at the input α of the AND-NOT gate 2 and thus also the clock output signal; the memory is cleared.

Because the DC voltage signal at the input e of the OR-NOT gate 1 determines the output signal of this gate, the memory according to FIG. 1 will predominantly "erase", ie when the memory and erase signals are present at the same time, the erase signal determines the behavior of the memory .

F i g. 2 shows once the already in connection with FIG. 1 explained elements 1,2,7,8,9,10,14, 15, on the other hand another OR-NOT gate

12 with a downstream capacitor 16 to obtain a non-equivalent output. A further OR-NOT gate 11 (cancellation stage) is also provided, to which the clock signal passed on to input b of AND-NOT gate 2 and a DC voltage cancellation signal, which can also be obtained from a clock signal, are switched is. The mode of action of this exemplary embodiment of the memory according to the invention results analogously to the mode of action of the memory according to FIG. 1.

The embodiment according to FIG. 3 differs from that according to FIG. 2 only in that the output of the OR-NOT gate 11 is connected via a bypass OR gate 13 to the input b of the AND-NOT gate 2 to achieve a dominant memory behavior, the input of the bypass OR gate Gatters

13 the memory clock signal is still switched. This ensures that when the memory clock signal is present, the clock signal is also present at input b of the AND-NOT gate 2 when a DC voltage cancel signal is present.

In the embodiments according to Fi g. 1 to 3 is an OR-NOT gate 1 and as input stage An AND-NOT gate 2 is provided as the output stage. This combination has been found to be very beneficial proven; in principle, however, two OR-NOT gates, two AND-NOT gates can also be used or OR and AND gates or combinations thereof are used. Delete inputs only have to be adapted accordingly

ίο be.

The memory created in this way is used with advantage wherever a control with high security is required. For example, be z. B. on controls of elevators, nuclear reactors, switches or the like. pointed out.

In the following, the advantageous application of the memory in the control of a press, punch, Cutting machine or the like. Be explained. This control works with advantage according to the one in the main patent proposed principle that the DC voltage for the actuator from a fed-in pulse-shaped- or AC voltage is taken, with the active switching elements of the controller Only allow the fed-in auxiliary voltages to pass through Coupling links are connected. The memory can also be operated with a DC voltage Use the controller because, as explained, the clock output signal of the memory is rectified can.

For a better understanding of the control according to FIG. 4 is to be based on FIG. 3 the principle of a Press control are explained.

The F i g. 4 shows a memory 17 which is stored in the idle state of the key T _1. The memory output signal is connected to one input of the AND gate 18, to whose other input a control signal can also be applied by pressing the button T _1. The yes output of the AND gate 18 is connected to the input of an OR gate 19, which in turn controls an actuator via an amplifier, if necessary. An initiator Z _{1 is also} provided, which sends a signal to the OR gate 19 in the range from 180 to 360 ° (movement of the crank for the press).

The mode of operation is as follows: By pressing button T ₁ , the AND condition for gate 18 is fulfilled and the actuator is thus controlled via OR gate 19, ie the stamp moves downwards. If the bottom dead center is reached, the initiator J ₁ gives an output signal and in turn controls - even when the button is released - the actuator via the OR gate 19, ie the stamp runs up automatically. At the same time, the memory 17 is erased, so that the press movement must be initiated again by pressing a button.

Starting from FIG. 4 is in FIG. 5 shows a press control which has a very high level of security, in particular also in that the memory 17 of FIG. 4 is formed by the memory according to the invention. The memory 17 is provided by an embodiment according to FIG. 1 formed. One recognizes in FIG. 5 the OR-NOT gate 1, the AND-NOT gate 2 and the others in connection with FIG. 1 explained elements 3 to 10, 14, 15, 20. Furthermore, the AND gate 18, the OR gate 19 and the initiator J ₁ are present in FIG. The individual gates are interconnected with only the clock signal voltage.

casual coupling links - here capacitors with a downstream diode - connected. In principle, inductive transformers can also be used. In analogy to FIG. 4, the clock memory signal is switched on the one hand to the memory input via the button T ₁ , and on the other hand the DC voltage cancellation signal obtained from the clock signal voltage of the initiator J _{2 is switched.} In the idle state, the initiator J _{2 has} no output signal, ie the memory is set using the T _{1 key.} The clock output voltage picked up via the capacitor 15 or shifted in potential by means of the diode 20 'is calculated in analogy to FIG. 4 switched to the input of the AND gate 18, on whose other input when the button T _{1 is} pressed, a clock signal also arrives. The AND gate 18 is connected via the capacitor-diode combination 15 ', 20 "to the OR gate 19, which in turn is not shown, but in the manner explained in the main patent via a coupling element or a rectifier arrangement, possibly via an amplifier, the actuator modulates, under the condition that the actuating DC voltage is obtained for the actuator from the clock signal voltage. g in extension of the basic circuit diagram according to F i. 4 g in F i. 5 for increasing the safety of two initiators J _1, J ₂ is provided , both of which work on an additionally provided AND gate 21. Two diodes 20 ^v , 20 ^VI are used in a known manner to shift the potential are fine.

An AND gate 22 is also provided, which is connected ^{to the AND gate 21 via the capacitor-diode combination 15 '", 20 IV} or via the capacitor-diode combination 15", 20'"to the OR gate 19. The clock output signal of the OR gate 19 is fed back to an input of the AND gate 22 via the coupling combination 3 ', 4' with subsequent rectification by the elements 5 ', 6' The operation of the press control according to Fig. 5 is the same as that of the control according to Fig. 4, but the clock signal takes the place of the DC voltage signal a very high level of security, because if a gate is defective, no clock signal is transmitted and the actuator cannot be operated.

In a further embodiment of the control according to FIG. 5 two buttons can be provided, both of them when pressed, a clock signal is sent to AND gate 18 and when idle via an additional one AND gate (not shown) a memory clock signal to the memory input, d. H. on the input of the OR-NOT gate 1, switch.

It is also conceivable to carry out the control with two channels, provided that the actuator is only operated when both channels are controlled. The channels can be inversely related to each other build up.

To meet the operating modes common in presses, e.g. B. Continuous running and foot switch operation can further initiators or logic circuits can be provided.

The in the F i g. 1 to 5 gates used preferably contain transistors as active switching elements. Other semiconductor elements such as the four-layer diode can also be used.

The AND gates used preferably contain no diodes as passive input gates, but rather there are resistors for potential distribution.

Claims (7)

Patent claims: 1. Digital binary protected against internal errors Control with at least one logic element with a semiconductor arrangement in which the Semiconductor arrangement with an alternating voltage or pulsed alternating voltage serving as a clock signal Voltage is applied in such a way that the value "L" of the digital-binary control signal a Pulse sequence is assigned and the logic element is a permeable for this control signal Coupling element is connected downstream to which either a further logic element or an actuator is connected, according to patent 1 125 069, characterized in that for creating of a memory a first OR element (OR-NOT gate 1) and a second AND element serving as an output stage (AND-NOT gate 2) a first coupling element (capacitor 7) and a rectifier circuit (8, 9, 10) connected in series are and that the output stage via a further coupling element (capacitor 14) to the Input stage is fed back and both stages are acted upon by the clock signal. 2. Controller according to claim 1, characterized in that on the input stage DC voltage signal is switched as a cancel signal. 3. Control according to claim 1 or 2, characterized in that a further OR element is provided as a cancellation stage (OR-NOT gate 11), the output of which is connected to the clock signal input (b) of the output stage and to its inputs once the clock signal, on the other hand, a DC voltage canceling signal is switched (Fig.2). 4. Control according to claim 3, characterized in that, in order to achieve a dominant storage behavior, the output of the erasing stage (11) is connected to the clock signal input (b) of the output stage via a further OR element (bypass OR gate 13) and that the clock signal is also switched to the second input of this OR element (Fig. 3). 5. Protected against internal errors digital-binary control according to claim 1 or one of the following, applied to a control for a work machine od like a press, punch ₁ ) the work machine can be set by the clock signal connected downstream with these means and the output side is connected to an input of an AND gate (18), the other input of which is acted upon with a clock signal in the working position of the actuating means and whose output is connected to an input of the actuator for operating the working machine OR gate (19) is connected, the second input of _{which is controlled by at least one initiator (Z 1} , J ₂ ) in the range 180 to 360 ° with a clock signal, from which the memory can be erased at the same time. 6. Controller according to claim 5, characterized in that a further, connected in parallel to the memory AND gate (22) is provided, the first input of which is from at least one initiator and its second input from the exit output signal of the operating machine operating OR gate (19) can be controlled. 7. Control according to claim 5 or 6, characterized in that two initiators (J ₁ , J ₂ ) are provided, each of which is connected to an input of an AND gate (21), which in turn controls the OR gate ( 19) either directly or indirectly via the AND gate (22) lying parallel to the memory. 1 sheet of drawings 109 530 / Π2