CN220154839U - An over-temperature protection circuit without comparator - Google Patents
An over-temperature protection circuit without comparator Download PDFInfo
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- CN220154839U CN220154839U CN202321312101.3U CN202321312101U CN220154839U CN 220154839 U CN220154839 U CN 220154839U CN 202321312101 U CN202321312101 U CN 202321312101U CN 220154839 U CN220154839 U CN 220154839U
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Abstract
The utility model relates to the technical field of chip over-temperature protection and provides an over-temperature protection circuit without a comparator, which comprises a positive temperature coefficient voltage generation module, an over-temperature protection core module and a hysteresis module, wherein the positive temperature coefficient voltage generation module comprises a first NPN triode and a resistance unit; the over-temperature protection core module comprises a first current mirror unit, a second current mirror unit, an output control unit, a second NPN triode and a current source; and the hysteresis module comprises a first MOS tube and a third resistor. The second NPN triode is controlled to be conducted to control the output signal, when the temperature of the chip is too high, the over-temperature protection signal is triggered, the chip is closed, and only when the temperature is reduced to a value lower than the over-temperature point, the chip is powered on again to work, and meanwhile, the second NPN triode has a hysteresis function, so that the area of the chip is reduced and the power consumption of a circuit is reduced while the over-temperature protection function is realized.
Description
Technical Field
The utility model relates to the technical field of chip over-temperature protection, in particular to an over-temperature protection circuit without a comparator.
Background
In a chip, an over-temperature protection circuit is a common protection circuit. When short circuit occurs in the chip or abnormal conditions occur, power consumption suddenly rises, the working temperature is too high, and the chip is damaged seriously. The over-temperature protection circuit is used for monitoring the temperature of the chip, and when the working temperature is higher than the threshold value, the over-temperature protection circuit sends out a logic signal to close the chip. Meanwhile, a certain hysteresis is reserved on the judgment of the over-temperature point of the over-temperature protection circuit, when the temperature is slightly lower than the over-temperature point, the over-temperature protection circuit sends out a logic signal, and the chip resumes normal operation.
The prior art over-temperature protection circuit is shown in figure 1. A negative temperature coefficient current (ICTAT) flows through the two resistors to generate a negative temperature coefficient Voltage (VCTAT) which is connected to the inverting terminal of the comparator CMP. The in-phase of the comparator CMP is connected to a temperature independent reference Voltage (VBG). The output signal OTP of the comparator is connected to the grid of the NMOS tube M1, and meanwhile, the OTP signal is also used as an over-temperature protection signal. When the temperature of the chip is low and no over-temperature occurs, VREF < VCTAT, the OTP signal is at a low level, M1 is cut off, the resistor R1 is connected into the circuit, and the chip works normally; when the temperature continuously rises and exceeds the over-temperature point, VREF > VCTAT, the OTP signal jumps from low level to high level, M1 is conducted, resistor R1 is short-circuited, and the chip is protected and closed. Since resistor R1 is shorted, the OTP returns to low only when the temperature drops below the over-temperature point and the chip resumes normal operation.
The over-temperature protection circuit in the prior art has the advantages that as the comparator is introduced, the transmission delay of signals is increased; in addition, the chip area is excessively large and the power consumption of the circuit is increased.
Disclosure of Invention
This section is intended to outline some aspects of embodiments of the utility model and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section as well as in the description of the utility model and in the title of the utility model, which may not be used to limit the scope of the utility model.
In view of the fact that the traditional over-temperature protection circuit is introduced into the comparator, the transmission delay of signals is increased, the chip area is overlarge, and the power consumption of the circuit is also increased.
In order to solve the technical problems, the utility model provides the following technical scheme: the over-temperature protection circuit without the comparator comprises a positive temperature coefficient voltage generation module, a first voltage regulator and a second voltage regulator, wherein the positive temperature coefficient voltage generation module comprises a first NPN triode and a resistance unit, the base electrode of the first NPN triode is connected with a reference voltage, the collector electrode of the first NPN triode is connected with a power supply voltage, and the emitter electrode of the first NPN triode is connected with the resistance unit; the over-temperature protection core module comprises a first current mirror unit, a second current mirror unit, an output control unit, a second NPN triode and a current source, wherein the first current mirror unit and the second current mirror unit are connected to the input end of the output control unit, the collector electrode of the second NPN triode is connected to the second current mirror unit, the emitter electrode of the second NPN triode is grounded, one end of the current source is connected to a power supply voltage, and the other end of the current source is connected to the first current mirror unit; the hysteresis module comprises a first MOS tube and a third resistor, wherein the drain electrode of the first MOS tube is connected to one end of the third resistor, and the source electrode of the first MOS tube is connected with the other end of the third resistor and grounded.
As a preferable scheme of the comparator-free over-temperature protection circuit, the emitter of the first NPN triode generates a first control voltage.
As an optimal scheme of the comparator-free over-temperature protection circuit, the resistance unit comprises a first resistor and a second resistor, one end of the first resistor is connected with the emitter of the first NPN triode, and the other end of the first resistor is connected with the second resistor in series.
As an optimal scheme of the comparator-free over-temperature protection circuit, the first current mirror unit comprises a second MOS tube and a third MOS tube, wherein the drain electrode of the second MOS tube is connected with a current source, the drain electrode of the second MOS tube is connected with a grid electrode, and the drain electrode of the second MOS tube is connected to the grid electrode of the third MOS tube.
As a preferable scheme of the comparator-free over-temperature protection circuit, the second current mirror unit comprises a fourth MOS tube and a fifth MOS tube, wherein the drain electrode and the grid electrode of the fourth MOS tube are connected and connected to the grid electrode of the fifth MOS tube.
As an optimal scheme of the comparator-free over-temperature protection circuit, the collector electrode of the second NPN triode is connected to the drain electrode of the fourth MOS tube.
As a preferable scheme of the comparator-free over-temperature protection circuit, the output control unit comprises a first inverter and a second inverter, wherein the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter is used as the output end of the circuit.
As an optimal scheme of the comparator-free over-temperature protection circuit, the drain electrode of the third MOS tube is connected with the drain electrode of the fifth MOS tube and is connected to the input end of the first inverter.
As an optimal scheme of the comparator-free over-temperature protection circuit, the first control voltage is divided by the first resistor and then connected to the base electrode of the second NPN triode, and is grounded through a series structure of the second resistor and the third resistor.
As an optimal scheme of the comparator-free over-temperature protection circuit, the output end of the first inverter in the output control unit is connected to the grid electrode of the first MOS tube.
As an optimal scheme of the comparator-free over-temperature protection circuit, the input end of the first inverter in the output control unit is connected to the grid electrode of the first MOS tube.
The utility model has the beneficial effects that: the over-temperature protection circuit does not use a comparator, has a hysteresis function, triggers an over-temperature protection signal when the temperature of the chip is over-high, closes the chip, and only when the temperature is reduced to a value lower than an over-temperature point, the chip is electrified to work again, so that the area of the chip is reduced and the power consumption of the circuit is reduced while the over-temperature protection function is realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
FIG. 1 is a prior art over-temperature protection circuit with a comparator;
FIG. 2 is a schematic diagram of an over-temperature protection circuit without a comparator according to the present utility model;
FIG. 3 is a schematic diagram illustrating the operation of the over-temperature protection circuit without the comparator according to the present utility model;
fig. 4 is a schematic diagram of hysteresis simulation of the over-temperature protection circuit without the comparator according to the present utility model.
Detailed Description
In order that the above-recited objects, features and advantages of the present utility model will become more readily apparent, a more particular description of the utility model will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present utility model, but the present utility model may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present utility model is not limited to the specific embodiments disclosed below.
Further, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic can be included in at least one implementation of the utility model. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
Further, in describing the embodiments of the present utility model in detail, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of description, and the schematic is only an example, which should not limit the scope of protection of the present utility model. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
Example 1
Referring to fig. 2, in a first embodiment of the present utility model, an over-temperature protection circuit without a comparator is provided, wherein a positive temperature coefficient voltage generating module 100 generates a first control voltage VA, and the first control voltage VA increases with increasing temperature.
Specifically, the positive temperature coefficient voltage generating module 100 includes a first NPN transistor Q1 and a resistor unit 101, wherein a base electrode of the first NPN transistor Q1 is connected to the reference voltage VBG, a collector electrode thereof is connected to the power supply voltage VDD, and an emitter electrode thereof is connected to the resistor unit 101.
The emitter of the first NPN transistor Q1 generates the first control voltage VA, i.e., the voltage at point a.
Further, the resistor unit 101 includes a first resistor R1 and a second resistor R2, where one end of the first resistor R1 is connected to the emitter of the first NPN transistor Q1, and the other end is connected in series with the second resistor R2.
The design idea of the circuit is that the over-temperature protection function is realized by utilizing the base-emitter voltage VBE of the triode, and the expression of the first control voltage VA at the point A can be written according to the circuit:
V A ＝V BG -V BE (1)
the reference voltage VBG is the output voltage of the bandgap reference circuit, and is zero temperature coefficient, VBE is the base-emitter voltage of the first NPN transistor Q1, and is a negative temperature coefficient voltage, so the first control voltage VA at point a is a positive temperature coefficient voltage.
Example 2
Referring to fig. 2 and 3, in a second embodiment of the present utility model, as the temperature increases and decreases, the second NPN transistor Q2 is turned on or off, thereby affecting the voltage level at point B and the output signal OTP, and further controlling the chip to stop or resume normal operation.
Specifically, the over-temperature protection core module 200 includes a first current mirror unit 201, a second current mirror unit 202, an output control unit 203, a second NPN transistor Q2 and a current source IB, where the first current mirror unit 201 and the second current mirror unit 202 are connected to an input end of the output control unit 203, a collector of the second NPN transistor Q2 is connected to the second current mirror unit 202, an emitter thereof is grounded, one end of the current source IB is connected to a power supply voltage VDD, and the other end is connected to the first current mirror unit 201.
The first current mirror unit 201 includes a second MOS transistor M2 and a third MOS transistor M3, where a drain of the second MOS transistor M2 is connected to the current source IB, and a drain of the second MOS transistor M2 is connected to the gate of the third MOS transistor M3.
Further, the second current mirror unit 202 includes a fourth MOS transistor M4 and a fifth MOS transistor M5, where a drain electrode of the fourth MOS transistor M4 is connected to a gate electrode of the fifth MOS transistor M5.
Preferably, the collector of the second NPN transistor Q2 is connected to the drain of the fourth MOS transistor M4.
Further, the output control unit 203 includes a first inverter INV1 and a second inverter INV2, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is used as the output end of the present circuit.
The drain of the third MOS transistor M3 is connected to the drain of the fifth MOS transistor M5, and is connected to the input end of the first inverter INV 1.
The rest of the circuit configuration is the same as in embodiment 1.
The fourth MOS tube M4 and the fifth MOS tube M5 of the PMOS tube form a current mirror structure, and the mirror proportion is 1:1, the second MOS tube M2 and the third MOS tube M3 of the NMOS tube form a current mirror structure, the reference current IB is mirrored to the third MOS tube M3, and the mirroring proportion is 1:1. in normal operation, the FB signal is high and the third resistor R3 is shorted. As the temperature rises, the first control voltage VA at the point a rises, the base voltage of the second NPN transistor Q2 is the divided voltage of the voltage at the point a, and as the temperature rises, when the temperature rises to a certain extent, the following conditions are satisfied:
the second NPN transistor Q2 is turned on, the current flowing through the second NPN transistor Q2 is mirrored to the fifth MOS transistor M5, and since the current flowing through the fifth MOS transistor M5 is greater than the current flowing through the third MOS transistor M3, the voltage at point B is pulled up, the FB signal becomes low, the output signal OTP becomes high, and the chip stops operating. When the temperature drops to meet:
the second NPN triode Q2 is turned off, the current flowing through the fifth MOS tube M5 is smaller than the current flowing through the third MOS tube M3, the voltage at the point B is pulled down, the FB signal becomes high level, the output signal OTP becomes low level, and the chip resumes normal operation. The operation of the circuit is shown in fig. 2.
Example 3
Referring to fig. 2 to 4, in a third embodiment of the present utility model, by introducing a third resistor R3, the chip operation is restored to generate a temperature hysteresis.
Specifically, the first control voltage VA is divided by the first resistor R1 and then connected to the base of the second NPN transistor Q2, and is grounded through the series structure of the second resistor R2 and the third resistor R3.
The first control voltage VA is connected to the base of the second NPN transistor Q2 after being divided by the first resistor R1, and is grounded after passing through the series structure of the second resistor R2 and the third resistor R3.
Further, an output end of the first inverter INV1 in the output control unit 203 is connected to the gate of the first MOS transistor M1.
The rest of the circuit configuration is the same as in embodiment 2.
It can be seen from formulas (2) and (3): the introduction of the resistor R3 generates a temperature hysteresis, namely, the temperature for judging the recovery work is smaller than the over-temperature point, so that the frequent switching of the output signal state of the circuit at the over-temperature point is avoided, and the oscillation is generated. By properly setting the resistance values of the resistors R1, R2, R3, a desired over-temperature point and hysteresis can be obtained. As shown in fig. 3, when r1=256K, R2=400K, R3=162K, the corresponding overtemperature point is 140 ℃, and the hysteresis amount is 20 ℃.
In addition, the power consumption in the chip is generally measured by current, and compared with a common over-temperature protection circuit with a comparator, the circuit can reduce the power consumption by 5-8 microamps, and compared with an over-temperature protection circuit with a high-speed comparator, the circuit can reduce the power consumption by tens of microamps.
It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
It should be noted that the above embodiments are only for illustrating the technical solution of the present utility model and not for limiting the same, and although the present utility model has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present utility model may be modified or substituted without departing from the spirit and scope of the technical solution of the present utility model, which is intended to be covered in the scope of the claims of the present utility model.
Claims (10)
1. An over-temperature protection circuit without a comparator is characterized in that: comprising the steps of (a) a step of,
the positive temperature coefficient voltage generation module (100) comprises a first NPN triode (Q1) and a resistance unit (101), wherein the base electrode of the first NPN triode (Q1) is connected with a reference Voltage (VBG), the collector electrode of the first NPN triode is connected with a power supply Voltage (VDD), and the emitter electrode of the first NPN triode is connected with the resistance unit (101);
the over-temperature protection core module (200) comprises a first current mirror unit (201), a second current mirror unit (202), an output control unit (203), a second NPN triode (Q2) and a current source (IB), wherein the first current mirror unit (201) and the second current mirror unit (202) are connected to the input end of the output control unit (203), the collector of the second NPN triode (Q2) is connected to the second current mirror unit (202), the emitter of the second NPN triode is grounded, one end of the current source (IB) is connected with a power supply Voltage (VDD), and the other end of the current source (IB) is connected to the first current mirror unit (201);
the hysteresis module (300) comprises a first MOS tube (M1) and a third resistor (R3), wherein the drain electrode of the first MOS tube (M1) is connected to one end of the third resistor (R3), and the source electrode of the hysteresis module is connected with the other end of the third resistor (R3) and grounded.
2. The comparator-less over-temperature protection circuit of claim 1, wherein: the emitter of the first NPN triode (Q1) generates a first control Voltage (VA).
3. The comparator-less over-temperature protection circuit of claim 2, wherein: the resistor unit (101) comprises a first resistor (R1) and a second resistor (R2), one end of the first resistor (R1) is connected with the emitter of the first NPN triode (Q1), and the other end of the first resistor is connected with the second resistor (R2) in series.
4. A comparator-less over-temperature protection circuit according to claim 3, wherein: the first current mirror unit (201) comprises a second MOS tube (M2) and a third MOS tube (M3), wherein the drain electrode of the second MOS tube (M2) is connected with the current source (IB), the drain electrode of the second MOS tube is connected with the grid electrode, and the drain electrode of the second MOS tube is connected to the grid electrode of the third MOS tube (M3).
5. The comparator-less over-temperature protection circuit of claim 4, wherein: the second current mirror unit (202) comprises a fourth MOS tube (M4) and a fifth MOS tube (M5), wherein the drain electrode and the grid electrode of the fourth MOS tube (M4) are connected, and the drain electrode and the grid electrode of the fifth MOS tube (M5) are connected.
6. The comparator-less over-temperature protection circuit of claim 5, wherein: and the collector electrode of the second NPN triode (Q2) is connected to the drain electrode of the fourth MOS tube (M4).
7. The comparator-less over-temperature protection circuit of claim 6, wherein: the output control unit (203) comprises a first inverter (INV 1) and a second inverter (INV 2), wherein the output end of the first inverter (INV 1) is connected to the input end of the second inverter (INV 2), and the output end of the second inverter (INV 2) is used as the output end of the circuit.
8. The comparator-less over-temperature protection circuit of claim 7, wherein: the drain electrode of the third MOS tube (M3) is connected with the drain electrode of the fifth MOS tube (M5) and is connected to the input end of the first inverter (INV 1).
9. The comparator-less over-temperature protection circuit of claim 8, wherein: the first control Voltage (VA) is connected to the base electrode of the second NPN triode (Q2) after being divided by the first resistor (R1), and is grounded after passing through the series structure of the second resistor (R2) and the third resistor (R3).
10. The comparator-less over-temperature protection circuit of claim 9, wherein: an output end of a first inverter (INV 1) in the output control unit (203) is connected to a grid electrode of the first MOS tube (M1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321312101.3U CN220154839U (en) | 2023-05-26 | 2023-05-26 | An over-temperature protection circuit without comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321312101.3U CN220154839U (en) | 2023-05-26 | 2023-05-26 | An over-temperature protection circuit without comparator |
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| Publication Number | Publication Date |
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| CN220154839U true CN220154839U (en) | 2023-12-08 |
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| CN202321312101.3U Expired - Fee Related CN220154839U (en) | 2023-05-26 | 2023-05-26 | An over-temperature protection circuit without comparator |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117881045A (en) * | 2024-03-11 | 2024-04-12 | 厦门元顺微电子技术有限公司 | LED linear driving thermal derating and over-temperature protection system |
| CN118282007A (en) * | 2024-06-04 | 2024-07-02 | 苏州四方杰芯电子科技有限公司 | Charging and discharging over-temperature protection system capable of generating zero-temperature current and free of temperature drift |
-
2023
- 2023-05-26 CN CN202321312101.3U patent/CN220154839U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117881045A (en) * | 2024-03-11 | 2024-04-12 | 厦门元顺微电子技术有限公司 | LED linear driving thermal derating and over-temperature protection system |
| CN117881045B (en) * | 2024-03-11 | 2024-06-11 | 厦门元顺微电子技术有限公司 | LED linear driving thermal derating and over-temperature protection system |
| CN118282007A (en) * | 2024-06-04 | 2024-07-02 | 苏州四方杰芯电子科技有限公司 | Charging and discharging over-temperature protection system capable of generating zero-temperature current and free of temperature drift |
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Granted publication date: 20231208 |