CN212269452U

CN212269452U - High-temperature pressure sensor chip

Info

Publication number: CN212269452U
Application number: CN202022283336.7U
Authority: CN
Inventors: 王立会; 邓杨
Original assignee: Guangzhou Zhihe Technology Co ltd
Current assignee: Guangzhou Zhihe Technology Co ltd
Priority date: 2020-10-14
Filing date: 2020-10-14
Publication date: 2021-01-01
Anticipated expiration: 2030-10-14

Abstract

The utility model relates to a high-temperature pressure sensor chip, which comprises a top silicon structure and a bottom SOI structure; the bottom SOI structure is sequentially distributed with a signal processing layer silicon, an insulating layer silicon oxide and a pressure sensing layer silicon from top to bottom, the top silicon structure is provided with a signal leading-out hole and a pressure cavity positioned on the lower surface, and the lower surface of the pressure sensing layer silicon is provided with a pressure leading-out cavity; the signal processing layer silicon comprises four Wheatstone bridge arm resistors R1, R2, R3 and R4, four Wheatstone bridge electrodes E1, E2, E3 and E4 and an isolation bonding layer, and is used for converting a pressure signal into an electric signal. The utility model provides a pressure sensor makes based on the SOI base, uses silicon oxide to replace the PN junction as its insulating layer, and its highest use temperature reaches 500 ℃.

Description

High-temperature pressure sensor chip

Technical Field

The utility model relates to a micro-electromechanical system field especially relates to a high temperature pressure sensor chip.

Background

The pressure sensor is commonly used for detecting the performance, parameters and the like of equipment and products in the modern industrial production process, and is widely applied to various industries such as industrial production, aerospace and the like, wherein the silicon piezoresistive pressure sensor is the most widely applied pressure sensor at present due to the advantages of simple manufacturing process, low cost, high reliability and the like.

The pressure sensor chip is a device which directly senses pressure in the sensor and is a core component of the sensor. At present, the most commonly used PN junction piezoresistive pressure sensor, and when the working temperature exceeds 120 ℃, the silicon material in the pressure chip can conduct electricity reversely at high temperature due to intrinsic excitation, so that the pressure measurement cannot be carried out in the environment of more than 120 ℃. With the development of modern industrial production and aerospace and military application fields, pressure measurement in high-temperature environments is particularly important, and conventional piezoresistive pressure sensors cannot meet the requirements of the fields.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present invention has been made to provide a high temperature pressure sensor chip and a method for manufacturing the same that overcome the above problems or at least partially solve the above problems.

According to one aspect of the present invention, there is provided a high temperature pressure sensor chip comprising a top silicon structure and a bottom SOI structure; the bottom SOI structure is sequentially distributed with a signal processing layer silicon, an insulating layer silicon oxide and a pressure sensing layer silicon from top to bottom, the top silicon structure is provided with a signal leading-out hole and a pressure cavity positioned on the lower surface, and the lower surface of the pressure sensing layer silicon is provided with a pressure leading-out cavity; the signal processing layer silicon comprises four Wheatstone bridge arm resistors R1, R2, R3 and R4, four Wheatstone bridge electrodes E1, E2, E3 and E4 and an isolation bonding layer, and is used for converting a pressure signal into an electric signal.

According to one possible design, the top silicon structure is made using a silicon wafer or a glass wafer.

According to one possible design, the isolation bonding layer is an insulating film of silicon nitride or silicon oxide.

According to another aspect of the present invention, there is provided a method for manufacturing a high temperature pressure sensor chip, including step S101 of cleaning a silicon wafer or a glass wafer, and an SOI wafer; step S102, performing thermal oxidation, namely performing double-sided thermal oxidation on a silicon wafer or a glass wafer and an SOI wafer; step S103, preparing a Wheatstone bridge arm resistor; step S104, flattening the front surface of the SOI; step S105, preparing a pressure guide cavity on the back of the bottom layer SOI structure; step S106, preparing a metal electrode; step S107, preparing a pressure cavity; step S108, preparing a signal leading-out hole; step S109, bonding; step S110, scribing; and step S111, storing.

According to a possible design, the step S101 specifically includes: the silicon wafer or the glass wafer and the SOI wafer are respectively cleaned by ultrasonic cleaning by using acetone and alcohol, and are dried by using nitrogen.

According to one possible design, the step S103 comprises: heavily doping the front surface of the bottom SOI structure to form a doped top silicon layer, wherein the doped top silicon layer is required to be 5 omega/□ -20 omega/□; and after doping is finished, patterning the front surface of the silicon substrate, and etching the top silicon layer in an ICP (inductively coupled plasma) mode until the silicon oxide on the insulating layer is etched.

According to a possible design, the step S105 specifically includes: and patterning the back surface of the bottom layer SOI structure, and corroding the back surface of the silicon by using corrosive liquid to form a pressure-leading cavity.

According to a possible design, the step S107 specifically includes: and patterning the back surface of the silicon wafer, and corroding the back surface of the silicon by using corrosive liquid to form a pressure cavity.

According to a possible design, the step S108 specifically includes: and patterning the front surface of the silicon wafer, and performing deep silicon etching by using ICP (inductively coupled plasma) to form a signal leading-out hole.

The utility model provides a pressure sensor makes based on the SOI base, uses silicon oxide to replace the PN junction as its insulating layer, and its highest use temperature reaches 500 ℃.

The above description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented according to the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the present invention is given.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a piezoresistive chip according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a piezoresistive chip bridge according to an embodiment of the present invention;

description of reference numerals:

11-top silicon structure, 12-bottom SOI structure;

111-signal outlet hole, 112-pressure cavity;

121-signal processing layer silicon, 122-insulating layer silicon oxide, 123-pressure sensing layer silicon and 1231-pressure guide cavity.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The terms "comprises" and "comprising," and any variations thereof, in the described embodiments of the invention, and in the claims and drawings, are intended to cover a non-exclusive inclusion, such as a list of steps or elements.

The technical solution of the present invention will be described in further detail with reference to the accompanying drawings and embodiments.

As shown in fig. 1-2, the embodiment of the present invention provides a high temperature pressure sensor chip, including top layer silicon structure 11 and bottom layer SOI structure 12, bottom layer SOI structure 12 is from top to bottom signal processing layer silicon 121, insulating layer silicon oxide 122 and pressure sensing layer silicon 123 that distribute in proper order, be provided with signal extraction hole 111 and pressure chamber 112 that is located the lower surface on top layer silicon structure 11, the lower surface of pressure sensing layer silicon 123 is provided with pressure induction chamber 1231.

The signal processing layer silicon 121 comprises four Wheatstone bridge arm resistors R1, R2, R3 and R4, four Wheatstone bridge electrodes E1, E2, E3 and E4 and an isolation bonding layer 29. The wheatstone bridge is formed by ICP etching, which requires etching to the silicon oxide insulating layer 122 during the etching process. The lower surface of the pressure sensing layer silicon 123 is provided with a pressure guide cavity 1231. The pressure sensing layer silicon 123 is a part which can directly sense pressure, the pressure sensing cavity 1231 can directly sense pressure, the insulating layer silicon oxide 122 isolates the signal processing layer silicon 121 from the pressure sensing layer silicon 123, the effect of electric insulation is achieved, a PN junction insulating layer structure of a traditional piezoresistive chip structure is replaced, and the signal processing layer silicon 121 is used for converting pressure signals into electric signals.

Because the wheatstone bridge is formed by adopting an etching process, and the silicon surface of the signal processing layer is in a rugged state after etching, before the top layer silicon structure and the bottom layer SOI structure are bonded to form the pressure-insulating cavity, the signal processing layer silicon needs to be subjected to planarization treatment. After the Wheatstone bridge is etched, silicon oxide is deposited on the upper surface of the SOI by a CVD method, the thickness of the silicon oxide is larger than that of the top silicon of the SOI, then the upper surface of the SOI is thinned, and CMP polishing is carried out, so that the flatness and the roughness of the upper surface of the SOI can meet the bonding requirements. And finally, bonding the SOI with the top silicon to form an insulating cavity.

In one example, the top silicon structure 11 is made of a silicon wafer or a glass wafer, and if a glass wafer is used, the bonding method may be anodic bonding.

The embodiment of the utility model provides a still provide a preparation method of high temperature pressure sensor chip, including following step:

and step S101, cleaning. Selecting a silicon wafer or a glass wafer of 4 inches or 6 inches and an SOI wafer, wherein the silicon wafer or the glass wafer is used for preparing a top layer silicon structure 11, the SOI wafer is used for preparing a bottom layer SOI structure 12, the SOI wafer requires that a signal processing layer silicon 121 is P (100) type and has the thickness range of 1-2 mu m, and an insulating layer silicon oxide 122 has the thickness range of 1-2 mu m, and ultrasonically cleaning the silicon wafer or the glass wafer respectively by using acetone and alcohol, and drying the silicon wafer or the glass wafer by using nitrogen.

And step S102, thermal oxidation. Performing double-sided thermal oxidation on a silicon wafer or a glass wafer and an SOI wafer, wherein the thickness of an oxide layer ranges from 47 nm to 53nm, and preferably, the thickness of the oxide layer is 50 nm.

And step S103, preparing a Wheatstone bridge arm resistor. And heavily doping the front surface of the bottom SOI structure 12 to form the doped top silicon layer, wherein the doped top silicon layer is required to be 5 omega/□ -20 omega/□. After doping, the front surface is patterned, and top silicon is etched in an ICP mode, wherein the etching is required to reach the insulating layer silicon oxide 122.

Step S104, the front surface of the SOI is planarized. And depositing low-stress silicon oxide on the front surface of the bottom layer SOI structure 12 by PECVD, wherein the thickness requirement of the silicon oxide is greater than that of the signal processing layer silicon 121, the difference between the thickness of the silicon oxide and the thickness of the signal processing layer silicon 121 is more than 2 mu m, thinning the silicon oxide after the deposition of the silicon oxide is finished, and polishing the silicon oxide by CMP (chemical mechanical polishing) to ensure that the flatness and the roughness of the front surface of the SOI can meet the bonding requirement, namely forming the isolation bonding layer 29.

In step S105, a pressure guiding cavity 1231 on the back side of the bottom SOI structure 12 is prepared. The back side of the bottom layer SOI structure 12 is patterned, and the silicon back side is etched by using an etching solution to form a pressure leading cavity 1231.

And step S106, preparing a metal electrode. The front side of the top layer silicon structure 11 is patterned, a physical vacuum deposition method is adopted for deposition, Cr and Pt films are sequentially deposited to form a Pt metal electrode, wherein the thickness range of Cr is 30-50 nm, and the thickness range of Pt is 100-300 nm. After the metal electrode is prepared, the metal electrode is annealed in a vacuum environment, so that ohmic contact is formed between the metal electrode and the signal processing layer silicon 121.

Step S107, preparing a pressure chamber. The backside of the silicon wafer is patterned and etched with an etching solution to form the pressure chamber 112.

And step S108, preparing a signal leading-out hole. The front surface of the silicon wafer is patterned, and deep silicon etching is performed by using ICP to form a signal lead-out hole 111.

And step S109, bonding. And bonding the silicon wafer and the SOI wafer in a vacuum environment.

And step S110, scribing. And scribing by using a scribing machine after bonding is finished, and cutting the whole wafer into single high-temperature piezoresistive chips.

And step S111, storing. And storing the scribed chips in a drying cabinet or a nitrogen cabinet for later use.

In one example, the isolation bonding layer 29 between the wheatstone bridges may use an insulating film of silicon oxide, and may also use an insulating film of silicon nitride.

In one example, the pressure chamber and the signal leading-out hole can be made of silicon wafers or glass wafers, and if the glass wafers are used, the bonding mode can be anodic bonding;

in one example, the wheatstone bridge may be used not only in a full bridge manner but also in an open bridge manner;

in one example, the chip may have a temperature compensation structure, or a temperature compensation resistor may be fabricated on the chip to form a high temperature piezoresistive chip with temperature compensation function.

The above embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above embodiments are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A high temperature pressure sensor chip comprising a top silicon structure (11) and a bottom SOI structure (12);

the bottom SOI structure (12) is sequentially distributed with a signal processing layer silicon (121), an insulating layer silicon oxide (122) and a pressure sensing layer silicon (123) from top to bottom, the top silicon structure (11) is provided with a signal leading-out hole (111) and a pressure cavity (112) positioned on the lower surface, and the lower surface of the pressure sensing layer silicon (123) is provided with a pressure leading-out cavity (1231);

the signal processing layer silicon (121) comprises four Wheatstone bridge arm resistors R1, R2, R3 and R4, four Wheatstone bridge electrodes E1, E2, E3 and E4 and an isolation bonding layer (29), and the signal processing layer silicon (121) is used for converting a pressure signal into an electric signal.

2. A high temperature pressure sensor die according to claim 1, wherein the top layer silicon structure (11) is made of a silicon wafer or a glass wafer.

3. A high temperature pressure sensor die according to claim 1, characterized in that the isolating bonding layer (29) is an insulating film of silicon nitride or silicon oxide.