CN112174085A - High-temperature pressure sensor chip and preparation method thereof - Google Patents
High-temperature pressure sensor chip and preparation method thereof Download PDFInfo
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- CN112174085A CN112174085A CN202011099028.7A CN202011099028A CN112174085A CN 112174085 A CN112174085 A CN 112174085A CN 202011099028 A CN202011099028 A CN 202011099028A CN 112174085 A CN112174085 A CN 112174085A
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 93
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 74
- 239000010703 silicon Substances 0.000 claims abstract description 74
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 24
- 238000012545 processing Methods 0.000 claims abstract description 18
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 239000011521 glass Substances 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 11
- 238000009616 inductively coupled plasma Methods 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 2
- 238000004506 ultrasonic cleaning Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 38
- 238000013461 design Methods 0.000 description 7
- 238000000151 deposition Methods 0.000 description 3
- 238000009776 industrial production Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000009530 blood pressure measurement Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L1/00—Measuring force or stress, in general
- G01L1/20—Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluids; by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
- G01L9/02—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in ohmic resistance, e.g. of potentiometers, electric circuits therefor, e.g. bridges, amplifiers or signal conditioning
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/02—Sensors
- B81B2201/0264—Pressure sensors
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/03—Bonding two components
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Measuring Fluid Pressure (AREA)
- Pressure Sensors (AREA)
Abstract
The invention relates to a high-temperature pressure sensor chip and a preparation method thereof, wherein the high-temperature pressure sensor chip comprises a top layer silicon structure and a bottom layer SOI structure; the bottom SOI structure is sequentially distributed with a signal processing layer silicon, an insulating layer silicon oxide and a pressure sensing layer silicon from top to bottom, the top silicon structure is provided with a signal leading-out hole and a pressure cavity positioned on the lower surface, and the lower surface of the pressure sensing layer silicon is provided with a pressure leading-out cavity; the signal processing layer silicon comprises four Wheatstone bridge arm resistors R1, R2, R3 and R4, four Wheatstone bridge electrodes E1, E2, E3 and E4 and an isolation bonding layer, and is used for converting a pressure signal into an electric signal. The pressure sensor provided by the invention is manufactured based on an SOI substrate, silicon oxide is used for replacing a PN junction as an insulating layer, and the maximum service temperature reaches 500 ℃.
Description
Technical Field
The invention relates to the field of micro-electromechanical systems, in particular to a high-temperature pressure sensor chip and a preparation method thereof.
Background
The pressure sensor is commonly used for detecting the performance, parameters and the like of equipment and products in the modern industrial production process, and is widely applied to various industries such as industrial production, aerospace and the like, wherein the silicon piezoresistive pressure sensor is the most widely applied pressure sensor at present due to the advantages of simple manufacturing process, low cost, high reliability and the like.
The pressure sensor chip is a device which directly senses pressure in the sensor and is a core component of the sensor. At present, the most commonly used PN junction piezoresistive pressure sensor, and when the working temperature exceeds 120 ℃, the silicon material in the pressure chip can conduct electricity reversely at high temperature due to intrinsic excitation, so that the pressure measurement cannot be carried out in the environment of more than 120 ℃. With the development of modern industrial production and aerospace and military application fields, pressure measurement in high-temperature environments is particularly important, and conventional piezoresistive pressure sensors cannot meet the requirements of the fields.
Disclosure of Invention
In view of the above problems, the present invention has been made to provide a high temperature pressure sensor chip and a method for manufacturing the same that overcome or at least partially solve the above problems.
According to one aspect of the present invention, there is provided a high temperature pressure sensor chip comprising a top silicon structure and a bottom SOI structure; the bottom SOI structure is sequentially distributed with a signal processing layer silicon, an insulating layer silicon oxide and a pressure sensing layer silicon from top to bottom, the top silicon structure is provided with a signal leading-out hole and a pressure cavity positioned on the lower surface, and the lower surface of the pressure sensing layer silicon is provided with a pressure leading-out cavity; the signal processing layer silicon comprises four Wheatstone bridge arm resistors R1, R2, R3 and R4, four Wheatstone bridge electrodes E1, E2, E3 and E4 and an isolation bonding layer, and is used for converting a pressure signal into an electric signal.
According to one possible design, the top silicon structure is made using a silicon wafer or a glass wafer.
According to one possible design, the isolation bonding layer is an insulating film of silicon nitride or silicon oxide.
According to another aspect of the present invention, there is provided a method for manufacturing a high temperature pressure sensor chip, including step S101 of cleaning a silicon wafer or a glass wafer, and an SOI wafer; step S102, performing thermal oxidation, namely performing double-sided thermal oxidation on a silicon wafer or a glass wafer and an SOI wafer; step S103, preparing a Wheatstone bridge arm resistor; step S104, flattening the front surface of the SOI; step S105, preparing a pressure guide cavity on the back of the bottom layer SOI structure; step S106, preparing a metal electrode; step S107, preparing a pressure cavity; step S108, preparing a signal leading-out hole; step S109, bonding; step S110, scribing; and step S111, storing.
According to a possible design, the step S101 specifically includes: the silicon wafer or the glass wafer and the SOI wafer are respectively cleaned by ultrasonic cleaning by using acetone and alcohol, and are dried by using nitrogen.
According to one possible design, the step S103 comprises: heavily doping the front surface of the bottom SOI structure to form a doped top silicon layer, wherein the doped top silicon layer is required to be 5 omega/□ -20 omega/□; and after doping is finished, patterning the front surface of the silicon substrate, and etching the top silicon layer in an ICP (inductively coupled plasma) mode until the silicon oxide on the insulating layer is etched.
According to a possible design, the step S105 specifically includes: and patterning the back surface of the bottom layer SOI structure, and corroding the back surface of the silicon by using corrosive liquid to form a pressure-leading cavity.
According to a possible design, the step S107 specifically includes: and patterning the back surface of the silicon wafer, and corroding the back surface of the silicon by using corrosive liquid to form a pressure cavity.
According to a possible design, the step S108 specifically includes: and patterning the front surface of the silicon wafer, and performing deep silicon etching by using ICP (inductively coupled plasma) to form a signal leading-out hole.
The pressure sensor provided by the invention is manufactured based on an SOI substrate, silicon oxide is used for replacing a PN junction as an insulating layer, and the maximum service temperature reaches 500 ℃.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a piezoresistive chip according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a piezoresistive chip bridge according to an embodiment of the present invention;
description of reference numerals:
11-top silicon structure, 12-bottom SOI structure;
111-signal outlet hole, 112-pressure cavity;
121-signal processing layer silicon, 122-insulating layer silicon oxide, 123-pressure sensing layer silicon and 1231-pressure guide cavity.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The terms "comprises" and "comprising," and any variations thereof, in the present description and claims and drawings are intended to cover a non-exclusive inclusion, such as a list of steps or elements.
The technical solution of the present invention is further described in detail with reference to the accompanying drawings and embodiments.
As shown in fig. 1-2, an embodiment of the present invention provides a high temperature pressure sensor chip, which includes a top layer silicon structure 11 and a bottom layer SOI structure 12, where the bottom layer SOI structure 12 includes, from top to bottom, a signal processing layer silicon 121, an insulating layer silicon oxide 122, and a pressure sensing layer silicon 123, which are sequentially distributed, the top layer silicon structure 11 is provided with a signal leading-out hole 111 and a pressure cavity 112 located on a lower surface, and the lower surface of the pressure sensing layer silicon 123 is provided with a pressure leading cavity 1231.
The signal processing layer silicon 121 comprises four Wheatstone bridge arm resistors R1, R2, R3 and R4, four Wheatstone bridge electrodes E1, E2, E3 and E4 and an isolation bonding layer 29. The wheatstone bridge is formed by ICP etching, which requires etching to the silicon oxide insulating layer 122 during the etching process. The lower surface of the pressure sensing layer silicon 123 is provided with a pressure guide cavity 1231. The pressure sensing layer silicon 123 is a part which can directly sense pressure, the pressure sensing cavity 1231 can directly sense pressure, the insulating layer silicon oxide 122 isolates the signal processing layer silicon 121 from the pressure sensing layer silicon 123, the effect of electric insulation is achieved, a PN junction insulating layer structure of a traditional piezoresistive chip structure is replaced, and the signal processing layer silicon 121 is used for converting pressure signals into electric signals.
Because the wheatstone bridge is formed by adopting an etching process, and the silicon surface of the signal processing layer is in a rugged state after etching, before the top layer silicon structure and the bottom layer SOI structure are bonded to form the pressure-insulating cavity, the signal processing layer silicon needs to be subjected to planarization treatment. After the Wheatstone bridge is etched, silicon oxide is deposited on the upper surface of the SOI by a CVD method, the thickness of the silicon oxide is larger than that of the top silicon of the SOI, then the upper surface of the SOI is thinned, and CMP polishing is carried out, so that the flatness and the roughness of the upper surface of the SOI can meet the bonding requirements. And finally, bonding the SOI with the top silicon to form an insulating cavity.
In one example, the top silicon structure 11 is made of a silicon wafer or a glass wafer, and if a glass wafer is used, the bonding method may be anodic bonding.
The embodiment of the invention also provides a preparation method of the high-temperature pressure sensor chip, which comprises the following steps:
and step S101, cleaning. Selecting a silicon wafer or a glass wafer of 4 inches or 6 inches and an SOI wafer, wherein the silicon wafer or the glass wafer is used for preparing a top layer silicon structure 11, the SOI wafer is used for preparing a bottom layer SOI structure 12, the SOI wafer requires that a signal processing layer silicon 121 is P (100) type and has the thickness range of 1-2 mu m, and an insulating layer silicon oxide 122 has the thickness range of 1-2 mu m, and ultrasonically cleaning the silicon wafer or the glass wafer respectively by using acetone and alcohol, and drying the silicon wafer or the glass wafer by using nitrogen.
And step S102, thermal oxidation. Performing double-sided thermal oxidation on a silicon wafer or a glass wafer and an SOI wafer, wherein the thickness of an oxide layer ranges from 47 nm to 53nm, and preferably, the thickness of the oxide layer is 50 nm.
And step S103, preparing a Wheatstone bridge arm resistor. And heavily doping the front surface of the bottom SOI structure 12 to form the doped top silicon layer, wherein the doped top silicon layer is required to be 5 omega/□ -20 omega/□. After doping, the front surface is patterned, and top silicon is etched in an ICP mode, wherein the etching is required to reach the insulating layer silicon oxide 122.
Step S104, the front surface of the SOI is planarized. And depositing low-stress silicon oxide on the front surface of the bottom layer SOI structure 12 by PECVD, wherein the thickness requirement of the silicon oxide is greater than that of the signal processing layer silicon 121, the difference between the thickness of the silicon oxide and the thickness of the signal processing layer silicon 121 is more than 2 mu m, thinning the silicon oxide after the deposition of the silicon oxide is finished, and polishing the silicon oxide by CMP (chemical mechanical polishing) to ensure that the flatness and the roughness of the front surface of the SOI can meet the bonding requirement, namely forming the isolation bonding layer 29.
In step S105, a pressure guiding cavity 1231 on the back side of the bottom SOI structure 12 is prepared. The back side of the bottom layer SOI structure 12 is patterned, and the silicon back side is etched by using an etching solution to form a pressure leading cavity 1231.
And step S106, preparing a metal electrode. The front side of the top layer silicon structure 11 is patterned, a physical vacuum deposition method is adopted for deposition, Cr and Pt films are sequentially deposited to form a Pt metal electrode, wherein the thickness range of Cr is 30-50 nm, and the thickness range of Pt is 100-300 nm. After the metal electrode is prepared, the metal electrode is annealed in a vacuum environment, so that ohmic contact is formed between the metal electrode and the signal processing layer silicon 121.
Step S107, preparing a pressure chamber. The backside of the silicon wafer is patterned and etched with an etching solution to form the pressure chamber 112.
And step S108, preparing a signal leading-out hole. The front surface of the silicon wafer is patterned, and deep silicon etching is performed by using ICP to form a signal lead-out hole 111.
And step S109, bonding. And bonding the silicon wafer and the SOI wafer in a vacuum environment.
And step S110, scribing. And scribing by using a scribing machine after bonding is finished, and cutting the whole wafer into single high-temperature piezoresistive chips.
And step S111, storing. And storing the scribed chips in a drying cabinet or a nitrogen cabinet for later use.
In one example, the isolation bonding layer 29 between the wheatstone bridges may use an insulating film of silicon oxide, and may also use an insulating film of silicon nitride.
In one example, the pressure chamber and the signal leading-out hole can be made of silicon wafers or glass wafers, and if the glass wafers are used, the bonding mode can be anodic bonding;
in one example, the wheatstone bridge may be used not only in a full bridge manner but also in an open bridge manner;
in one example, the chip may have a temperature compensation structure, or a temperature compensation resistor may be fabricated on the chip to form a high temperature piezoresistive chip with temperature compensation function.
The above embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above embodiments are merely exemplary embodiments of the present invention and are not intended to limit the scope of the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (9)
1. A high temperature pressure sensor chip comprising a top silicon structure (11) and a bottom SOI structure (12);
the bottom SOI structure (12) is sequentially distributed with a signal processing layer silicon (121), an insulating layer silicon oxide (122) and a pressure sensing layer silicon (123) from top to bottom, the top silicon structure (11) is provided with a signal leading-out hole (111) and a pressure cavity (112) positioned on the lower surface, and the lower surface of the pressure sensing layer silicon (123) is provided with a pressure leading-out cavity (1231);
the signal processing layer silicon (121) comprises four Wheatstone bridge arm resistors R1, R2, R3 and R4, four Wheatstone bridge electrodes E1, E2, E3 and E4 and an isolation bonding layer (29), and the signal processing layer silicon (121) is used for converting a pressure signal into an electric signal.
2. A high temperature pressure sensor die according to claim 1, wherein the top layer silicon structure (11) is made of a silicon wafer or a glass wafer.
3. A high temperature pressure sensor die according to claim 1, characterized in that the isolating bonding layer (29) is an insulating film of silicon nitride or silicon oxide.
4. A method of manufacturing a high temperature pressure sensor chip according to any of claims 1 to 3, comprising:
step S101, cleaning a silicon wafer or a glass wafer and an SOI wafer;
step S102, performing thermal oxidation, namely performing double-sided thermal oxidation on a silicon wafer or a glass wafer and an SOI wafer;
step S103, preparing a Wheatstone bridge arm resistor;
step S104, flattening the front surface of the SOI;
step S105, preparing a pressure guide cavity (1231) on the back surface of the bottom layer SOI structure (12);
step S106, preparing a metal electrode;
step S107, preparing a pressure chamber (112);
step S108, preparing a signal leading-out hole (111);
step S109, bonding;
step S110, scribing;
and step S111, storing.
5. The method according to claim 4, wherein the step S101 specifically comprises:
the silicon wafer or the glass wafer and the SOI wafer are respectively cleaned by ultrasonic cleaning by using acetone and alcohol, and are dried by using nitrogen.
6. The method according to claim 4, wherein the step S103 includes:
heavily doping the front surface of the bottom SOI structure (12) to form a doped top silicon layer, wherein the doped top silicon layer is required to be 5 omega/□ -20 omega/□;
after doping is finished, the front surface of the silicon substrate is patterned, and top silicon is etched in an ICP mode and is required to be etched to the position of the insulation layer silicon oxide (122).
7. The method according to claim 4, wherein the step S105 specifically comprises:
the back surface of the bottom SOI structure (12) is patterned, and the back surface of the silicon is etched by using an etching solution to form a pressure-leading cavity (1231).
8. The method according to claim 4, wherein the step S107 specifically comprises:
the back surface of the silicon wafer is patterned, and the back surface of the silicon is etched by using an etching solution to form a pressure chamber (112).
9. The method according to claim 4, wherein the step S108 specifically comprises:
and patterning the front surface of the silicon wafer, and performing deep silicon etching by using ICP (inductively coupled plasma) to form a signal leading-out hole (111).
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115127700A (en) * | 2022-08-31 | 2022-09-30 | 南京元感微电子有限公司 | High-temperature-resistant pressure sensor and processing method thereof |
| CN115144122A (en) * | 2022-08-31 | 2022-10-04 | 南京元感微电子有限公司 | High-temperature-resistant pressure sensor with multilayer structure and processing method thereof |
| CN116295967A (en) * | 2023-05-23 | 2023-06-23 | 无锡胜脉电子有限公司 | High-voltage MEMS pressure sensor chip and preparation method of chip and sensor |
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| CN212269452U (en) * | 2020-10-14 | 2021-01-01 | 广州市智芯禾科技有限责任公司 | High-temperature pressure sensor chip |
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2020
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| US5591679A (en) * | 1995-04-12 | 1997-01-07 | Sensonor A/S | Sealed cavity arrangement method |
| CN105021328A (en) * | 2015-07-13 | 2015-11-04 | 厦门大学 | Piezoresistive pressure sensor compatible with CMOS process and preparation method of piezoresistive pressure sensor |
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| CN116295967A (en) * | 2023-05-23 | 2023-06-23 | 无锡胜脉电子有限公司 | High-voltage MEMS pressure sensor chip and preparation method of chip and sensor |
| CN116295967B (en) * | 2023-05-23 | 2023-08-11 | 无锡胜脉电子有限公司 | High-voltage MEMS pressure sensor chip and preparation method of chip and sensor |
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| CN112174085B (en) | 2024-09-06 |
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