CN211956463U

CN211956463U - I/O (input/output) bridge piece based on Feiteng processor

Info

Publication number: CN211956463U
Application number: CN202020307046.9U
Authority: CN
Inventors: 付迪; 冯建东; 徐文; 熊涛; 杨发; 陈志伟; 刘剑
Original assignee: Guangzhou Chaoyun Technology Co ltd
Current assignee: Beijing Tiandi Huiyun Technology Co.,Ltd.
Priority date: 2020-03-12
Filing date: 2020-03-12
Publication date: 2020-11-17
Anticipated expiration: 2030-03-12

Abstract

A processor-based I/O bridge chip comprises a Feiteng processor and an I/O bridge chip; the upstream of the I/O bridge chip is connected with the Feiteng processor through a PCIE bus; the I/O bridge chip is internally integrated with a 2D display card, an SATA controller, a USB controller, a PCIE interface, an RGMII interface and a VGA display interface; the SATA controller outputs an SATA interface, the USB controller outputs a USB interface, the PHY chip is mounted under the RGMII interface, and the 2D display card is applied to the VGA display interface. The utility model relates to a simply, the cost is lower, the integrated level is high, the interface kind is abundant, can satisfy the user demand of user to the PC mainboard.

Description

I/O (input/output) bridge piece based on Feiteng processor

Technical Field

The utility model relates to a computer field especially relates to a IO bridge plate based on processor soars.

Background

With the big background of the promotion of national information security, the information security problem is increasingly emphasized, and the construction for strengthening the information security is not slow enough. At present, home-made processors under national information security are also in a mass emergence, and an ARM architecture, an X86 architecture, an MIPS architecture and the like are available. However, the technical solutions of the platform products are different due to different architectures of the processors. The architecture based on the Feiteng storage processor is the most popular ARM architecture at present, but the processor is only simply integrated with PCIE and an MCU controller and is not integrated in the processor, and common peripheral interfaces such as SATA, USB serial bus, VGA display and the like are not integrated in a main chip and are necessary for a PC mainboard. The number of interfaces based on the FT processor itself is limited.

The design of an I/O (input/output) bridge chip based on a Feiteng processor has the advantages that the existing traditional technical scheme is relatively complex, the cost is high, the integration level is low, the use requirement of a user on a product is far from being met, and the problem becomes a problem to be solved by technical personnel in the field.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide an IO bridgeware based on it is soar to solve the aforementioned problem that exists among the prior art.

In order to realize the purpose, the utility model discloses a technical scheme as follows:

an I/O (input/output) bridge chip based on a Feiteng processor comprises the Feiteng processor and the I/O bridge chip; the upstream of the I/O bridge chip is connected with the Feiteng processor through a PCIE bus; the I/O bridge chip is internally integrated with a 2D display card, an SATA controller, a USB controller, a PCIE interface, an RGMII interface and a VGA display interface; the SATA controller outputs an SATA interface, the USB controller outputs a USB interface, the PHY chip is mounted under the RGMII interface, and the 2D display card is applied to the VGA display interface.

Preferably, the PCIE interface is an HOST end of a PCIE device, and may be used to connect a PCIE X16 slot and a PCIE X8 slot, and also mount an m.2 or NVMe interface.

Preferably, the PHY chip implements an output gigabit network interface.

Preferably, the VGA display interface implements display output.

The utility model has the advantages that: the I/O bridge sheet based on the Feiteng processor can expand the interface of the Feiteng processor through the USB controller, the SATA controller and the PCIE interface which are integrated in the I/O bridge sheet, and solves the situation that the interface resource of the Feiteng processor is insufficient; the flexibility of the design of developers is improved by multiple selectivity of the PCIE interface integrated inside; IO bridgeware based on Feiteng designs simply, the cost is lower, the integrated level is high, the interface kind is abundant, can satisfy the user demand of user to the PC mainboard.

Drawings

FIG. 1 is a block diagram of an IO bridge chip architecture.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the invention, are given by way of illustration only.

An IO bridge sheet based on a Feiteng processor comprises the Feiteng processor and an I/O bridge sheet; the upstream of the I/O bridge chip is connected with the Feiteng processor through a PCIE bus; the I/O bridge chip is internally integrated with a 2D display card, an SATA controller, a USB controller, a PCIE interface, an RGMII interface and a VGA display interface; the SATA controller outputs an SATA interface, the USB controller outputs a USB interface, the PHY chip is mounted under the RGMII interface, and the 2D display card is applied to the VGA display interface.

The Feiteng processor is of an ARM (advanced RISC machine) framework, a memory controller interface is integrated inside the Feiteng processor, and the operation data of the Feiteng processor and the data exchanged with an external memory are temporarily stored through an external memory strip of the memory controller interface; and a PCIE interface is further integrated and used as the upstream of a PCIE bus of the I/O bridge chip, and the PCIE bus is connected with the I/O bridge chip to realize data communication between the Feiteng processor and the I/O bridge chip.

A PCIE interface integrated in the I/O bridge chip is used as the downstream of a PCIE bus of the Feiteng processor and is connected with the Feiteng processor through the PCIE bus, so that real-time data communication between the Feiteng processor and the I/O bridge chip is realized, and the PCIE interface of the Feiteng processor is expanded; the other PCIE interface is used as an HOST end of the PCIE equipment, can be used for connecting a PCIE X16 slot and a PCIE X8 slot, and can also be used for directly mounting an M.2 or NVMe interface, so that the storage performance is improved; the USB controller can directly lead out a USB interface for developers to design a universal USB peripheral interface or USB equipment; the SATA controller can directly lead out an SATA interface for developers to design a universal SATA peripheral interface; the RGMII interface is a network protocol interface and outputs a kilomega network interface by mounting the PHY chip; the VGA display interface is internally integrated with a 2D display card, and standard display output of the VGA display interface is realized.

Examples

In the I/O bridge based on the FT processor in this embodiment, the FT processor employs a FT 2000+ processor, the I/O bridge employs a mega-core ZX-200 bridge, and a USB interface led out from the USB controller supports the USB3.0 specification and is downward compatible with the USB2.0 interface specification; the PHY chip mounted on the RGMII interface adopts a low-cost BCM5461S chip. Finally, the various components described above are placed on a printed circuit board.

Through adopting the utility model discloses an above-mentioned technical scheme has obtained following profitable effect:

the T/O bridge sheet based on the Feiteng processor can expand the interface of the Feiteng processor through the USB controller, the SATA controller and the PCIE interface which are integrated in the T/O bridge sheet, and solves the situation that the interface resource of the Feiteng processor is insufficient; the flexibility of the design of developers is improved by multiple selectivity of the PCIE interface integrated inside; IO bridgeware based on Feiteng designs simply, the cost is lower, the integrated level is high, the interface kind is abundant, can satisfy the user demand of user to the PC mainboard.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be viewed as the protection scope of the present invention.

Claims

1. An I/O bridge chip based on a Feiteng processor is characterized by comprising the Feiteng processor and the I/O bridge chip; the upstream of the I/O bridge chip is connected with the Feiteng processor through a PCIE bus; the I/O bridge chip is internally integrated with a 2D display card, an SATA controller, a USB controller, a PCIE interface, an RGMII interface and a VGA display interface; the SATA controller outputs an SATA interface, the USB controller outputs a USB interface, the PHY chip is mounted under the RGMII interface, and the 2D display card is applied to the VGA display interface.

2. The Feiteng processor-based I/O bridge chip according to claim 1, wherein the PCIE interface is an HOST port of a PCIE device, and can be used to connect a PCIE X16 slot and a PCIE X8 slot, and can also mount an M.2 or NVMe interface.

3. The Feiteng processor-based I/O bridge chip according to claim 1, wherein the PHY chip implements an output gigabit network interface.

4. A FT processor-based I/O bridge as claimed in claim 1, wherein the VGA display interface implements a display output.