CN202838317U - Bus unit and rear panel system - Google Patents

Abstract

The utility model discloses a bus device and a rear panel system including the same. The bus unit comprises a central processing unit (CPU) bus, a bus converter and a peripheral component interconnect (PCI) / peripheral component interconnect express (PCIe) bus, wherein a panel card of one side of a rear panel is connected with the bus converter in a communication mode through the CPU bus, the bus converter is connected with access main equipment in a communication mode through the PCI / PCIe bus, and the bus converter is used for conversion between the PCI / PCIe bus and the CPU bus. According to the rear panel system, the bus converter is arranged, so the rear panel system only needs to be connected in a communication mode through the CPU bus, and high-speed and low-speed panel cards of various types can be expanded easily.

Description

Bus device and backplane system

technical field

The utility model relates to the communication field, in particular to a bus device and a backboard system.

Background technique

In highly integrated electronic equipment, slots are often used to improve the flexibility of the product. Through the flexible configuration of various types of cards, the diversification of product functions can be realized, and the development cost and material cost of the product can be reduced at the same time. Improved product scalability. Currently, a backplane system is usually used _to implement the above-mentioned applications. As shown in FIG _. ... 110 _k ), and the bus device 120 . The board can be a service board and/or a signal board, and is used for service processing and/or signal interconnection between boards. Because a backplane can expand as few as a few or as many as a dozen functional boards, it can greatly improve the integration of the product. Each board is connected to the access master device 200 (the access master device 200 includes the CPU 210 ) and each board card is connected through a bus device, so as to realize data interaction and finally realize the functions of the whole machine.

In the current backplane system, different bus devices are used according to the difference of the CPU 210 of the access master device 200 connected to the board. For example, when the access master device 200 is a platform such as ARM/DSP (wherein, ARM is the abbreviation of Advanced RISC Machines, indicating a type of microprocessor based on the British ARM company; DSP is the abbreviation of Digital Signal Processor, indicating a signal processor) , as shown in FIG. 1, the bus device 120 generally adopts a common CPU bus, which has low cost and good expansion flexibility, and is easy to realize low-cost expansion of low-speed devices, but the bus speed is relatively low. For another example, in the access master device 200 that requires high-speed data transmission, such as in the X86 platform, as shown in FIG. 2 , the bus device 120 generally includes PCI: Peripheral Component Interconnect : Peripheral Component Interconnect Express) bus for communication connection, this type of bus device 120 can realize high-speed data interaction at a speed of G. Compared with the traditional CPU bus, the PCI/PCIe bus can increase the data transmission rate. However, in this solution, the bus device 120 is required to further include a bridge group 122 , and the bridge group 122 is communicatively connected with the access master device 200 through the PCI/PCIe bus 121 . _The bridge group 122 _is composed _of one or more bridges 122 ₁ , 122 _{2 .} Since each board must be equipped with a PCI/PCIe bridge, the cost is high.

Utility model content

The technical problem to be solved by the utility model is to provide a bus device for the defect of low backplane expandability in the prior art; to provide a backplane system for the defect of low backplane expandability in the prior art.

The technical solution adopted by the utility model to solve the technical problems is: according to one aspect of the utility model, a bus device is provided, including a CPU bus, a PCI/PCIe bus, and a bus for the PCI/PCIe bus and the A bus converter for data flow conversion between CPU buses; wherein,

The board arranged on one side of the backplane communicates with the bus converter through the CPU bus;

The bus converter communicates with the access master device through the PCI/PCIe bus.

In the bus device according to the embodiment of the utility model, the bus converter includes:

A bus analysis module for resolving data and address information multiplexed in the PCI/PCIe bus into independent data information and independent address information;

Connected to the bus analysis module, used for mapping the independent data information to the data lines of the CPU bus, and mapping the independent address information to the bus conversion mapping in the address lines of the CPU bus module.

In the bus device according to the embodiment of the present utility model, the bus converter further includes a chip select signal generation module for generating a corresponding chip select signal according to the access address of the board.

In the bus device according to the present utility model, the bus converter also includes a board control line analysis module for parsing the PCI/PCIe bus to obtain board control information, wherein the board control information includes independent Interrupt signal information, card detection signal information, read and write control information, and board reset signal information.

In the bus device according to the present utility model, the bus converter further includes a backplane manager communicatively connected to the board control line analysis module, and the backplane manager includes:

An interrupt control unit for interrupting the communication connection of the board through the interrupt signal information obtained by the board control line analysis module;

A card detection unit for identifying the board according to the card detection signal information obtained by the board control line analysis module;

A read-write control unit for controlling the read-write operation and/or write operation of the board through the read-write control information acquired by the board control line analysis module; and

A board reset unit for resetting the board through the board reset signal information acquired by the board control line analysis module.

In the bus device according to the embodiment of the present utility model, the bus converter is a bus converter based on FPGA or ASIC.

According to another aspect of the present utility model, a bus device is also provided, including a CPU bus, an SPI bus, and a timing sequence for simulating the SPI device through the CPU bus so as to transmit data streams from the SPI bus converting a bus converter mapped to the CPU bus; wherein,

The board arranged on one side of the backplane communicates with the bus converter through the CPU bus;

The bus converter is communicatively connected with the SPI device through the SPI bus.

In the bus device according to the embodiment of the present utility model, the bus converter is a bus converter based on a hardware interface circuit.

According to another aspect of the present invention, a backplane system is also provided, and the backplane system includes any one of the above-mentioned bus devices.

In the backplane system according to the embodiment of the present utility model, the backplane system further includes a backplane and one or more boards arranged on one side of the backplane, wherein the boards communicate with the access The master device is in communication connection, and the boards are in communication connection with each other through the bus device.

The beneficial effects of the utility model are: in the backplane system of the utility model, by setting the bus converter, the backplane system only needs to be connected through the CPU bus communication, so it is easier to expand various high-speed and low-speed boards .

Description of drawings

The utility model will be further described below in conjunction with accompanying drawing and embodiment, in the accompanying drawing:

FIG. 1 is a schematic structural diagram of a backplane system in the prior art;

Fig. 2 is a structural schematic diagram when the backplane system in Fig. 1 adopts PCI/PCIe bus;

Fig. 3 is a schematic structural diagram of a backplane system according to an embodiment of the present invention;

Fig. 4 is the schematic diagram that is used to describe the conversion between PCI/PCIe bus and CPU bus in Fig. 3;

Fig. 5 is a logical block diagram of the bus converter in Fig. 3;

FIG. 6 is a schematic structural diagram of a backplane system according to another embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solution and advantages of the utility model clearer, the utility model will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model, and are not intended to limit the utility model.

Figure 3 shows a logical block diagram of a backplane system according to an embodiment of the present invention. The backplane system includes a backplane (not shown in the figure), a board card 310 arranged on one side of the backplane (in this embodiment , specifically boards 310 ₁ , 310 ₂ ... 310 _k ), and a bus device for communication connection. Wherein, the board 310 communicates with the access master device 200 through the bus device, and the boards communicate with each other through the bus device.

In an embodiment of the present invention, the board 310 may be a service board and/or a signal board. The access master device 200 may be any type of access device, including but not limited to the aforementioned X86 platform that requires high-speed data transmission.

The bus device in the embodiment of the utility model includes: a CPU bus 323 , a PCI/PCIe bus 322 and a bus converter 321 . As shown in FIG. 3 , the board 310 communicates with the bus converter 321 through the CPU bus 323 ; the bus converter 321 communicates with the board 310 and the access master device 200 through the CPU bus 323 and the PCI/PCIe bus 322 respectively. The bus converter 321 is used for the signal information conversion between the PCI/PCIe bus 322 and the CPU bus 323, so that the access master device 200 realizes the board card 310 through the PCI/PCIe bus 322, the bus converter 321, and the CPU bus 323. access.

In the embodiment of the present utility model, the CPU bus 323 is a low-speed bus compared to the PCI/PCIe bus 322, including but not limited to data lines, address lines, read and write control lines, chip selection control lines, interrupt signal lines, reset Key signal lines such as signal lines, general IO lines, card detection signal lines, power lines, and ground lines.

Compared with the PCI/PCIe bus 322, the CPU bus 323 has the advantages of lower cost, better expansion flexibility, and low-cost expansion of low-speed devices, but the data transmission speed is low, and it is usually only applicable to data transmission. The access master device 200 with lower speed requirements, such as the ARM/DSP platform mentioned above. PCI/PCIe bus 322 includes a conventional PCI bus or a PCIe bus.

The bus converter 321 is preferably a bus converter 321 based on FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit). In an embodiment of the present invention, the bus converter 321 may be an FPGA-based bus converter 321 . Those skilled in the art should know that the above-mentioned bus converter 321 is only used as an example, and is not a limitation of the present invention. Any programmable device applicable to the above-mentioned conversion function can be used as the bus converter 321 .

As shown in FIG. 4 and FIG. 5 , the bus converter 321 includes a bus analysis module 31 , a bus conversion mapping module 32 , a chip select signal generation module 33 , a board control line analysis module 34 and a backplane manager 35 . Wherein, the bus analysis module 31 is interconnected with the PCI/PCIe bus 322 and the bus conversion mapping module 32 respectively, and the bus conversion mapping module 32 is interconnected with the CPU bus 323; the chip selection signal generation module 33 is connected with the bus analysis module 31 and the CPU bus 323 The board control line analysis module 34 is interconnected with the PCI/PCIe bus 322 and the backplane manager 35 respectively, and the backplane manager 35 is interconnected with the CPU bus 323 .

The bus analysis module 31 can analyze the PCI/PCIe bus 322, so as to extract each independent signal information from the multiplexed signal information in the PCI/PCIe bus 322, such as extracting independent data from the multiplexed data and address information Information and independent address information, and further extract independent clock information, data transmission status information, bus status information and other key signal information from the multiplexed signal information. Since the PCI/PCIe bus adopts a time-division multiplexing mode of operation, various signal information is multiplexed, so the independent data information and address information and other independent signal information obtained by analyzing the bus analysis module 31 here can ensure that the subsequent bus The conversion mapping module 32 can convert and map the data flow transmitted by the PCI/PCIe bus 322 to the CPU bus 323 for transmission.

The bus conversion and mapping module 32 is connected to the bus analysis module 31, and the bus conversion and mapping module 32 can map the independent signal information analyzed by the bus analysis module 31 to the signal line of the CPU bus. For example, the bus conversion mapping module 32 can map the independent data information analyzed by the bus analyzing module 31 to the data lines of the CPU bus, and map the independent address information analyzed by the bus analyzing module 31 to the address lines of the CPU bus. This conversion mapping process can adopt various applicable methods to carry out, for example, bus converter 321 can map the address space based on CPU bus 323 to access the chip to the storage space or IO space of PCI/PCIe bus 322, and then access master device 200 The CPU in the CPU acts as an initiator (the initiator of the PCI operation) to access the CPU bus 323 through PCI memory read or memory write operations. Of course, other ways can also be used to perform conversion mapping, which will not be repeated here.

The chip selection signal generation module 33 is directly connected with the CPU bus 323 in communication, the chip selection signal generation module 33 can obtain the access address of the board card 310 from the address information analyzed by the bus analysis module 31, and generate a corresponding chip selection signal to support multiple The parallel work of each board makes it easier to expand and manage the board.

The board control line analysis module 34 can analyze and extract independent board control information from the PCI/PCIe bus 322, so as to control and manage the work of each board through the board control information. The above board control information specifically includes independent interrupt signal information, card insertion detection signal information, read and write control information, and board reset signal information.

The backplane manager 35 connected to the board control line analysis module 34 controls and manages the work of the board card through the CPU bus 323 based on the board control line analysis module 34 analyzing and extracting each board control information from the PCI/PCIe bus 322 .

Correspondingly, the backplane manager 35 includes: an interrupt control unit, a card insertion detection unit, a read-write control unit, and a board reset unit. Wherein, the interrupt control unit interrupts the communication connection of the board card by interrupting signal information; the card detection unit identifies the board card according to the card detection signal information; the read-write control unit controls the read operation and/or operation of the board card by reading and writing control information Or write operation; the board card reset unit resets the board card through the board card reset signal information.

In the above embodiments, the access master device 200 may be a device requiring high-speed data transmission, such as an X86 platform. In the example of the X86 platform, the boards in the backplane system are usually a digital quantity acquisition module, an analog quantity acquisition module, an 8-way serial port module, and a flash memory module. For this type of access master device 200 , in a conventional backplane system, its bus device must include a PCI/PCIe bus 322 and a bridge to realize the communication connection between the backplane and the access master device 200 . However, in this embodiment, by setting the bus converter, on the one hand, the bridges corresponding to each board are omitted, thereby saving costs.

On the other hand, the backplane system only needs to be connected through the CPU bus 323 for communication, so it is easier to expand various high-speed and low-speed boards. At the same time, the technical solution provided by the utility model still ensures that the access master device 200 communicates through the PCI/PCIe bus 322, thereby ensuring high-speed transmission speed; /PCIe bus for data interaction, and does not know whether the access to the backplane system is through the high-level PCI/PCIe bus or through the relatively low-speed CPU bus, so it will not affect the access to the upper layer software in the master device 200 to the bottom layer of the backplane system hardware access.

As shown in Figure 6, in the backplane system according to another embodiment of the present utility model, the access master device 200 is an SPI (Serial External Interface) device, and the bus device includes a CPU bus 423, a bus converter 421 and an SPI Bus 422; wherein, the boards 410 (specifically, for example, boards 410 ₁ , 410 ₂ ... 410 _k ) arranged on the side of the backplane are communicatively connected to the bus converter 421 through the CPU bus 423; the bus converter 421 is connected through the SPI bus 422 is communicatively connected with the SPI device 200; the bus converter 421 is used to simulate the timing of the SPI device 200 through the CPU bus 423, so as to convert and map the data stream transmitted from the SPI bus 422 to the CPU bus 423 for transmission. At this time, there is only a small amount of data interaction in the backplane, so the bus converter may be a bus converter based on a hardware interface circuit.

It can be further seen from this embodiment that since the backplane system only needs to be connected through the CPU bus for communication, it has good scalability and can be used for example on an X86 platform or an SPI device.

It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should belong to the protection scope of the appended claims of the present utility model.

Claims (10)

1. a bus device, is characterized in that, comprises CPU bus, PCI/PCIe bus and is used for the bus converter of data stream conversion between described PCI/PCIe bus and described CPU bus; Wherein, The board arranged on one side of the backplane communicates with the bus converter through the CPU bus; The bus converter communicates with the access master device through the PCI/PCIe bus. 2. The bus device according to claim 1, wherein the bus converter comprises: A bus analysis module for resolving data and address information multiplexed in the PCI/PCIe bus into independent data information and independent address information; Connected to the bus analysis module, used for mapping the independent data information to the data lines of the CPU bus, and mapping the independent address information to the bus conversion mapping in the address lines of the CPU bus module. 3. The bus device according to claim 1, wherein the bus converter also includes a chip selection signal generating module for generating a corresponding chip selection signal according to the access address of the board. 4. bus device according to claim 1, is characterized in that, described bus converter also comprises the board card control line analysis module that is used to analyze described PCI/PCIe bus line to obtain board card control information, wherein, described The board control information includes independent interrupt signal information, card detection signal information, read and write control information, and board reset signal information. 5. bus device according to claim 4, it is characterized in that, described bus converter further comprises the backboard manager that is connected with described board control line analysis module communication, and described backplane manager comprises: An interrupt control unit for interrupting the communication connection of the board through the interrupt signal information obtained by the board control line analysis module; A card detection unit for identifying the board according to the card detection signal information obtained by the board control line analysis module; A read-write control unit for controlling the read-write operation and/or write operation of the board through the read-write control information acquired by the board control line analysis module; and A board reset unit for resetting the board through the board reset signal information acquired by the board control line analysis module. 6. The bus device according to any one of claims 1-5, wherein the bus converter is a bus converter based on FPGA or ASIC. 7. A bus device, characterized in that, comprises a CPU bus, an SPI bus, and is used to simulate the timing of the SPI device by the CPU bus to map the data flow conversion from the SPI bus transmission to the CPU bus converter for the bus; where, The board arranged on one side of the backplane communicates with the bus converter through the CPU bus; The bus converter is communicatively connected with the SPI device through the SPI bus. 8. The bus device according to claim 7, wherein the bus converter is a bus converter based on a hardware interface circuit. 9. A backplane system, characterized in that the backplane system comprises the bus device according to any one of claims 1-8. 10. The backplane system according to claim 9, wherein the backplane system further comprises a backplane and one or more boards arranged on one side of the backplane, wherein the board passes through the The bus device is in communication connection with the access master device, and the boards are in communication connection with each other through the bus device.

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