CN211238248U - Semiconductor package - Google Patents

Abstract

The utility model of the present disclosure relates to a semiconductor package. The semiconductor package includes: a substrate including a plurality of connection pads and a plurality of ground pads; an electronic component coupled to a mounting surface of the substrate and connected to at least one of the plurality of connection pads through at least one lead; an interposer disposed on a first surface of the electronic component facing away from the substrate and including an insulating surface and a ground surface disposed oppositely; wherein the insulating surface is insulatingly coupled to the first surface of the electronic component; and the ground surface is via the first surface The shield structure is connected to a plurality of ground pads. A semiconductor package having a shielding structure is provided.

Description

Semiconductor packaging

technical field

Embodiments of the present disclosure relate generally to the field of semiconductors, and more particularly to semiconductor packaging.

Background technique

Integrated circuits and other electronic devices can be packaged on semiconductor packages. Semiconductor packages can be integrated into products such as wireless communication devices or other products. In some cases, integrated circuits and/or electronic devices on a semiconductor package may interfere with each other or with other electronic components.

There is a need to provide a semiconductor package structure to improve the anti-interference capability of the semiconductor package.

Utility model content

According to embodiments of the present disclosure, semiconductor packages are provided to solve or partially solve the above-mentioned problems and other problems with existing semiconductor packages.

In a first aspect of the present disclosure, there is provided a semiconductor package comprising: a substrate including a plurality of connection pads and a plurality of ground pads; an electronic component coupled to a mounting surface of the substrate and through at least one a lead is connected to at least one of the plurality of connection pads; a first interposer is disposed on a first surface of the electronic component facing away from the substrate, and includes an insulating surface and a ground surface disposed oppositely; wherein the insulating surface is connected to the electronic component and the ground surface is connected to the plurality of ground pads via the first shield structure.

A first interposer including an insulating surface and a grounding surface is arranged on the surface of the electronic component, and the grounding surface is connected to a plurality of grounding pads through the first shielding structure, so that the first shielding structure is formed above the electronic component. In this way, the grounding surface of the first interposer on the top of the electronic component and the first shielding structure are grounded together, thereby forming a good shielding shell surrounding the electronic component to improve the electromagnetic shielding performance of the electronic component. This can provide good shielding performance for transmission devices used to transmit high-speed signals, high-speed differential signals, and radio frequency signals, and can ensure signal integrity.

In some embodiments, the first shield structure includes a plurality of first shield wires or first shield strips. Connecting each of the plurality of first shield wires or the first shield strips to the ground pad may form a ground shield, thereby shielding the energy of interfering signals from the outside to provide at least partially and/or fully the electronic component shielding effect.

In some embodiments, the plurality of ground pads are arranged corresponding to the plurality of connection pads, such that the first shield wire or first shield strip connected to each ground pad is connected to the lead wire connected to the corresponding connection pad Corresponding. Arranging the first shielding wire or the first shielding tape corresponding to the corresponding lead can easily ensure that the distance between the corresponding lead and the grounding wire or the grounding tape is consistent, so as to provide better shielding of electronic components, and provide better protection for electronic components. The signal transmitted by the component provides a continuous constant reference (ie, grounded shield wire or shield tape).

In some embodiments, the first interposer covers at least 80% of the area of the first surface of the electronic component. A certain space may be reserved for the first interposer to connect to the first shielding structure, so as to arrange the first shielding structure (eg, the first shielding wire or the first shielding tape) corresponding to the lead.

In some embodiments, further comprising: a second interposer between the electronic component and the substrate, and the electronic component is coupled to the mounting surface of the substrate through the second interposer, the second interposer including a plurality of shield pads; The second shield structure includes a plurality of second shield wires or second shield strips connected to one or more of the plurality of shield pads to at least partially surround the electronic component.

By using the second interposer, a second shielding structure is further formed on the periphery of the electronic component, which can further improve the anti-interference ability of the electronic component. This can provide good shielding performance for transmission devices used to transmit high-speed signals, high-speed differential signals, and radio frequency signals, and can ensure signal integrity.

In some embodiments, the first interposer is a silicon interposer. Thereby, the fabrication of the interposer can be conveniently realized during the semiconductor fabrication process.

Various embodiments of the present disclosure have been described above, and the foregoing descriptions are exemplary, not exhaustive, and not limiting of the disclosed embodiments. Numerous modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or improvement over the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

It should be understood that what is described in this Summary section is not intended to limit key or critical features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Description of drawings

The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent when taken in conjunction with the accompanying drawings and with reference to the following detailed description. In the drawings, the same or similar reference numbers refer to the same or similar elements, wherein:

1 shows a simplified cross-sectional schematic diagram of a semiconductor package according to an embodiment of the present disclosure;

2 shows a simplified schematic cross-sectional view of a semiconductor package according to an embodiment of the present disclosure;

FIG. 3 shows a top view of the semiconductor package of FIG. 2 according to an embodiment of the present disclosure; and

FIG. 4 shows a top view of the semiconductor package of FIG. 2 according to an embodiment of the present disclosure.

Detailed ways

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for the purpose of A more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes, and are not intended to limit the protection scope of the present disclosure.

As described above, there is currently a need to improve the anti-interference performance of semiconductor devices. In response to the above problems and other possible potential problems, embodiments of the present disclosure provide a semiconductor package. Embodiments of the present disclosure are specifically described below with reference to FIGS. 1 to 4 .

In a first aspect, the present disclosure provides a semiconductor package. FIG. 1 shows a schematic diagram of a semiconductor package according to an embodiment of the present disclosure. In general, the semiconductor package includes a substrate 10 , electronic components 20 , and a first interposer 30 .

The substrate 10 includes a plurality of connection pads 12 and a plurality of ground pads 14 . The connection pads 12 are pads for communication or electrical connection with the electronic component 20 . The ground pad 14 is a pad for grounding. In some embodiments, connection pads 12 and ground pads 14 may be one or more pads and/or interconnect traces, respectively.

In some embodiments, the substrate 10 may be an organic structure. Under other embodiments, the substrate 10 may be inorganic (eg, ceramic, etc.). Substrate 10 may have any suitable size and/or shape. For example, in an exemplary embodiment, the substrate 10 may be a rectangular panel, and the substrate 10 may be fabricated from any suitable material, including polymeric materials, fiberglass, plastics, composite materials, glass, ceramic materials, FR-5 materials, its combination, etc.

The electronic component 20 is coupled to the mounting surface of the substrate 10 , and the electronic component 20 is connected to at least one of the plurality of connection pads 12 through at least one lead 21 , thereby electrically and mechanically coupling the electronic component 20 to the substrate 10 .

In some embodiments, the electronic components include at least one integrated circuit chip, which may be electrically and mechanically coupled to the substrate 10 via any means, such as metal pillars, solder bumps, anisotropic conductive films (ACFs), Non-conductive film (NCF) and other known technologies.

The first interposer 30 is arranged on the first surface 23 of the electronic component 20 facing away from the substrate 10 (ie the top surface of the electronic component 20 shown in FIG. 1 ). The first interposer 30 includes an insulating surface 35 and a grounding surface 33 that are oppositely arranged. As shown in FIG. 1 , the grounding surface 33 is further away from the electronic component 20 than the insulating surface 35 .

In some embodiments, insulating surface 35 and ground surface 33 may be insulating and ground layers on first interposer 30 . Also, the insulating surface 35 is insulatingly coupled to the first surface 23 of the electronic component 20 , and the grounding surface 33 is connected to the plurality of grounding pads 14 via the first shielding structure 31 .

In some embodiments, ground surface 33 may be formed on first interposer 30 (eg, on a silicon interposer) by any suitable means. For example, conductive metal layers formed using physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, and the like.

In other embodiments, the ground surface 33 may be a metal layer, such as aluminum, silver, copper, etc., and/or alloys of aluminum, silver, copper, and the like. Ground surface 33 may be formed via sputtering, paste printing, squeegee printing, atomic layer deposition (ALD), or a variety of different physical vapor deposition (PVD) techniques.

In this way, the electronic component 20 can be sufficiently enclosed in the first shielding structure to improve the electromagnetic shielding performance of the electronic component. This can provide good shielding performance for transmission devices used to transmit high-speed signals, high-speed differential signals, and radio frequency signals, and can ensure signal integrity.

The electronic component 20 is insulatively coupled with the insulating surface 35 , and the ground surface 33 and the ground pad are connected through the first shield structure 31 . In this way, the grounding surface 33 of the first interposer 30 located on the top of the electronic component 20 and the first shielding structure 31 are grounded together, thereby forming a good shielding shell surrounding the electronic component 20, which can sufficiently shield external interference energy , and also shields the energy (eg, electric and/or magnetic fields) emitted from the electronic component 20 outward.

In some embodiments, the first interposer 30 is a silicon interposer. Fabrication of the first interposer can be conveniently accomplished during semiconductor fabrication. As previously mentioned, the silicon interposer includes the ground surface 33 .

In some embodiments, the first shielding structure 31 includes a plurality of first shielding wires or first shielding tapes. Thereby, the energy of external interfering signals can be shielded, so that a shielding effect is provided for the electronic component at least partially and/or completely.

In some embodiments, as shown in FIG. 1 , the plurality of ground pads 14 are disposed corresponding to the plurality of connection pads 12 . The first shield wire or first shield tape thus connected to each ground pad 14 corresponds to the lead 21 connected to the corresponding connection pad 12 .

In this way, it is convenient to ensure that the distance between the corresponding lead and the grounding wire or grounding strip is consistent, so as to provide better shielding of the electronic components, and provide a continuous and constant reference for the signals transmitted by the electronic components (ie, grounding). shielded wire or tape).

In some embodiments, the first interposer 30 covers at least 80% of the area of the first surface 23 of the electronic component 20 . Thus, a certain space can be reserved for the first interposer to connect to the first shielding structure, so as to arrange the first shielding structure (eg, the first shielding wire or the first shielding tape) corresponding to the lead. In some embodiments, the first interposer is caused to cover at least the area of the first surface 23 of the electronic component 20, eg, in the range 85%-90% (eg, 88%), or in the range 90%-98% (eg, 95%) ). This arrangement can not only ensure the shielding effect, but also simplify the manufacturing process.

In some embodiments, as shown in FIGS. 2-4 , the semiconductor package may further include a second interposer 40 and a second shielding structure 42 . FIG. 2 shows a side view of the semiconductor package including the second interposer 40 , FIG. 3 is a top view of the semiconductor package of FIG. 2 , and FIG. 4 shows a top view of the semiconductor package of FIG. 2 . In order to avoid confusion in the drawings, the ground pads 14 , the connection pads 12 , the leads 21 , and the first shielding structure 31 in FIGS. 2 to 3 are omitted in FIG. 4 , and only a schematic diagram of the second shielding structure 42 is shown. .

As shown in FIGS. 2 and 4 , the second interposer 40 is located between the electronic component 20 and the substrate 10 , and the electronic component 20 is coupled with the mounting surface of the substrate 10 through the second interposer 40 , the second interposer 40 includes A plurality of shield pads 41 . The second shielding structure 42 includes a plurality of second shielding wires or second shielding tapes, and the second shielding wires or the second shielding tapes are connected to one or more of the plurality of shielding pads 41, so that the electronic component 20 is shielded by the second Structure 42 is at least partially enclosed.

By using the second interposer, a second shielding structure is further formed on the periphery of the electronic component, which can further improve the anti-interference ability of the electronic component. This can provide good shielding performance for transmission devices used to transmit high-speed signals, high-speed differential signals, and radio frequency signals, and can ensure signal integrity.

In some embodiments, as shown in FIGS. 3 and 4 , the bottom surface of the second interposer 40 is coupled with the substrate 10 and the top surface 45 of the second interposer 40 is coupled with the electronic component 20 . A plurality of shielding pads 41 are arranged on the top surface 45 of the second interposer 40 . In some embodiments, the second interposer 40 is larger in area than the electronic component 20, eg, 1%-10% larger. In order to simplify the manufacturing process of the shielding pad 41 and facilitate the connection between the second shielding structure 42 and the shielding pad 41 .

In some embodiments, as shown in FIG. 4 , a second shield wire or second shield tape may be connected, for example, from shield pads 41 on one side of electronic component 20 to shield pads on the other side of electronic component 20 . 41. The second shielded wires or the second shielded tapes may be repeatedly connected with a predetermined density in a plurality of lanes. According to the requirements of the required shielding level, the density and connection method of the second shielding wire or the second shielding tape can be designed. For example, a plurality of second shield wires or second shield strips may be arranged as a mesh housing shield structure surrounding the electronic component 20 to provide local and/or global shielding.

It should be understood that any number of electronic components 10 may be provided in a semiconductor package. Electronic components 10 may include, but are not limited to, integrated circuits, active devices, passive devices, diodes, transistors, connectors, resistors, inductors, capacitors, microelectromechanical systems (MEMS), combinations thereof, and the like.

The shielding wires and/or shielding tapes herein may be pre-manufactured and then attached to the substrate 10 via pick and place techniques. The first shield wire and/or shield tape may be connected to the substrate 10 by its connection to the ground pad 14 (eg, comprising silver or copper). First Shielded Wire The shielded wire and/or the shielding tape may comprise gold, silver or copper, aluminum, and/or other suitable metals and combinations thereof. The second shield wire and/or shield tape may be connected to the second interposer 40 by its connection to the shield pad 41 (eg comprising silver or copper). The second shield wire and/or shield tape may comprise gold, silver or copper, aluminum, and/or other suitable metals and combinations thereof.

As an example, the diameter of the wire may be approximately in the range of about 6 microns to about 80 millimeters, with an exemplary diameter/radius being about 2 mm. The diameter of the tape may be approximately 15 microns to approximately 80 millimeters, with an exemplary diameter of approximately 2 mm. In some embodiments, when multiple electronic components 20 are present, not all of the electronic components are covered by the first shielding structure and the second shielding structure.

Various embodiments of the present disclosure have been described above, and the foregoing descriptions are exemplary, not exhaustive, and not limiting of the disclosed embodiments. Numerous modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or improvement over the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (6)

1. A semiconductor package, comprising:

a substrate (10) comprising a plurality of connection pads (12) and a plurality of ground pads (14);

an electronic component (20) coupled to a mounting surface of the substrate (10) and connected with at least one of the plurality of connection pads (12) through at least one lead (21);

a first interposer (30) arranged on a first surface (23) of the electronic component (20) facing away from the substrate (10) and comprising oppositely arranged insulating surfaces (35) and ground surfaces (33);

wherein the insulating surface (35) is insulatively coupled with the first surface (23) of the electronic component (20); and the ground surface (33) is connected with the plurality of ground pads (14) via a first shielding structure (31).

2. The semiconductor package according to claim 1, wherein the first shielding structure (31) comprises a plurality of first shielding lines or first shielding strips.

3. The semiconductor package according to claim 2, wherein the plurality of ground pads (14) are disposed in correspondence with the plurality of connection pads (12) such that the first shield line or first shield tape connected to each ground pad (14) corresponds to the lead (21) connected to the corresponding connection pad (12).

4. The semiconductor package of claim 1, wherein the first interposer (30) covers at least 80% of an area of the first surface (23) of the electronic component (20).

5. The semiconductor package of claim 1, further comprising:

a second interposer (40) located between the electronic component (20) and the substrate (10), and the electronic component (20) coupled with a mounting surface of the substrate (10) through the second interposer (40), the second interposer (40) including a plurality of shielding pads (41);

a second shielding structure (42) comprising a plurality of second shielding lines or second shielding strips connected with one or more of the plurality of shielding pads (41) to at least partially surround the electronic component (20).

6. The semiconductor package of claim 1, wherein the first interposer (30) is a silicon interposer.

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