CN102446870A - Encapsulation with electrostatic discharge and anti-electromagnetic interference - Google Patents

Abstract

The invention relates to a packaging part with electrostatic discharge and electromagnetic wave interference prevention, comprising: a carrier having electrically isolated first and second ground structures; a semiconductor element disposed on one surface of the carrier and electrically connected to the first ground structure; and a covering member covering the carrier and the semiconductor element and electrically connected to the second grounding structure. The invention makes the semiconductor element and the covering component respectively electrically connected with the first and the second grounding structures to respectively conduct and remove the charges of static electricity and electromagnetic waves, and prevents the semiconductor element from being damaged by the static electricity, thereby improving the yield and avoiding the occurrence of short circuit.

Description

Encapsulation with electrostatic discharge and anti-electromagnetic interference

technical field

The invention relates to a package, in particular to a package with electrostatic discharge and avoiding electromagnetic wave interference.

Background technique

With the rapid development of science and technology, various new products are constantly being introduced. In order to meet the needs of consumers for easy use and portability, all kinds of electronic products are now developing towards light, thin, short and small. Among them, semiconductor packages (Semiconductor Package) is a method of electrically connecting a semiconductor chip (chip) to a carrier of a packaging substrate, and then covering the semiconductor chip and the carrier with an encapsulant such as epoxy resin, so as to protect the semiconductor chip through the encapsulant and the carrier, and avoid external moisture or pollutants, and then cover the encapsulant with a metal shell covering member; or only cover the semiconductor chip and the carrier with a metal shell covering member, so as to Protect the semiconductor chip from damage by external influences (such as electrostatic discharge (ESD), etc.) by the covering member, and block internal and external electromagnetic interference (Electro-Magnetic Interference, EMI) and electromagnetic compatibility (Electromagnetic Compatibility) by the covering member. -Magnetic Compatibility, EMC).

The grounding system of the existing packaging component or system-level package (System in Package, SiP or System Integrated Package, SIP) is electrically connected to its own grounding structure through the external covering component, and then electrically connected to the system ground , thereby leading to the removal of external electromagnetic and electrostatic charges.

US Patent No. 5,166,772 proposes a semiconductor package with a mesh metal cover. As shown in Figures 1A and 1B, the semiconductor package disclosed in the US Patent No. 5,166,772 is connected with a meshed metal cover (Meshed Metallic Shield) 12 on the substrate 10, and the chip 11 is accommodated therein, and then the encapsulation compound 13 The mesh metal cover 12 and the chip 11 are completely covered. The semiconductor package is provided with the mesh metal cover 12 to shield the electromagnetic wave interference generated by the chip 11 or the electromagnetic wave interference generated by an external device, wherein the mesh metal cover 12 is electrically connected to the substrate 10 ground line 14.

Please refer to FIG. 2 , which is a schematic cross-sectional view of another conventional semiconductor package disclosed in US Pat. No. 6,187,613. As shown in the figure, on the substrate 10, a chip 11 is connected in a flip-chip (flip-chip) manner through a bump 15, and a metal foil 16 is adhered and covered on the substrate 10 and the chip 11, and the metal The encapsulant 13 is filled between the foil 16 and the substrate 10 . The semiconductor package shields the electromagnetic wave interference generated by the chip 11 or the electromagnetic wave interference generated by the external device through the metal foil 16 externally disposed on the encapsulant 13 .

However, the above-mentioned grounding methods of these packages are all electrically connected to the chip and the grounding lines of the active/passive components through the mesh metal cover or metal foil. When the semiconductor package is connected to the circuit board, if the net If the metal cover or metal foil has static electricity, the static electricity will be conducted along the path of the grounding line to the circuit board, chip and active/passive components. The chip and active/passive components are damaged.

Furthermore, the path connecting the meshed metal cover or metal foil to the system ground is too long, especially when the existing substrate 10 is less than six layers of lines, the grounding effect of the grounding line is reduced due to too many lines, making it difficult to release the charge. It may cause internal damage to the chip or other active/passive components.

Therefore, how to provide a package that can prevent internal chips or active/passive components from being damaged by static electricity, and has good electrostatic protection and has both functions of discharge and electromagnetic interference prevention is an important issue.

Contents of the invention

In view of the various deficiencies of the above-mentioned prior art, the present invention discloses a package with electrostatic protection and anti-electromagnetic interference, including: a carrier with opposite first and second surfaces, and the carrier has an electrically insulating first surface A grounding structure and a second grounding structure; at least one semiconductor element, placed on the first surface of the carrier, and electrically connected to the carrier and its first grounding structure; and a covering member, covered on the carrier on the first surface of the component to cover the semiconductor element, and the covering member is electrically connected to the second grounding structure.

In the above package, the second grounding structure is disposed around or at four corners of the carrier, a plurality of conductive elements are implanted on the second surface of the carrier, and each of the conductive elements is electrically connected to the first a ground structure and a second ground structure.

In a specific embodiment, the second ground structure directly passes through the conductive holes on the first and second surfaces, and the covering member is connected to the terminal of the conductive holes on the first surface.

In the above package with electrostatic discharge and anti-electromagnetic interference, the carrier also has an internal circuit.

According to the above-mentioned package, the semiconductor element is electrically connected to the internal circuit of the carrier and the first ground structure by wire bonding or flip-chip; the semiconductor element is selected from active components such as chips. component, passive component, or both; the passive component is a capacitor, resistor, or inductor.

According to the above package, a dummy pad is provided on the second surface, the second ground structure is electrically connected to the dummy pad, and the dummy pad is located around the carrier or outside the four corners.

Furthermore, in the above-mentioned package, an encapsulation material is further included to cover the semiconductor element, and the covering member is formed on the encapsulation material.

The package with electrostatic discharge and anti-electromagnetic interference further includes a package material covering the covering member.

It can be seen from the above that the carrier of the package with electrostatic protection and anti-electromagnetic interference of the present invention has electrically insulated first and second grounding structures, so that the semiconductor element and the covering member are electrically connected to the first grounding structure and the second grounding structure respectively. The second grounding structure, when the package is connected to the circuit board, if the covering member is charged with static electricity, the static charge can be directly conducted from the covering member to the circuit board through the second grounding structure instead of passing through the first grounding structure , so that the semiconductor element will not be protected from electrostatic discharge; and the covering member can block external electromagnetic waves and radio frequency interference, and discharge charges through the second grounding structure, so as to prevent the semiconductor element from being disturbed.

Description of drawings

1A and 1B are three-dimensional schematic diagrams of a semiconductor package disclosed in US Pat. No. 5,166,772;

2 is a schematic cross-sectional view of a semiconductor package disclosed in US Pat. No. 6,187,613;

3A, 3B and 3C are schematic cross-sectional views of different embodiments of the package with electrostatic discharge and anti-electromagnetic interference of the present invention;

4A and 4B are bottom views of the carrier of the package with electrostatic discharge and anti-electromagnetic interference of the present invention; and

Figure 4B' is a cross-sectional view of the package of the present invention with the carrier of Figure 4B.

Explanation of main component symbols

10 Substrates 11 Chips

12 Mesh metal cover 13 Encapsulation colloid

14 grounding line 15, 342 bumps

16 foils 20 packages

31 Carrier 310 Internal circuit

311 First grounding structure 312 Second grounding structure

31a first surface 31b second surface

32 Semiconductor components 33 Covering components

321 chip 322 passive components

341 wires 35 conductive components

331 contact part 312a conductive hole

313, 313' pad 36 circuit board

37a, 37b packaging material

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

Please refer to FIGS. 3A , 3B and 3C , which are schematic cross-sectional views of different embodiments of the package with electrostatic discharge and anti-electromagnetic interference of the present invention.

The present invention provides a package with electrostatic discharge and anti-electromagnetic interference, including: a carrier 31 , at least one semiconductor element 32 and a covering member 33 .

The carrier 31 includes a ball grid array substrate (BGA substrate) or a land grid array (LGA) substrate, the carrier 31 has opposite first surfaces 31a and second surfaces 31b, and the carrier 31 has an internal The circuit 310 (including signal and power parts), and the electrically insulated first ground structure 311 and the second ground structure 312 .

The semiconductor element 32 is selected from an active element such as a chip 321, a passive element 322, or both, and the passive element 322 is a capacitor, a resistor or an inductor; and the semiconductor element 32 is placed on the first surface of the carrier 31 31a, and electrically connect the internal circuit 310 of the carrier 31 with the wire 341 of the wire bonding method (as shown in FIG. A ground structure 311 .

The covering member 33 is disposed on the first surface 31 a of the carrier 31 to cover the semiconductor device 32 , and the covering member 33 is electrically connected to the second ground structure 312 .

The above package can be molded first to form a packaging material 37a covering the semiconductor element 32, and then a metal layer is sputtered on the packaging material 37a to form the covering member 33 (as shown in FIGS. 3A and 3B ). or, after covering the preformed covering member 33, perform a second molding to form the encapsulating material 37b covering the covering member 33 (as shown in FIG. 3C ).

In a preferred embodiment, the second grounding structure 312 directly penetrates the conductive holes 312a of the first surface 31a and the second surface 31b to shorten the electrical conduction path, and the covering member 33 is connected to the conductive hole 312a at the second Termination of a surface 31a.

According to the above package, the second surface 31b of the carrier is implanted with a plurality of conductive elements 35, the conductive elements 35 can be solder balls, solder pins or pads, and each of the conductive elements 35 is electrically connected to the internal circuit 310, the first ground structure 311 and the second ground structure 312; then the package is placed on the circuit board 36, so that the signal or power of the semiconductor element 32 can be conducted through the internal circuit 310 and the conductive element 35, and through the first ground The structure 311 is electrically connected to the ground structure (not shown) of the circuit board 36 , and the cover member 33 can be electrically connected to the circuit board 36 through the second ground structure 312 and the conductive element 35 .

According to the above, the conductive element 35 is directly disposed under the second ground structure 312, and the second ground structure 312 is vertically penetrated under the cover member 33, so as to shorten the conduction path and accelerate the discharge of charges. speed.

It can be known from the above that the semiconductor element 32 is electrically connected to the first ground structure 311 of the carrier 31, and the covering member 33 is electrically connected to the second ground structure 312. When the package is connected to the circuit board 36, if the cover When the component 33 or the package is charged with static electricity, the static charge can be discharged directly toward the circuit board 36 by the covering component 33 through the second ground structure 312 instead of going through the first ground structure 311, so that the semiconductor element 32 will not It will be affected by electrostatic charges, so that the semiconductor element 32 can be protected from damage.

Furthermore, the covering member 33 can block external electromagnetic interference (EMI) and electromagnetic compatibility (EMC), and discharge charges through the second ground structure 312, so as to prevent the semiconductor element 32 from being disturbed; and the semiconductor element 32 The internal electrostatic charge, electromagnetic wave, and radio frequency interference can be released by the first ground structure 311 alone, so as to protect the semiconductor element 32 .

Please refer to FIGS. 4A and 4B, which are bottom views of the carrier 31; as shown in FIG. The periphery or four corners of the carrier 31 provide the covering member 33 with its contact portion 331 extending to the periphery or corners (as shown in FIGS. 3A to 3C ) to electrically connect the second ground structure 312 and the pad 313 . Specifically, the second grounding structure 312 can be conductive holes 312 a disposed around or at four corners of the carrier 31 . Similarly, the conductive elements 35 connected to the second ground structure 312 are correspondingly disposed around the second surface 31 b of the carrier 31 or on the pads 313 at four corners.

In another embodiment shown in FIGS. 4B and 4B', the solder pads 313' to which the second ground structure 312 is connected on the second surface 31b can also be provided around the carrier 31 or outside the four corners. The position, for example, the inner row position, and the welding pad 313 ′ can be a dummy pad, as long as the second ground structure 312 and the first ground structure 311 electrically connected to it are independent and electrically insulated.

To sum up, in the present invention, the carrier with the electrostatic discharge and anti-electromagnetic interference package has an electrically isolated first ground structure and a second ground structure, so that the semiconductor element is electrically connected to the first ground of the carrier. structure, and the covering member is electrically connected to the second grounding structure. When the package is connected to the circuit board, if the covering member has static electricity, the electrostatic charge can be directly conducted from the covering member to the circuit board through the second grounding structure , without going through the first grounding structure, so that the semiconductor element will not be affected by electrostatic discharge and will not be damaged; and the covering member can block external electromagnetic waves and radio frequency interference, and pass through the second The ground structure discharges the charge to prevent the semiconductor element from being disturbed.

The above-mentioned embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be listed in the claims.

Claims (11)

1. A package with electrostatic discharge and anti-electromagnetic interference, characterized in that it comprises: The carrier has opposite first and second surfaces, and the carrier has a first ground structure and a second ground structure that are electrically insulated; at least one semiconductor device mounted on the first surface of the carrier and electrically connected to the carrier and its first ground structure; and A covering member is disposed on the first surface of the carrier to cover the semiconductor element, and the covering member is electrically connected to the second grounding structure. 2 . The package with electrostatic discharge and anti-electromagnetic interference according to claim 1 , wherein the second grounding structure is arranged around or at four corners of the carrier. 3 . 3. The package with electrostatic discharge and anti-electromagnetic interference according to claim 2, wherein a plurality of conductive elements are implanted on the second surface of the carrier, and each conductive element is electrically connected to the first a ground structure and a second ground structure. 4. The package with electrostatic discharge and anti-electromagnetic interference according to claim 2, wherein the second grounding structure directly passes through the conductive holes on the first and second surfaces, and the covering member is placed on the The conductive via terminates in the first surface. 5 . The package with electrostatic discharge and anti-electromagnetic interference according to claim 1 , wherein the carrier further has an internal circuit. 6 . 6. The package with electrostatic discharge and anti-electromagnetic interference according to claim 5, wherein the semiconductor element is electrically connected to the internal circuit of the carrier and the first grounding structure by wire bonding or flip-chip . 7 . The package with electrostatic discharge and anti-electromagnetic interference according to claim 1 , wherein the semiconductor element is selected from active elements, passive elements, or both. 8 . The package with electrostatic discharge and anti-electromagnetic interference according to claim 1 , wherein a dummy pad is provided on the second surface, and the second grounding structure is electrically connected to the dummy pad. 9 . The package with electrostatic discharge and anti-electromagnetic interference according to claim 8 , wherein the dummy pads are located around the carrier or outside the four corners. 10 . The package with electrostatic discharge and anti-electromagnetic interference according to claim 1 , further comprising an encapsulation material covering the semiconductor device, and the covering member is formed on the encapsulation material. 11 . 11 . The package with electrostatic discharge and anti-electromagnetic interference according to claim 1 , further comprising a package material covering the covering member. 12 .

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