CN210864615U - Power supply circuit of tablet computer - Google Patents

Abstract

The utility model relates to the technical field of computer motherboard power supplies, and discloses a power supply circuit for a tablet computer with timely level output state transition, comprising: a controller, which is arranged at a signal output end of an inverter; Connected to the signal output end of the inverter for receiving the level signal output by the inverter; the base of the first triode is connected to the signal output end of the controller; the base of the second triode is coupled to The signal output end of the inverter; the base of the third triode is coupled to the collector of the second triode, and the first signal input end of the dual-channel MOS tube is connected to the collector of the third triode; The second signal input end of the channel MOS tube is coupled to the collector of the first triode; when the screen changes from sleep to work, the inverter outputs a high level, and the high level is used to drive the dual-channel MOS tube to conduct, to light up the tablet screen.

Description

A power circuit of a tablet computer

technical field

The utility model relates to the technical field of computer motherboard power supply, in particular to a power supply circuit of a tablet computer.

Background technique

Switching power supply circuits are the most commonly used power supply circuits in electronic products. In the past, when the switching power supply provided working power for the tablet computer, it was easily affected by the fluctuating voltage of the power grid, resulting in an unstable output voltage.

Therefore, in the prior art, a switching power supply circuit with stable output voltage and little influence by fluctuating voltage is provided, which effectively solves the situation that the output voltage is unstable due to power grid fluctuations. However, when the switching power supply circuit in the prior art turns into normal operation from the sleep state of the tablet computer, the transition between the output levels of the tablet computer is delayed, resulting in a poor user experience.

Utility model content

The technical problem to be solved by the present invention is to provide a power supply circuit of a tablet computer with a timely level output state transition, aiming at the above-mentioned problem of delay in switching between levels when the above-mentioned tablet computer in the prior art is working state transition.

The technical solution adopted by the utility model to solve the technical problem is to construct a power supply circuit of a tablet computer, which has:

a controller, which is configured at the signal output end of the inverter, the signal input end of the controller is coupled to the signal output end of the inverter, and is used for receiving the level signal output by the inverter;

a first triode, the base of the first triode is connected to the signal output end of the controller;

a second triode, the base of the second triode is coupled to the signal output end of the inverter;

a third triode, the base of the third triode is coupled to the collector of the second triode,

A dual-channel MOS transistor, the first signal input end of the dual-channel MOS transistor is connected to the collector of the third triode;

The second signal input end of the dual-channel MOS transistor is coupled to the collector of the first triode;

When the screen changes from sleep to work, the inverter outputs a high level, and the high level is used to drive the dual-channel MOS transistor to be turned on, so as to light up the screen of the tablet computer.

In some embodiments, it further includes a first resistor and a second resistor, one end of the first resistor is connected to the signal output end of the controller, and the other end of the first resistor is coupled to the first third resistor the base of the pole tube,

One end of the second resistor is connected to the collector of the first triode;

The other end of the second resistor is coupled to the auxiliary power end of the controller.

In some embodiments, a fourth resistor and a fifth resistor are further included, one end of the fourth resistor is connected to the signal output end of the inverter, and the other end of the fourth resistor is coupled to the second resistor The base of the triode,

One end of the fifth resistor is respectively connected to the collector of the second triode and the base of the third triode;

The other end of the fifth resistor is coupled to the auxiliary power end of the controller.

In some embodiments, a second controller is further included, and the signal input terminal of the second controller is connected to a high level;

The signal output end of the second controller is coupled to the signal input end of the south bridge chip, and provides working power for the south bridge chip.

In some embodiments, a first capacitor, a second capacitor and a third capacitor are further included,

the first capacitor, the second capacitor and the third capacitor are connected in parallel,

One ends of the first capacitor, the second capacitor and the third capacitor are respectively connected to the signal input end of the second controller.

In some embodiments, a seventh resistor and an eighth resistor are also included,

The seventh resistor and the eighth resistor are connected in series,

One end of the seventh resistor is connected to the signal output end of the second controller,

One end of the eighth resistor and the other end of the seventh resistor are respectively connected to the adjustment end of the second controller.

The power supply circuit of the tablet computer according to the present invention includes a controller arranged at the signal output end of the inverter, and the signal input end of the controller is coupled to the signal output end of the inverter, which is used for receiving the inverter The level signal output by the device; the dual-channel MOS tube, the first signal input end of the dual-channel MOS tube is connected to the collector of the third triode; the second signal input end of the dual-channel MOS tube is coupled to the first triode The collector of the tube; when the screen changes from sleep to work, the inverter outputs a high level, and the high level is used to drive the dual-channel MOS tube to turn on to light up the screen of the tablet computer. Compared with the existing technology, the level signal (high level or low level) inputted by the inverter enables the level signal to be switched in time when the tablet computer screen is turned from sleep state to normal operation, which can effectively Improve user experience.

Description of drawings

The utility model will be further described below in conjunction with the accompanying drawings and embodiments, in the accompanying drawings:

1 is a partial drive circuit diagram of an embodiment of a power supply circuit for a tablet computer provided by the present invention;

FIG. 2 is a partial power circuit diagram of another embodiment of a power circuit of a tablet computer provided by the present invention.

Detailed ways

In order to have a clearer understanding of the technical features, purposes and effects of the present invention, the specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a partial drive circuit diagram of an embodiment of a power supply circuit for a tablet computer provided by the present invention; FIG. 2 is a partial power circuit diagram of another embodiment of the power supply circuit for a tablet computer provided by the present invention. As shown in FIGS. 1 and 2 , in the first embodiment of the power supply circuit of the tablet computer of the present invention, the power supply circuit of the tablet computer only needs to include an inverter A1, a controller U1, a first transistor Q1, a second The transistor Q2, the third transistor Q3 and the dual-channel MOS transistors (VT1, VT2).

Among them, the inverter A1 is the basic unit of the logic circuit. When its input terminal is high level (logic is 1), the output terminal is low level (logic is 0); when its input terminal is low level, the output The terminal is high, that is to say, the level state of the input terminal and the output terminal is always reversed.

The controller U1 is used for receiving the level signal input by the inverter A1, and has the functions of logical operation and controlling the output signal (current signal or voltage signal).

The controller U1 is provided with a "NOT" signal input terminal (corresponding to ATXPWROK#), a south bridge chip signal terminal (corresponding to SLP_S4#), a signal output terminal (corresponding to OUT) and an auxiliary power terminal (corresponding to PWR).

The triode acts as a switch.

Dual-channel MOS tubes (VT1, VT2) have the functions of signal conversion and control circuit on-off.

Specifically, the controller U1 is configured at the signal output terminal (corresponding to the F terminal) of the inverter A1.

A signal input terminal (corresponding to A terminal) of the controller U1 is coupled to the signal output terminal of the inverter A1, and another signal input terminal (corresponding to the B terminal) of the controller U1 is connected to the signal output terminal (SLP) of the South Bridge IC. -S4#) connection, which is used to receive the level signal (ie high level or low level) output by the inverter A1 and the south bridge chip IC, and output the level signal to the first transistor Q1.

The base of the first transistor Q1 is connected to the signal output terminal OUT of the controller U1, which is used for receiving the level signal output by the controller U1.

The base of the second transistor Q2 is coupled to the signal output terminal (corresponding to the ATXPWROK terminal) of the inverter A1, which is used for receiving the level signal output by the inverter A1.

The base of the third transistor Q3 is coupled to the collector of the second transistor Q2, and the collector of the third transistor Q3 is connected to the 12V voltage terminal.

The first signal input end (corresponding to pin 2) of the dual-channel MOS transistors (VT1, VT2) is connected to the collector of the third transistor Q3.

The second signal input terminals (corresponding to pin 4) of the dual-channel MOS transistors (VT1, VT2) are coupled to the collector of the first transistor Q1.

The emitters of the first transistor Q1, the second transistor Q2 and the third transistor Q3 are respectively connected to the common terminal.

When the screen of the tablet computer changes from sleep to work, the inverter A1 outputs a high level to drive the dual-channel MOS transistors (VT1, VT2) to turn on the high level to light up the screen of the tablet computer, so that the tablet computer can be timely change the working state.

Specifically, the ATXPWROK# signal in the circuit is converted from ATXPWROK through a "NOT" circuit (ie, inverter A1), that is, the level is opposite to that of ATXPWROK.

Its working principle is as follows: when the tablet computer is in sleep state, ATXPWROK is low level, and no +12V voltage is input to the collector of the third transistor Q3, and the first signal input of the dual-channel MOS transistors (VT1, VT2) is input. The terminal (corresponding to 2 feet) is low level, and the N-type channel in the dual-channel MOS tube (VT1, VT2) is cut off.

At this time, ATXPWROK# is high level, and SLP_S4# sent by the south bridge chip IC is high level, the controller U1 outputs a high level signal, controls the first transistor Q1 to conduct, and outputs a low level, dual-channel The P-type channel on the second signal input end (corresponding to pin 4) of the MOS tubes (VT1, VT2) is turned on. At this time, pins 5 and 6 of the dual-channel MOS transistor (VT2) output the 5V-USB converted from 5VSB.

That is, the screen can be lit by mouse or keyboard.

When ATXPWROK is at a high level during normal operation, the second transistor Q2 is turned on, the third transistor Q3 is turned off, and +12V is applied to the first signal input of the dual-channel MOS transistors (VT1, VT2) through the sixth resistor R6 On the terminal (corresponding to pin 2), that is, the control pin of the N-type channel of the dual-channel MOS tube is high, and the channel is turned on.

At this time, the VCC voltage is output as 5V-USB voltage from the pin 7 and pin 8 of the dual-channel MOS transistor (VT2) through the N-type MOS transistor. At the same time, if ATXPWROK is high and ATXPWROK# is low, the output of controller U1 is low, the first transistor Q1 is turned off, and a high-level control signal is output to the dual-channel MOS transistors (VT1, VT2 ) on the second signal input end (corresponding to pin 4), that is, the P-type channel of the dual-channel MOS tube is cut off. At this time, there is no current output to pins 5 and 6 of the dual-channel MOS tube (VT2), that is, 5VSB does not provide the voltage of 5V-USB.

In some embodiments, in order to improve the stability of the circuit, a first resistor R1 and a second resistor R2 can be set in the circuit. Among them, the first resistor R1 and the second resistor R2 have the function of limiting current.

Specifically, one end of the first resistor R1 is connected to the signal output end of the controller U1, the other end of the first resistor R1 is coupled to the base of the first transistor Q1, and the level signal output by the controller U1 is passed through the first The resistor R1 is input to the first transistor Q1 to control the first transistor Q1 to be turned on or off.

One end of the second resistor R2 is connected to the collector of the first transistor Q1, and the other end of the second resistor R2 is coupled to the auxiliary power terminal (corresponding to the 5VSB terminal) of the controller U1.

That is, when the controller U1 outputs a high level, the first transistor Q1 is turned on. At this time, the voltage output from the auxiliary power supply terminal (corresponding to the 5VSB terminal) of the controller U1 can be input to the dual-channel MOS transistor through the second resistor R2 (VT1, VT2) the second signal input terminal (corresponding to 4 feet).

In some embodiments, in order to improve the stability of the circuit, a fourth resistor R4 and a fifth resistor R5 may be set in the circuit. Specifically, one end of the fourth resistor R4 is connected to the signal output end (corresponding to the F end) of the inverter A1, and the other end of the fourth resistor R4 is coupled to the base of the second transistor Q2.

That is, the level signal inverted and output by the inverter A1 is input to the second transistor Q2 through the fourth resistor R4 to control the second transistor Q2 to be turned on or off.

Further, one end of the fifth resistor R5 is respectively connected to the collector of the second transistor Q2 and the base of the third transistor Q3, and the other end of the fifth resistor R5 is coupled to the auxiliary power terminal of the controller U1.

In some embodiments, in order to ensure the stability of the output voltage of the power supply circuit, a second controller U2 may be provided in the circuit, wherein the second controller U2 provides stable operating voltages for the south bridge IC and the north bridge IC.

Specifically, the signal input terminal (corresponding to Vin terminal) of the second controller U2 is connected to a high level (ie, the VCC terminal), and the signal output terminal (corresponding to the Vout terminal) of the second controller U2 is connected to the signal input of the South Bridge IC terminal to provide 1.5V working power for the South Bridge IC.

In some embodiments, a first capacitor C1 , a second capacitor C2 and a third capacitor C3 are further included, wherein the first capacitor C1 , the second capacitor C2 and the third capacitor C3 have the function of filtering.

Specifically, the first capacitor C1, the second capacitor C2 and the third capacitor C3 are connected in parallel, and one ends of the first capacitor C1, the second capacitor C2 and the third capacitor C3 are respectively connected to the signal input end of the second controller U2.

After the input voltage is filtered by the capacitor, the impurities of the power supply can be effectively reduced, thereby improving the quality of the output power supply.

In some embodiments, a seventh resistor R7 and an eighth resistor R8 are further included, the seventh resistor R7 and the eighth resistor R8 are connected in series, one end of the seventh resistor R7 is connected to the signal output end of the second controller U2, and the seventh resistor R7 is connected in series. The other end of the resistor R7 and one end of the eighth resistor R8 are respectively connected to the adjustment end of the second controller U2 (ie, the ADJ end).

Through the above circuit, the input VCC power supply is adjusted and converted into a voltage of 1.5V to meet the standard operating voltage of other components (extended AGP bus, I/O chip) in the internal circuit of the motherboard.

The embodiments of the present utility model have been described above in conjunction with the accompanying drawings, but the present utility model is not limited to the above-mentioned specific embodiments, which are merely illustrative rather than restrictive, and those of ordinary skill in the art Under the inspiration of the present utility model, personnel can make many forms without departing from the scope of protection of the present utility model and the claims, which all belong to the protection of the present utility model.

Claims (6)

1. A power supply circuit for a tablet computer, comprising: a controller, which is configured at the signal output end of the inverter, the signal input end of the controller is coupled to the signal output end of the inverter, and is used for receiving the level signal output by the inverter; a first triode, the base of the first triode is connected to the signal output end of the controller; a second triode, the base of the second triode is coupled to the signal output end of the inverter; a third triode, the base of the third triode is coupled to the collector of the second triode, A dual-channel MOS transistor, the first signal input end of the dual-channel MOS transistor is connected to the collector of the third triode; The second signal input end of the dual-channel MOS transistor is coupled to the collector of the first triode; When the screen changes from sleep to work, the inverter outputs a high level, and the high level is used to drive the dual-channel MOS transistor to be turned on, so as to light up the screen of the tablet computer. 2. The power supply circuit of the tablet computer according to claim 1, wherein, It also includes a first resistor and a second resistor, one end of the first resistor is connected to the signal output end of the controller, and the other end of the first resistor is coupled to the base of the first triode, One end of the second resistor is connected to the collector of the first triode; The other end of the second resistor is coupled to the auxiliary power end of the controller. 3. The power supply circuit of the tablet computer according to claim 2, wherein, Also includes a fourth resistor and a fifth resistor, one end of the fourth resistor is connected to the signal output end of the inverter, and the other end of the fourth resistor is coupled to the base of the second triode , One end of the fifth resistor is respectively connected to the collector of the second triode and the base of the third triode; The other end of the fifth resistor is coupled to the auxiliary power end of the controller. 4. The power supply circuit of the tablet computer according to claim 1, wherein, Also includes a second controller, the signal input end of the second controller is connected to a high level; The signal output end of the second controller is coupled to the signal input end of the south bridge chip, and provides working power for the south bridge chip. 5. The power supply circuit of the tablet computer according to claim 4, wherein, Also includes a first capacitor, a second capacitor and a third capacitor, the first capacitor, the second capacitor and the third capacitor are connected in parallel, One ends of the first capacitor, the second capacitor and the third capacitor are respectively connected to the signal input end of the second controller. 6. The power supply circuit of the tablet computer according to claim 5, characterized in that, Also includes a seventh resistor and an eighth resistor, The seventh resistor and the eighth resistor are connected in series, One end of the seventh resistor is connected to the signal output end of the second controller, One end of the eighth resistor and the other end of the seventh resistor are respectively connected to the adjustment end of the second controller.

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