CN204392640U - A kind of delay startup circuit - Google Patents

Abstract

This application discloses a kind of delay startup circuit, comprise RC charging circuit, NPN type triode, transistor and the first resistance, wherein: the base stage of described NPN type triode takes back collector electrode through described first resistance R1; Between the collector electrode that described RC charging circuit is connected to described NPN type triode and ground, and be connected with the control end of described transistor, for controlling the output end signal of described transistor; The base stage of NPN type triode described in the output termination of described transistor, the earth terminal ground connection of described transistor, solves the problem that output voltage is on the low side or delay time is not enough of the delay startup circuit occurred because component parameter value is different.

Description

A delay start circuit

technical field

The utility model relates to the technical field of power electronics, in particular to a delay start circuit.

Background technique

High-quality LED drivers generally adopt a two-stage circuit structure. The front-stage circuit realizes active power factor correction and provides functions such as DC bus voltage for the rear-stage circuit, and the latter-stage circuit realizes constant current source output, dimming, and various Functions such as data sampling and circuit protection, and the rear-stage circuit needs a certain delay to restart, and the pre-stage circuit completes the preparation work within this delay time, so as to avoid the confusion of the working sequence of the front-end circuit and the front-end circuit when starting up.

Figure 1 is a common delay start circuit, including resistor R1, capacitor C1, resistor R2 and NPN transistor Q1. Its working principle is: after power-on, the input voltage _Vin charges C1 through R1. After the electrode voltage is greater than the tube voltage drop between the base and the emitter, Q1 starts to conduct, and its emitter voltage (that is, the output voltage V _out ) rises slowly; after charging for a certain time T, the output voltage V _out is enough to start the subsequent circuit , the time T is the delay start time.

However, when this design is actually used, the output voltage V _out is often much lower than the input voltage V _in , which sometimes causes the downstream circuit to fail to work normally. The reason for this result is that the value of R1 is too large, so that the base current of Q1 is biased Small, the voltage drop between the collector and the emitter is too large, and if R1 is small, the value of C1 must be increased accordingly to meet the delay time requirements of the circuit, but a capacitor with a large value is used It is not advisable for LED drivers with a certain cost and layout space. Then, how to solve the problem of low output voltage V _out or insufficient delay time due to different parameter values of components has become an urgent need in this field. solved problem.

Utility model content

In view of this, the utility model provides a delay start circuit to solve the problem that the output voltage of the delay start circuit is low or the delay time is insufficient due to different parameter values of components.

A delayed start circuit, comprising an RC charging circuit, an NPN triode, a transistor and a first resistor, wherein:

The base of the NPN transistor is connected back to the collector through the first resistor R1;

The RC charging circuit is connected between the collector of the NPN triode and the ground, and connected to the control terminal of the transistor for controlling the output signal of the transistor;

The output terminal of the transistor is connected to the base of the NPN transistor, and the ground terminal of the transistor is grounded.

Wherein, the RC charging circuit includes a second resistor and a third resistor sequentially connected in series between the collector of the NPN transistor and the ground, and a capacitor connected in parallel at both ends of the third resistor.

Wherein, the transistor is a PNP transistor; the collector of the PNP transistor is grounded, its base is connected to the connection point between the second resistor and the third resistor, and its emitter is connected to the base of the NPN transistor. pole.

Wherein, the RC charging circuit includes a second resistor, a capacitor and a third resistor sequentially connected in series between the collector of the NPN transistor and the ground.

Wherein, the transistor is an NMOS transistor; the source of the NMOS transistor is grounded, its gate is connected to the connection point between the capacitor and the third resistor, and its drain is connected to the base of the NPN transistor.

It can be seen from the above technical scheme that the transistor in the utility model is turned on instantly when the delay start-up circuit is powered on, and the RC charging circuit is charged with the input voltage V _in , and the input voltage V _in controls the NPN type through the first resistor. The triode is turned on, and the NPN triode emitter starts to output voltage, that is, the output voltage V _out ; after a certain period of time, the RC charging circuit completes charging, the input voltage V _in controls the NPN triode to be saturated and turned on through the first resistor, and the output voltage V _out reaches stable value. The delay start time is determined by the parameter values of the components of the RC charging circuit, and the stable value of the output voltage V _out is determined by the value of the input voltage V _in . The voltage V _out is low or the delay time is insufficient.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are only some embodiments of the utility model, and those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is a schematic structural diagram of a delay start circuit disclosed in the prior art;

Fig. 2 is a schematic structural diagram of a delay start circuit disclosed in an embodiment of the present invention;

Fig. 3 is the specific circuit structure schematic diagram of the first kind of implementation mode of the delay starting circuit in Fig. 2;

FIG. 4 is a schematic diagram of a specific circuit structure of a second implementation of the delay start circuit in FIG. 2 .

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. example. Based on the embodiments of the present utility model, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of the present utility model.

Referring to Fig. 2, the embodiment of the utility model discloses a delayed start-up circuit to solve the problem that the post-stage circuit of the LED driver cannot work normally due to the influence of different component parameter values on the performance of the delayed start-up circuit, including RC charging circuit 10, NPN transistor Q1, transistor Q2 and first resistor R1, wherein:

The base of the NPN transistor Q1 is connected back to the collector through the first resistor R1; the collector of the NPN transistor Q1 is the input terminal of the delay start circuit to receive the input voltage V _in provided by the power supply circuit, and the NPN transistor Q1 The emitter pole is the output terminal of the delay start circuit, which is used to provide the output voltage V _out to the circuit modules that need delay restart, such as the LED driver rear-stage circuit;

The RC charging circuit 10 is connected between the collector of the NPN transistor Q1 and the ground, and is connected to the control terminal of the transistor Q2 for controlling the output signal of the transistor Q2;

The output terminal of the transistor Q2 is connected to the base of the NPN transistor Q1, and the ground terminal of the transistor Q2 is grounded.

The working principle of the delayed start circuit is: the transistor Q2 is turned on at the moment when the delay start circuit is powered on, and the RC charging circuit 10 is charged with the input voltage V _in , the NPN transistor Q1 is turned on, and the input voltage V _in passes through The first resistor R1 controls the emitter voltage of the NPN transistor Q1, that is, the output voltage V _out ; after a certain period of time, the RC charging circuit 10 completes charging, and the input voltage V _in flows into the base of the NPN transistor Q1 through the current of the first resistor R1 It is large enough to make the NPN transistor Q1 saturated and turned on. At this time, there is almost no voltage difference between the output voltage V _out and the input voltage V _in , which meets the requirements for the starting voltage of the rear-stage circuit of the LED driver. The final stable value of the output voltage V _out It is determined by the value of the input voltage _Vin . The delayed start time is determined by the parameter values of the components of the RC charging circuit 10. In order to meet the requirement for the delay time, two different implementations of the delayed start circuit are provided as follows:

1) The specific circuit structure of the first implementation of the delay start circuit in Fig. 2 is as shown in Fig. 3, wherein:

The RC charging circuit 10 includes a second resistor R2 and a third resistor R3 sequentially connected in series between the collector of the NPN transistor Q1 and the ground, and a capacitor C1 connected in parallel at both ends of the third resistor R3;

The transistor Q2 is a PNP transistor, and the ground terminal, control terminal and output terminal of the transistor Q2 correspond to the collector, base and emitter of the PNP transistor respectively; the collector of the PNP transistor Q2 is grounded, and its base is connected to the second resistor R2 The emitter of the connection point with the third resistor R3 is connected to the base of the NPN transistor Q1.

The working principle of the circuit shown in Figure 3 is:

At the moment when the delay start circuit is powered on, the voltage at both ends of the capacitor C1 is V _C1 = 0, and the third resistor R3 is short-circuited. At this time, the base voltage of the PNP transistor Q2 is V _B-2 = V _C1 = 0, and the PNP transistor Q2 is instantly conduction; the emitter voltage V _E-2 of the PNP transistor Q2 is equal to its base voltage V _B-2 plus the tube voltage drop between the emitter and the base of the PNP transistor Q2 (assuming that the tube voltage drop is 0.6V , the following is the same), that is, V _E-2 = V _B-2 +0.6 = V _C1 +0.6; as the input voltage V _in continues to charge the capacitor C1, the emitter voltage V _E-2 of the PNP transistor Q2 continues to rise , and finally the NPN transistor Q1 is turned on, at this time, the emitter of the NPN transistor Q1 starts to output voltage, that is, the voltage of the output voltage V _out rises from zero; it can be known from the characteristics of the transistor that the emitter voltage V of the NPN transistor Q1 _E-1 is equal to its base voltage V _B-1 minus the tube voltage drop between the base and emitter of NPN transistor Q1, that is, V _E-1 = V _B-1 -0.6, and because V _B-1 =V _E-2 , so VE _-1 =V _C1 , it can be seen that the emitter voltage V _E-1 of the NPN transistor Q1 is equal to the voltage across the capacitor C1 in the linear conduction stage, and changes with the voltage across the capacitor C1 After the capacitor C1 is charged for a certain period of time, the emitter voltage V _E-1 of the NPN transistor Q1 rises to the start-up voltage of the rear-stage circuit of the LED driver. At this time, the rear-stage circuit of the LED driver starts to work, and the delay ends. The time is the period from when the delay startup circuit is powered on to when the LED driver rear-stage circuit starts to work.

After the capacitor C1 is fully charged, the voltage across the capacitor C1 is stable at V _in *R3/(R2+R3). At this time, the parameter ratio of the second resistor R2 to the third resistor R3 is selected within a certain range to ensure that the capacitor C1 The deviation between the stabilized voltage value V _in *R3/(R2+R3) and the input voltage V _in is very small, and the base current of the input voltage V _in flowing into the NPN transistor Q1 through the first resistor R1 is very large, so that the NPN transistor Q1 Saturation conduction, there is almost no voltage difference between the output voltage V _out and the input voltage V _in , thus meeting the requirements of the starting voltage of the LED driving post-stage circuit.

It can be seen that this solution only needs to consider selecting the parameter ratio of the second resistor R2 and the third resistor R3 within a certain range to meet the requirements for the starting voltage of the LED driving post-stage circuit; the delay time is determined by the second resistor R2 and the second resistor R2. The values of the three resistors R3 and the capacitor C1 can be set arbitrarily, which can avoid the problem of insufficient delay time.

2) The specific circuit structure of the second implementation of the delay start circuit in Fig. 2 is as shown in Fig. 4, wherein:

The RC charging circuit 10 includes a second resistor R2, a capacitor C1 and a third resistor R3 sequentially connected in series between the collector of the NPN transistor Q1 and the ground;

The transistor Q2 is an NMOS transistor, and the ground terminal, control terminal and output terminal of the transistor Q2 respectively correspond to the source, gate and drain of the PMOS transistor; the source of the NMOS transistor Q2 is grounded, and its gate is connected to the capacitor C1 and the third resistor R3 Its drain is connected to the base of the NPN transistor Q1.

The working principle of the circuit shown in Figure 4 is:

When the delay start circuit is powered on, the voltage across the capacitor C1 is zero, and the gate voltage of the NMOS transistor Q2 is equal to V _in *R3/(R2+R3), so that the NMOS transistor Q2 is instantly saturated and turned on, and its drain output voltage is almost is zero, the NPN transistor Q1 is controlled to be closed, and the output voltage V _out =0;

As the input voltage V _in continues to charge the capacitor C1, the voltage across the capacitor C1 continues to rise until it reaches _Vin , and the voltage across the second resistor R2 and the third resistor R3 decreases continuously until it reaches zero, and the NMOS transistor Q2 follows It exits the saturated conduction, enters the linear conduction region, and then cuts off. Correspondingly, the drain voltage of the NMOS transistor Q2 rises slowly from zero to V _in ; during this process, the input voltage V _in flows into the NPN transistor through the first resistor R1 The current of Q1 changes from small to large, controlling the NPN transistor Q1 from cut-off to linear conduction, and finally entering a saturated conduction state, controlling the emitter voltage of the NPN transistor Q1 (that is, the output voltage V _out ) to rise slowly from zero to The start-up voltage required by the post-stage circuit of the LED driver, so far, the delay ends.

In this solution, since the NPN transistor Q1 is finally in a saturated conduction state, the voltage difference between the output voltage V _out and the input voltage V _in is very small, thus meeting the requirements for the starting voltage of the LED driving post-stage circuit. The final voltage across the capacitor C1 is V _in , and the NMOS transistor Q2 is finally in the cut-off state. The delay time is set arbitrarily by the values of the second resistor R2, the third resistor R3 and the capacitor C1, which can meet the delay time requirement.

In summary, the transistor in the utility model is turned on instantly when the delay startup circuit is powered on, and the RC charging circuit is charged with the input voltage V _in , and the input voltage V _in controls the NPN transistor to be turned on through the first resistor. The emitter of the NPN transistor starts to output voltage, that is, the output voltage V _out ; after a certain period of time, the RC charging circuit completes charging, the input voltage V _in controls the NPN transistor to be saturated and turned on through the first resistor, and the output voltage V _out reaches a stable value. The delay start time is determined by the parameter values of the components of the RC charging circuit, and the stable value of the output voltage V _out is determined by the value of the input voltage V _in . The voltage V _out is low or the delay time is insufficient.

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

The above description of the disclosed embodiments enables those skilled in the art to realize or use the utility model. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims (5)

1. A delay start circuit, characterized in that, comprises an RC charging circuit, an NPN transistor, a transistor and a first resistor, wherein: The base of the NPN transistor is connected back to the collector through the first resistor R1; The RC charging circuit is connected between the collector of the NPN triode and the ground, and connected to the control terminal of the transistor for controlling the output signal of the transistor; The output terminal of the transistor is connected to the base of the NPN transistor, and the ground terminal of the transistor is grounded. 2. The delay start circuit according to claim 1, wherein the RC charging circuit comprises a second resistor and a third resistor connected in series between the collector of the NPN transistor and the ground in sequence, and A capacitor connected in parallel to both ends of the third resistor. 3. The delay start circuit according to claim 2, wherein the transistor is a PNP transistor, wherein: the collector of the PNP transistor is grounded, and its base is connected to the second resistor and the The connection point of the third resistor, the emitter of which is connected to the base of the NPN transistor. 4. The delay start circuit according to claim 1, wherein the RC charging circuit comprises a second resistor, a capacitor and a third resistor connected in series between the collector of the NPN transistor and the ground in sequence . 5. The delay start circuit according to claim 4, wherein the transistor is an NMOS transistor, wherein: the source of the NMOS transistor is grounded, and its gate is connected to the connection between the capacitor and the third resistor. A connection point, the drain of which is connected to the base of the NPN transistor.