CN103076836B - Low-power voltage complementary metal oxide semiconductor (CMOS) constant-voltage source circuit - Google Patents

Abstract

The invention discloses a low power supply voltage CMOS constant voltage source circuit, which includes a first-stage start-up circuit, a first-stage current generating circuit that is independent of the power supply voltage but affected by temperature, a second-stage start-up circuit, and a second-stage start-up circuit that is connected to the power supply voltage The irrelevant but temperature-affected current generation circuit and the branch current subtraction circuit utilize the output current of the branch current subtraction circuit to realize an output voltage with a low temperature coefficient through a load resistance. The invention does not contain a bipolar device, and generates a reference voltage with a low temperature coefficient in the environment of a low power supply voltage.

Description

Low power supply voltage CMOS constant voltage source circuit

technical field

The invention relates to a constant voltage source circuit, in particular to a pure CMOS constant voltage source circuit working under low power supply voltage.

Background technique

In the application of CMOS circuits, a constant voltage source that is independent of the power supply voltage and temperature is often used. For example in the biasing circuits of some amplifiers, or in some comparators. In these cases, more accurate voltage values are often required. And we know that due to the influence of various factors such as technology, the voltage value often changes with the change of one or several factors, and the two more important factors are the influence of power supply voltage and temperature. At the same time, as the size of the CMOS process becomes smaller and smaller, the influence of various factors such as temperature is also increasing. Therefore, for circuits that require high-precision voltage values, it is very important to design a constant voltage source circuit that does not change with changes in power supply voltage and temperature.

The traditional constant voltage source circuit is mainly based on the voltage with a negative temperature coefficient generated between the base and emitter of the bipolar transistor and the difference between the base and emitter voltages of two bipolar transistors of different sizes. The generated voltages with positive temperature coefficients are summed, and through certain coefficient matching, voltages with zero temperature coefficients can be obtained. The constant voltage can generate a constant voltage on a fixed resistance and output it through some mirror images and matching with a certain temperature coefficient.

In commonly used high-precision constant voltage source circuits, the voltage between the base and emitter of bipolar transistors is required. We know that the voltage between the base and the emitter is generally around 0.7V. Therefore, this limits the minimum power supply voltage to be greater than 1V. As the size of the CMOS process becomes smaller and smaller, the provided power supply voltage becomes lower and lower. At the same time, due to the requirement on power consumption performance, it is also necessary to reduce the power supply voltage as much as possible. Therefore, when the power supply voltage is close to or lower than the voltage between the base and emitter of the bipolar transistor, the traditional high-precision constant current source circuit will completely lose its function.

Contents of the invention

Purpose of the invention: In view of the problems and deficiencies in the above-mentioned prior art, the purpose of the invention is to provide a low power supply voltage CMOS constant voltage source circuit, which is all composed of MOS tubes, works under a power supply voltage environment of 0.6V, and has low power Consumption of the function, while greatly reducing the area of the chip.

Technical solution: In order to achieve the purpose of the above invention, the technical solution adopted in the present invention is a low power supply voltage CMOS constant voltage source circuit, including a first-stage startup circuit, a first-stage current generation circuit that is independent of the power supply voltage but affected by temperature, The second-stage start-up circuit, the second-stage current generating circuit that is independent of the power supply voltage but affected by temperature, the branch current subtraction circuit, the branch current subtraction circuit is used to generate the first-stage current that is independent of the power supply voltage but influenced by temperature The affected current is subtracted from that of the second stage, which is independent of supply voltage but temperature dependent; where:

The first-stage start-up circuit includes a first P-type metal oxide transistor, a second P-type metal oxide transistor, and a first N-type metal oxide transistor;

The first stage current generation circuit which is independent of the power supply voltage but is affected by temperature includes a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor, a third NMOS transistor a transistor, a first resistor, and a seventh N-type metal oxide transistor;

The second-stage start-up circuit includes the fifth P-type metal oxide transistor, the sixth P-type metal oxide transistor, and the fourth N-type metal oxide transistor; the second-stage current generation circuit that is independent of the power supply voltage but affected by temperature includes the first Seventh PMOS transistor, eighth PMOS transistor, ninth PMOS transistor, second resistor, fifth NMOS transistor, sixth NMOS transistor;

The branch current subtraction circuit includes a tenth P-type metal oxide transistor, an eleventh P-type metal oxide transistor, a twelfth P-type metal oxide transistor, a thirteenth P-type metal oxide transistor, an eighth N-type a metal oxide transistor, a ninth N-type metal oxide transistor, a third resistor, and a fourth resistor;

in:

The source of the first P-type metal oxide transistor is connected to the power supply, the gate of the first P-type metal oxide transistor is connected to the source of the second P-type metal oxide transistor, and the drain of the first P-type metal oxide transistor It is connected to the drain of the first N-type metal oxide transistor; the gate of the first N-type metal oxide transistor is connected to its own drain, and is connected to the gate of the second P-type metal oxide transistor; the second P The substrate and the gate of the type metal oxide transistor are separated and connected to the power supply; the source of the first N type metal oxide transistor and the drain of the second P type metal oxide transistor are grounded; the third P type metal oxide transistor The source of the fourth P-type metal oxide transistor is connected to the power supply, the gate of the third P-type metal oxide transistor is connected to the gate of the fourth P-type metal oxide transistor and connected to the third P-type metal oxide transistor The drain of the material transistor is connected; the drain of the third P-type metal oxide transistor is connected with the drain of the second N-type metal oxide transistor and connected with the gate of the first P-type metal oxide transistor; the fourth P-type metal oxide transistor The drain of the oxide transistor is connected to the drain of the third N-type metal oxide transistor; the drain of the third N-type metal oxide transistor is connected to its own gate; the substrate and source of the second N-type metal oxide transistor The poles are separated and grounded; the source of the second N-type metal oxide transistor is connected to one section of the first resistor; the other section of the first resistor is connected to the source of the third N-type metal oxide transistor; the fifth P-type metal oxide transistor The source of the oxide transistor is connected to the power supply, the gate is connected to the source of the sixth P-type metal oxide transistor, and the drain is connected to the drain of the fourth P-type metal oxide transistor; the fourth N-type metal oxide transistor The gate is connected to its own drain and to the gate of the sixth P-type metal oxide transistor; the substrate and source of the sixth P-type metal oxide transistor are separated and connected to the power supply; the sixth P-type metal oxide transistor The drain of the transistor is grounded together with the source of the fourth N-type metal oxide transistor; the source of the seventh P-type metal oxide transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to the power supply; the seventh The gate of the P-type metal oxide transistor is connected to the gate of the eighth P-type metal oxide transistor and the gate of the ninth P-type metal oxide transistor and is connected to the drain of the eighth P-type metal oxide transistor and the fifth The gate of the P-type metal oxide transistor is connected; the source of the ninth P-type metal oxide transistor, the drain, the substrate and the source of the eighth P-type metal oxide transistor are all connected to the power supply; the fifth N-type metal oxide transistor The gate of the oxide transistor is connected to its own drain and to the gate of the sixth N-type metal oxide transistor; the source of the fifth N-type metal oxide transistor is connected to the source of the sixth N-type metal oxide transistor The gate of the tenth P-type metal oxide transistor is connected to the drain of the eighth P-type metal oxide transistor, the source of the tenth P-type metal oxide transistor is connected to the power supply, and the drain is connected to the eighth N The drain of the type metal oxide transistor; the gate of the eighth N type metal oxide transistor and the gate of the seventh N type metal oxide transistor and the third N type metal oxide transistor The drain of the object transistor is connected; the source of the eighth N-type metal oxide transistor and the source, substrate, and drain of the seventh N-type metal oxide transistor are all connected to the ground; the eleventh P-type metal oxide transistor The gate and drain of the twelfth P-type metal oxide crystal are connected to the gate of the thirteenth P-type metal oxide transistor; the source of the eleventh P-type metal oxide transistor is connected to the gate of the twelfth P-type metal oxide transistor. The source, drain, and substrate of the P-type metal oxide transistor and the source of the thirteenth P-type metal oxide transistor are connected to the power supply; the drain of the thirteenth P-type metal oxide transistor is connected to one end of the third resistor , the other end of the third resistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is grounded; the gate of the ninth N-type metal oxide transistor is connected between the third resistor and the fourth resistor, and the ninth N-type The source, substrate and drain of metal oxide transistors are all grounded.

The constant voltage source circuit of the present invention does not contain bipolar devices, and generates a constant voltage with high power supply voltage rejection ratio and low temperature coefficient in the environment of low power supply voltage.

Beneficial effects: compared with the prior art, the present invention has the following beneficial effects:

1. Work on low power supply voltage, such as a single solar panel. The constant voltage source circuit of the present invention can be used in reference circuits and bias circuits of various CMOS circuits where a constant voltage source is required. The constant voltage source circuit of the present invention can work under the low power supply voltage of 0.6V. Since the entire circuit is composed of MOS devices, the area of the chip is greatly reduced.

2. High current utilization efficiency and low power consumption. With the development of CMOS technology, the power supply voltage is getting smaller and smaller, which poses a challenge to the constant current source circuit containing bipolar transistor devices. The present invention does not contain bipolar devices, so the power supply voltage can be lower than the conduction voltage of bipolar triodes. Therefore, the power consumption of the whole circuit is very low. Moreover, in order to generate a constant voltage source with high precision, the present invention first designs a current that is independent of temperature and voltage and works at a power supply voltage of 0.6V. Since the temperature coefficient of the resistance is opposite to that of the generated current, a constant voltage with a lower temperature coefficient can be obtained through the combination of the current and the resistance.

Description of drawings

Fig. 1 is a circuit diagram of the present invention;

Fig. 2 is a waveform diagram of the variation of voltage with temperature coefficient in the present invention.

Detailed ways

Below in conjunction with accompanying drawing and specific embodiment, further illustrate the present invention, should be understood that these embodiments are only for illustrating the present invention and are not intended to limit the scope of the present invention, after having read the present invention, those skilled in the art will understand various aspects of the present invention Modifications in equivalent forms all fall within the scope defined by the appended claims of this application.

As shown in Figure 1, a low power supply voltage CMOS constant voltage source circuit of the present invention includes a first-stage start-up circuit, a first-stage current generation circuit that is independent of the power supply voltage but affected by temperature, a second-stage start-up circuit, and a second-stage start-up circuit. A secondary current generating circuit independent of supply voltage but temperature dependent and a branch current subtraction circuit for combining the first stage independent of supply voltage but temperature dependent current with the second stage Current subtraction independent of supply voltage but dependent on temperature; where:

The first-stage start-up circuit includes a first P-type metal oxide transistor P1, a second P-type metal oxide transistor P2, and a first N-type metal oxide transistor N1;

The first stage current generation circuit which has nothing to do with the power supply voltage but is affected by temperature includes a third P-type metal oxide transistor P3, a fourth P-type metal oxide transistor P4, a second N-type metal oxide transistor N2, a third N-type metal oxide transistor a metal oxide transistor N3, a first resistor R1, and a seventh N-type metal oxide transistor N7;

The second-stage startup circuit includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, and a fourth NMOS transistor N4;

The second-stage current generation circuit that is independent of the supply voltage but affected by temperature includes a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, and a second resistor R2 , the fifth N-type metal oxide transistor N5, the sixth N-type metal oxide transistor N6;

The branch current subtraction circuit includes a tenth P-type metal oxide transistor P10, an eleventh P-type metal oxide transistor P11, a twelfth P-type metal oxide transistor P12, a thirteenth P-type metal oxide transistor P13, An eighth NMOS transistor N8, a ninth NMOS transistor N9, a third resistor R3, and a fourth resistor R4;

in:

The source of the first P-type metal oxide transistor P1 is connected to the power supply, the gate of the first P-type metal oxide transistor P1 is connected to the source of the second P-type metal oxide transistor P2, and the first P-type metal oxide transistor P2 The drain of P1 is connected to the drain of the first N-type metal oxide transistor N1; the gate of the first N-type metal oxide transistor N1 is connected to its own drain, and is connected to the drain of the second P-type metal oxide transistor P2 The gate is connected; the substrate and the gate of the second P-type metal oxide transistor P2 are separated, and connected to the power supply in parallel; the source of the first N-type metal oxide transistor N1 and the drain of the second P-type metal oxide transistor P2 Grounding; the source of the third PMOS transistor P3 and the source of the fourth PMOS transistor P4 are connected to the power supply, the gate of the third PMOS transistor P3 and the fourth PMOS transistor The gate of the transistor P4 is connected to the drain of the third PMOS transistor P3; the drain of the third PMOS transistor P3 is connected to the drain of the second NMOS transistor N2 and connected to the drain of the third PMOS transistor P3. The gate of a P-type metal oxide transistor P1 is connected; the drain of the fourth P-type metal oxide transistor P4 is connected to the drain of the third N-type metal oxide transistor N3; the drain of the third N-type metal oxide transistor N3 The pole is connected to its own gate; the substrate and source of the second N-type metal oxide transistor N2 are separated and grounded; the source of the second N-type metal oxide transistor N2 is connected to one end of the first resistor R1; the first The other end of the resistor R1 is connected to the source of the third N-type metal oxide transistor N3 and grounded; the source of the fifth P-type metal oxide transistor P5 is connected to the power supply, and the gate is connected to the source of the sixth P-type metal oxide transistor P6 The source is connected, and the drain is connected to the drain of the fourth P-type metal oxide transistor P4; the gate of the fourth N-type metal oxide transistor N4 is connected to its own drain, and connected to the sixth P-type metal oxide transistor The gate of P6 is connected; the substrate and source of the sixth PMOS transistor P6 are separated and connected to the power supply; the drain of the sixth PMOS transistor P6 and the source of the fourth NMOS transistor N4 poles are grounded together; the source of the seventh P-type metal oxide transistor P7 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the power supply; the gate of the seventh P-type metal oxide transistor P7 is connected to the first The gate of the eighth PMOS transistor P8 and the gate of the ninth PMOS transistor P9 are connected to the drain of the eighth PMOS transistor P8 and the drain of the fifth PMOS transistor P5 The gate is connected; the source of the ninth P-type metal oxide transistor P9, the drain, the substrate and the source of the eighth P-type metal oxide transistor P8 are all connected to the power supply; the fifth N-type metal oxide transistor N5 The gate is connected to its own drain and connected to the gate of the sixth NMOS transistor N6; the source of the fifth NMOS transistor N5 is connected to the source of the sixth NMOS transistor N6 Connected and grounded; the tenth PMOS transistor P10 The gate is connected to the drain of the eighth P-type metal oxide transistor P8, the source of the tenth P-type metal oxide transistor P10 is connected to the power supply, and the drain is connected to the drain of the eighth N-type metal oxide transistor N8; the eighth The gate of the NMOS transistor N8 is connected to the gate of the seventh NMOS transistor N7 and the drain of the third NMOS transistor N3; the source of the eighth NMOS transistor N8 The source, substrate, and drain of the seventh N-type metal oxide transistor N7 are all connected to the ground; the gate and drain of the eleventh P-type metal oxide transistor P11, and the twelfth P-type metal oxide transistor The gate of P12 is connected to the gate of the thirteenth PMOS transistor P13; the source of the eleventh PMOS transistor P11, and the source and drain of the twelfth PMOS transistor P12 , the substrate, and the source of the thirteenth P-type metal oxide transistor P13 are connected to the power supply; the drain of the thirteenth P-type metal oxide transistor P13 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to One end of the fourth resistor R4 is connected, and the other end of the fourth resistor R4 is grounded; the gate of the ninth N-type metal oxide transistor N9 is connected between the third resistor R3 and the fourth resistor R4, and the ninth N-type metal oxide transistor N9 The source, substrate and drain of transistor N9 are all grounded.

The above-mentioned high-precision constant voltage source circuit is all composed of CMOS devices. Since there is no bipolar transistor device, the power supply voltage can be lower than the conduction voltage of the bipolar transistor, so the entire constant current source circuit can work at a low power supply voltage of 0.6V and has very low power consumption. Moreover, since the size of the bipolar triode device is very large, the present invention greatly reduces the area of the chip. The main idea of the present invention is to use the two currents with the same temperature coefficient generated by the first-stage current generation circuit that has nothing to do with the power supply voltage but is affected by temperature and the second-stage current generation circuit that has nothing to do with the power supply voltage but is affected by temperature, A current with a low temperature coefficient can be obtained by the branch current subtraction circuit. At the same time, the temperature coefficient of the resistance in the process is opposite to that of the generated current, so the combination of current and resistance can be used to obtain a constant voltage with a lower temperature coefficient.

The first stage starting circuit is composed of a first P-type metal oxide transistor, a second P-type metal oxide transistor and a first N-type metal oxide transistor. When the current generating circuit of the first stage which has nothing to do with the power supply voltage but is affected by temperature is in the inactive state, the drain voltage of the third PMOS transistor P3 is very high, because the third PMOS transistor P3 The drain is connected to the source of the second PMOS transistor P2, so the source of the second PMOS transistor P2 is also at a high potential. At this time, the second PMOS transistor P2 is turned on, and a large amount of current flows through the second PMOS transistor P2 after it is turned on, which can reduce the drain voltage of the third PMOS transistor P3, Play the function of starting the circuit. In the case of a very small process size, the threshold voltage of the MOS transistor is very large. In order to better achieve the purpose of starting the subsequent circuit, the substrate of the second PMOS transistor P2 is connected to the power source in the circuit. The threshold voltage is reduced by utilizing the substrate bias effect existing in the MOS transistor itself. In this way, for the same drain and source voltage difference, the second PMOS transistor P2 can pass a larger current, thereby reducing the drain voltage of the third PMOS transistor P3 to a greater extent, and starting Better results. When the circuit is in the on state, the second PMOS transistor P2 should be in the off state to avoid its influence on the subsequent first stage current generation circuit which is independent of the power supply voltage but is affected by temperature. When the circuit works normally, since the drain voltage of the third PMOS transistor P3 is relatively high, to make the second PMOS transistor P2 in the cut-off state, the second PMOS transistor P2 should be turned off. The gate voltage rises. The gate of the second PMOS transistor P2 is connected to the drain of the first NMOS transistor N1, so the drain voltage of the first NMOS transistor N1 can be raised correspondingly The gate voltage of the second PMOS transistor P2. Therefore, in the first-stage start-up circuit, the width-to-length ratio of the first P-type metal oxide transistor P1 is set larger, and the first N-type metal-oxide transistor is set to an inverted width-to-length ratio, that is, the first N The width of the type metal oxide transistor is smaller than the channel length. In this way, when the circuit works normally, the second PMOS transistor P2 can be turned off. At the same time, the setting of the first PMOS transistor P1 and the first NMOS transistor N1 can also greatly reduce the current flowing through the first stage start-up circuit when the circuit is in normal operation, thereby further reducing the power of the entire circuit. consumption. The principle of the second-level start-up circuit is the same as that of the first-level start-up circuit.

In order to obtain the current value which has nothing to do with the power supply voltage, we adopt the first-stage current generation circuit which is independent of the power supply voltage but influenced by temperature. In this circuit, if the first resistor R1 is removed, the current flowing through the third PMOS transistor P3 is obtained by mirroring the current of the fourth PMOS transistor P4; The current of the transistor N3 is obtained by mirroring the current of the second NMOS transistor N2. Therefore, it can be seen that the current flowing through the whole branch has nothing to do with the power supply voltage. But at this time the current in the circuit can be any value. As long as the circuit has an original current, the current can flow in both branches by mirroring back and forth. In order to get the current value of the specific size required. We add a first resistor R1 to the source terminal of the first NMOS transistor N1. By setting the width-to-length ratio of each MOS device and the size of the first resistor R1, we can obtain a desired specific current value. The second level of supply voltage independent but temperature dependent current generating circuit uses the same principle as the first level of supply voltage independent but temperature dependent current generating circuit. In order to obtain a more stable waveform, the seventh N-type metal oxide transistor N7 and the fourth P-type metal oxide transistor P4 are used as the first-stage current generation circuit independent of the power supply voltage but affected by temperature and the second-stage and The filter device of the power supply voltage independent but temperature-affected current generating circuit to filter out the first stage current generating circuit independent of power supply voltage but temperature-affected and the second stage current generating circuit independent of power supply voltage but temperature-affected The clutter current contained in the current.

Using the first-stage current generation circuit that is independent of the power supply voltage but affected by temperature, we can get a specific current value that has nothing to do with the power supply voltage, but the current value is still a function of process and temperature. In order to obtain a high-precision constant voltage that has nothing to do with process and temperature, the invention uses the subtraction of two branch currents that have nothing to do with the power supply voltage but have the same process and temperature coefficient to offset the influence of process and temperature on the constant voltage value . In the circuit diagram of the invention, the eighth N-type metal oxide transistor N8 is used to mirror the current generation circuit of the first stage that has nothing to do with the power supply voltage but is affected by the temperature. circuit current; use the tenth P-type metal oxide transistor P10 to mirror the branch current that is independent of the power supply voltage but is a function of process and temperature generated in the second-stage current generation circuit that has nothing to do with the power supply voltage but is affected by temperature; The tenth P-type metal oxide transistor P10, the eleventh P-type metal oxide transistor P11, the twelfth P-type metal oxide transistor P12, the thirteenth P-type metal oxide transistor P13, the eighth N-type metal oxide transistor transistor N8, the ninth N-type metal oxide transistor N9, the third resistor R3, and the branch current subtraction circuit composed of the fourth resistor R4, since the eighth N-type metal oxide transistor N8 and the tenth P The current of the type metal oxide transistor P10 has the same coefficient relationship with temperature and process, so through the matching of a certain coefficient, the subtraction of the two branch currents can obtain a high voltage that is not related to the power supply voltage, but also has nothing to do with temperature and process. precision constant voltage. It can be seen from the circuit diagram that the current flowing through the eleventh PMOS transistor P11 is the current independent of the power supply voltage and temperature obtained by subtracting the two branch currents through coefficient matching.

The current flowing through the thirteenth PMOS transistor P13 is obtained by mirroring the current of the eleventh PMOS transistor P11. The coefficient of the fourth resistor R4 and temperature and process and the coefficient of current and temperature and process are opposite, so the Vout point between the third resistor and the fourth resistor can be obtained by matching the magnitude and value of the resistance and the current. Higher precision Voltage value. The twelfth PMOS transistor P12 and the ninth NMOS transistor N9 also function as filters.

The influence of the high-precision constant voltage source and the temperature coefficient produced by the present invention will be illustrated below through simulation and comparison.

use The simulation software performs scanning analysis of the temperature coefficient of the high-precision constant voltage source. The analysis results are shown in Figure 2. It can be seen from Figure 2 that the output reference voltage is in the range from -20 degrees to 80 degrees, which reflects the first-order temperature compensation characteristics. In the entire temperature range, the variation range of the output voltage is controlled within 1.5mV. Can meet most application requirements.

Claims (1)

1. a low supply voltage CMOS constant voltage source circuit, comprise first order start-up circuit, the first order and supply voltage have nothing to do but the current generating circuit of temperature influence, second level start-up circuit, the second level and supply voltage have nothing to do but the current generating circuit of temperature influence and branch current subtraction circuit, and described branch current subtraction circuit is used for the first order and supply voltage to have nothing to do but the electric current of temperature influence and the second level and supply voltage have nothing to do but the current subtraction of temperature influence; Wherein:

First order start-up circuit comprises a P type MOS transistor (P1), the 2nd P type MOS transistor (P2), the first N-type MOS transistor (N1);

The first order and supply voltage have nothing to do but the current generating circuit of temperature influence comprises the 3rd P type MOS transistor (P3), 4th P type MOS transistor (P4), second N-type MOS transistor (N2), 3rd N-type MOS transistor (N3), first resistance (R1), the 7th N-type MOS transistor (N7);

Second level start-up circuit comprises the 5th P type MOS transistor (P5), the 6th P type MOS transistor (P6), the 4th N-type MOS transistor (N4);

The second level and supply voltage have nothing to do but the current generating circuit of temperature influence comprises the 7th P type MOS transistor (P7), 8th P type MOS transistor (P8), 9th P type MOS transistor (P9), second resistance (R2), 5th N-type MOS transistor (N5), the 6th N-type MOS transistor (N6);

Branch current subtraction circuit comprises the tenth P type MOS transistor (P10), 11 P type MOS transistor (P11), 12 P type MOS transistor (P12), 13 P type MOS transistor (P13), 8th N-type MOS transistor (N8), 9th N-type MOS transistor (N9), the 3rd resistance (R3), the 4th resistance (R4);

Wherein:

The source electrode of the one P type MOS transistor (P1) connects power supply, the grid of the one P type MOS transistor (P1) is connected with the source electrode of the 2nd P type MOS transistor (P2), and the drain electrode of a P type MOS transistor (P1) is connected with the drain electrode of the first N-type MOS transistor (N1); The grid of the first N-type MOS transistor (N1) is connected with the drain electrode of self, and is connected with the grid of the 2nd P type MOS transistor (P2); The substrate of the 2nd P type MOS transistor (P2) and source electrode separately, and connect power supply; The source electrode of the first N-type MOS transistor (N1) and the grounded drain of the 2nd P type MOS transistor (P2); The source electrode of the 3rd P type MOS transistor (P3) and the source electrode of the 4th P type MOS transistor (P4) connect power supply, and the grid of the 3rd P type MOS transistor (P3) is connected with the grid of the 4th P type MOS transistor (P4) and is connected with the drain electrode of the 3rd P type MOS transistor (P3); The drain electrode of the 3rd P type MOS transistor (P3) is connected with the second N-type MOS transistor (N2) drain electrode and is connected with the grid of a P type MOS transistor (P1); The drain electrode of the 4th P type MOS transistor (P4) is connected with the drain electrode of the 3rd N-type MOS transistor (N3); 3rd N-type MOS transistor (N3) drain electrode is connected with the grid of itself, and the grid of the second N-type MOS transistor (N2) is connected with the grid of the 3rd N-type MOS transistor (N3); The substrate of the second N-type MOS transistor (N2) and source electrode separate and ground connection; The source electrode of the second N-type MOS transistor (N2) is connected with one end of the first resistance (R1); The other end of the first resistance (R1) is connected with the source electrode of the 3rd N-type MOS transistor (N3) and ground connection; The source electrode of the 5th P type MOS transistor (P5) connects power supply, and grid is connected with the source electrode of the 6th P type MOS transistor (P6), and drain electrode is connected with the drain electrode of the 4th N-type MOS transistor (N4); The grid of the 4th N-type MOS transistor (N4) is connected with the drain electrode of itself, and is connected with the grid of the 6th P type MOS transistor (P6); Substrate and the source electrode of the 6th P type MOS transistor (P6) separate and connect power supply; The drain electrode of the 6th P type MOS transistor (P6) and the source electrode together ground connection of the 4th N-type MOS transistor (N4); The source electrode of the 7th P type MOS transistor (P7) is connected with one end of the second resistance (R2), and the other end of the second resistance (R2) is connected with power supply; The grid of the 7th P type MOS transistor (P7) is connected with the grid of the grid of the 8th P type MOS transistor (P8) and the 9th P type MOS transistor (P9) and is connected with the drain electrode of the 8th P type MOS transistor (P8) and the grid of the 5th P type MOS transistor (P5); The source electrode of the 9th P type MOS transistor (P9), drain electrode, the source electrode of substrate and the 8th P type MOS transistor (P8) is all connected with power supply, and the drain electrode of the 7th P type MOS transistor (P7) is connected with the drain electrode of the 5th N-type MOS transistor (N5); The grid of the 5th N-type MOS transistor (N5) is connected with the drain electrode of itself, and is connected with the grid of the 6th N-type MOS transistor (N6); The source electrode of the 5th N-type MOS transistor (N5) is connected with the source electrode of the 6th N-type MOS transistor (N6) and ground connection, and the drain electrode of the 6th N-type MOS transistor (N6) is connected with the drain electrode of the 8th P type MOS transistor (P8); The grid of the tenth P type MOS transistor (P10) is connected with the drain electrode of the 8th P type MOS transistor (P8), the source electrode of the tenth P type MOS transistor (P10) connects power supply, and drain electrode connects the drain electrode of the 8th N-type MOS transistor (N8); The grid of the 8th N-type MOS transistor (N8) is connected with the drain electrode of the grid of the 7th N-type MOS transistor (N7) and the 3rd N-type MOS transistor (N3); The source electrode of the 8th N-type MOS transistor (N8) is all connected with ground with the source electrode of the 7th N-type MOS transistor (N7), substrate, drain electrode; The grid of the 11 P type MOS transistor (P11), drain electrode, the grid of the 12 P type MOS transistor (P12), the grid of the 13 P type MOS transistor (P13) and the drain electrode of the tenth P type MOS transistor (P10) are connected; The source electrode of the 11 P type MOS transistor (P11), the source electrode of the source electrode of the 12 P type MOS transistor (P12), drain electrode, substrate and the 13 P type MOS transistor (P13) is connected with power supply; The drain electrode of the 13 P type MOS transistor (P13) is connected with the 3rd resistance (R3) one end, and the other end of the 3rd resistance (R3) is connected with one end of the 4th resistance (R4), the other end ground connection of the 4th resistance (R4); The grid of the 9th N-type MOS transistor (N9) is connected to the centre of the 3rd resistance (R3) and the 4th resistance (R4), source electrode, the substrate of the 9th N-type MOS transistor (N9) and all ground connection that drains.