CN103760943B - A kind of slew rate enhancing circuit being applied to LDO - Google Patents

Abstract

The invention discloses a slew rate enhancement circuit applied to LDO, the slew rate enhancement circuit comprises: PMOS transistors M ₀ , M ₂ , M ₄ , M ₆ , M ₈ , NMOS transistors M ₁ , M ₃ , M ₅ , M ₇ , M ₉ , bias current source I ₀ and capacitor C _f . The LDO integrated with the slew rate enhancement circuit can quickly detect the change of the output terminal voltage and perform transient adjustment on the gate of the power regulator when the load of the LDO jumps without significantly increasing the static power consumption. , greatly increasing the voltage slew rate of the gate of the power adjustment tube, thereby improving the transient response of the LDO circuit.

Description

A Slew Rate Enhancement Circuit Applied to LDO

technical field

The invention relates to the technical field of power management, in particular to a slew rate enhancement circuit applied to an LDO.

Background technique

Portable devices such as smartphones, personal digital assistants, and handheld devices often require different levels to power different modules. LDO has the advantages of low cost, low output noise, simple circuit structure, and small chip area, and has become an important circuit in power management chips. The essence of LDO is to use the stable voltage generated by the bandgap reference and the negative feedback control loop to obtain an output voltage that basically does not change with the environment. LDO can convert the decaying battery voltage into a stable and accurate voltage with low noise to meet the needs of noise-sensitive analog modules and radio frequency modules in portable equipment.

The traditional LDO circuit is shown in Figure 1, V _out will produce a spike when the load changes transiently, and it takes a certain amount of time for V _out to recover and stabilize. To obtain a fast load transient response, a large quiescent current is required to increase the power consumption. Adjust the charging and discharging speed of the tube grid. However, in portable applications, it is necessary to extend the service life of the battery as much as possible, and the traditional LDO circuit structure cannot take into account both low quiescent current and fast load transient response.

Therefore, in order to obtain fast transient response without significantly increasing the quiescent current, it is necessary to design a slew rate enhancement circuit to improve its transient response.

Contents of the invention

The object of the present invention is to provide a slew rate enhancement circuit applied to LDO in order to remedy the defects of the prior art.

The present invention is achieved through the following technical solutions:

A slew rate enhancement circuit applied to LDO, including PMOS transistors M _{0 ,} M ₂ , M ₄ , M ₆ , M ₈ , NMOS transistors M ₁ , M ₃ , M ₅ , M ₇ , M ₉ and capacitor C _f ; One end of the capacitor C _f is the input end of the slew rate enhancement circuit, and the other end is respectively connected to the grid of the PMOS transistor _M2 , the drain, the grid of the PMOS transistor _M4 , the grid of the PMOS transistor _M6 and the NMOS _The drain connection of tube M3;

_The source of the PMOS transistor _M2 is _respectively connected to the source of the PMOS transistor M0, the source of the PMOS transistor M4, the source of the PMOS transistor _M6 , and the source of the PMOS transistor _M8 , and is connected to the external input power supply V _IN , _The drain of the PMOS transistor _M2 is connected to the drain of the NMOS transistor M3, and the gate of the PMOS transistor _M2 is connected to the gate of the PMOS transistor M4 _;

_The drain of the PMOS transistor M4 is connected to the drain of the NMOS transistor _M5 and the gate of the NMOS transistor _{M9 ;} the gate of the NMOS transistor M5 is respectively connected to the gate and drain _of the NMOS transistor M1 and the gate _of the NMOS transistor M3. Grid, the grid of NMOS transistor _M7 ;

_The drain of the NMOS transistor M1 is connected to the drain _of the PMOS transistor M0, the source _of the NMOS transistor M1 is connected to the source of the NMOS transistor M3, the source of the NMOS transistor _M5 , the source of the NMOS transistor _M7 and the _NMOS transistor _M9 The source level of the connected and grounded;

The gate of the NMOS transistor M3 is connected to the gate of the NMOS transistor _M5 , the gate _of the NMOS transistor M1, and the gate _of the NMOS transistor _M7 . The source _of the NMOS transistor M3 is connected to the source _of the NMOS transistor M1, the NMOS The source level of the tube _M5 , the source level of the NMOS tube _M7 and the source level of the NMOS tube _M9 are connected and grounded;

_The drain of the NMOS transistor _M5 is connected to the drain of the PMOS transistor M4 and the gate of the NMOS transistor _M9 , and the source of the NMOS transistor _M5 is connected to the source _of the NMOS transistor M1, the source _of the NMOS transistor M3, and the NMOS transistor M9. The source of M ₇ is connected to the source of NMOS transistor M ₉ and grounded;

_The gate of the PMOS transistor _M6 is connected to the gates of the PMOS transistor _M2 and the PMOS transistor M4, the drain of the PMOS transistor _M6 is connected to the drain of the NMOS transistor _M7 and the gate of the PMOS transistor _M8 , and the PMOS transistor M ₆ The source stage is connected to the sources of PMOS transistor M ₀ , PMOS transistor M ₂ , PMOS transistor M ₄ , and PMOS transistor M ₈ , and is connected to an external input power supply V _IN ;

_The gate of the NMOS transistor _M7 is connected to the gate _of the NMOS transistor M1, the gate _of the NMOS transistor M3, and the gate of the NMOS transistor _M5 , and the drain of the NMOS transistor M7 is connected to the drain of the PMOS transistor _M6 and the PMOS _The gate of the transistor M8 is connected, the source of the NMOS transistor _M7 is connected to the source _of the NMOS transistor M1, the source _of the NMOS transistor M3, the source of the NMOS transistor _M5 , and the source of the NMOS transistor _M9 and grounded ;

_The gate of the PMOS transistor M8 is connected to the drains of the PMOS transistor _M6 and the NMOS transistor _M7 , the drain of the PMOS transistor _M8 is connected to the drain of the NMOS transistor _M9 , and the source of the PMOS transistor _M8 is connected to the PMOS transistor M _{0. The} sources of the PMOS transistor _M2 , the PMOS transistor M4 and the PMOS transistor _M6 are connected, and connected to the external input power supply V _IN ;

_The gate of the NMOS transistor _M9 is connected to the drain of the PMOS transistor M4 and the drain of the NMOS transistor _M5 , the source of the NMOS transistor _M9 is connected to the source _of the NMOS transistor M1, the source _of the NMOS transistor M3, the NMOS _The source of the tube _M5 is connected to the source of the NMOS tube M7 and grounded, and the drain of the NMOS tube _M9 is connected to the drain of the PMOS tube _M8 and used as the output terminal of the slew rate enhancement circuit;

The drain of the PMOS transistor M ₀ is connected to the drain of the NMOS transistor M ₁ , the source of the PMOS transistor M ₀ is connected to the external input power supply V _IN , and the gate of the PMOS transistor M ₀ is connected to the external bias voltage V _b .

The advantages of the present invention are: the present invention adopts the slew rate enhancement technology, and when the load of the LDO jumps transiently, the grid of the power adjustment tube is transiently adjusted according to the situation of the output terminal V _out , which greatly improves the power adjustment tube grid. The slew rate improves the transient response of the LDO circuit and also improves the output accuracy of the LDO.

Description of drawings

Figure 1 is a schematic diagram of a traditional LDO structure.

FIG. 2 is a schematic structural diagram of the slew rate enhancement circuit of the present invention.

Figure 3 is a schematic diagram of the LDO structure.

FIG. 4 is an equivalent small-signal circuit diagram of the LDO of the present invention.

detailed description

As shown in Figure 2, a slew rate enhancement circuit applied to LDO includes PMOS transistors M _{0 ,} M ₂ , M ₄ , M ₆ , M ₈ , NMOS transistors M ₁ , M ₃ , M ₅ , M ₇ , M ₉ and capacitor C _f ; one end of the capacitor C _f is the input end of the slew rate enhancement circuit, and the other end is respectively connected to the grid and drain of the PMOS transistor M ₂ , the grid of the PMOS transistor M ₄ , and the PMOS transistor M The gate of ₆ and the drain _of NMOS transistor M3 are connected;

_The source of the PMOS transistor _M2 is _respectively connected to the source of the PMOS transistor M0, the source of the PMOS transistor M4, the source of the PMOS transistor _M6 , and the source of the PMOS transistor _M8 , and is connected to the external input power supply V _IN , _The drain of the PMOS transistor _M2 is connected to the drain of the NMOS transistor M3, and the gate of the PMOS transistor _M2 is connected to the gate of the PMOS transistor M4 _;

_The drain of the PMOS transistor M4 is connected to the drain of the NMOS transistor _M5 and the gate of the NMOS transistor _{M9 ;} the gate of the NMOS transistor M5 is respectively connected to the gate and drain _of the NMOS transistor M1 and the gate _of the NMOS transistor M3. Grid, the grid of NMOS transistor _M7 ;

_The drain of the NMOS transistor M1 is connected to the drain _of the PMOS transistor M0, the source _of the NMOS transistor M1 is connected to the source of the NMOS transistor M3, the source of the NMOS transistor _M5 , the source of the NMOS transistor _M7 and the _NMOS transistor _M9 The source level of the connected and grounded;

The gate of the NMOS transistor M3 is connected to the gate of the NMOS transistor _M5 , the gate _of the NMOS transistor M1, and the gate _of the NMOS transistor _M7 . The source _of the NMOS transistor M3 is connected to the source _of the NMOS transistor M1, the NMOS The source level of the tube _M5 , the source level of the NMOS tube _M7 and the source level of the NMOS tube _M9 are connected and grounded;

_The drain of the NMOS transistor _M5 is connected to the drain of the PMOS transistor M4 and the gate of the NMOS transistor _M9 , and the source of the NMOS transistor _M5 is connected to the source _of the NMOS transistor M1, the source _of the NMOS transistor M3, and the NMOS transistor M9. The source of M ₇ is connected to the source of NMOS transistor M ₉ and grounded;

_The gate of the PMOS transistor _M6 is connected to the gates of the PMOS transistor _M2 and the PMOS transistor M4, the drain of the PMOS transistor _M6 is connected to the drain of the NMOS transistor _M7 and the gate of the PMOS transistor _M8 , and the PMOS transistor M ₆ The source stage is connected to the sources of PMOS transistor M ₀ , PMOS transistor M ₂ , PMOS transistor M ₄ , and PMOS transistor M ₈ , and is connected to an external input power supply V _IN ;

_The gate of the NMOS transistor _M7 is connected to the gate _of the NMOS transistor M1, the gate _of the NMOS transistor M3, and the gate of the NMOS transistor _M5 , and the drain of the NMOS transistor M7 is connected to the drain of the PMOS transistor _M6 and the PMOS _The gate of the transistor M8 is connected, the source of the NMOS transistor _M7 is connected to the source _of the NMOS transistor M1, the source _of the NMOS transistor M3, the source of the NMOS transistor _M5 , and the source of the NMOS transistor _M9 and grounded ;

_The gate of the PMOS transistor M8 is connected to the drains of the PMOS transistor _M6 and the NMOS transistor _M7 , the drain of the PMOS transistor _M8 is connected to the drain of the NMOS transistor _M9 , and the source of the PMOS transistor _M8 is connected to the PMOS transistor M _{0. The} sources of the PMOS transistor _M2 , the PMOS transistor M4 and the PMOS transistor _M6 are connected, and connected to the external input power supply V _IN ;

_The gate of the NMOS transistor _M9 is connected to the drain of the PMOS transistor M4 and the drain of the NMOS transistor _M5 , the source of the NMOS transistor _M9 is connected to the source _of the NMOS transistor M1, the source _of the NMOS transistor M3, the NMOS _The source of the tube _M5 is connected to the source of the NMOS tube M7 and grounded, and the drain of the NMOS tube _M9 is connected to the drain of the PMOS tube _M8 and used as the output terminal of the slew rate enhancement circuit;

The drain of the PMOS transistor M ₀ is connected to the drain of the NMOS transistor M ₁ , the source of the PMOS transistor M ₀ is connected to the external input power supply V _IN , and the gate of the PMOS transistor M ₀ is connected to the external bias voltage V _b .

As shown in Figure 3, an LDO integrated with a slew rate enhancement circuit includes a _PMOS transistor MP, an error amplifier 1, a voltage buffer 2, a reference voltage module 3, a feedback circuit 4, and a compensation capacitor C _C , the error The inverting input terminal of the amplifier 1 is connected to the reference voltage module 3, the non-inverting input terminal of the error amplifier 1 is connected to the output terminal of the feedback circuit 4, the output terminal of the error amplifier 1 is connected to the input terminal of the voltage buffer 2, and the output terminal of the voltage buffer 2 Connect to the gate of the _PMOS transistor MP, the drain of the _PMOS transistor MP is connected to the input end of the feedback circuit and used as the output end of the LDO, the drain of the _PMOS transistor MP is also connected to one end of the compensation capacitor C _C , and the compensation capacitor C _C The other end is connected to the output terminal of the error amplifier 1, the source of the _PMOS transistor MP is connected to the external input power supply V _IN , the output terminal of the voltage buffer 2 is connected to the output terminal of the slew rate enhancement circuit, and the drain of the _PMOS transistor MP is connected to the slew rate input to the booster circuit.

The feedback circuit 4 is composed of a first resistor R _f1 and a second resistor R _f2 , one end of the first resistor R _f1 is connected to the drain of the _PMOS transistor MP, and the other end of the first resistor R _f1 is connected to the second resistor R _f2 One terminal of the second resistor R f2 is connected to the non-inverting input terminal of the error amplifier as the output terminal of the feedback circuit, and the other terminal of the second resistor R _f2 is grounded.

The working principle of the present invention is: the _PMOS tube M0 realizes the function of the bias current source, the _PMOS tube _MP realizes the function of the power adjustment tube, V _out is the output voltage of the LDO, V _G is the gate voltage of the PMOS tube MP, Because there is an imbalance between M ₄ and M ₅ , when V _out does not drop, point X is at a low level, and M ₉ is always turned off until the load current increases, causing V _out to drop. Since the voltage difference between the two ends of the capacitor cannot change suddenly, C _f can quickly sample the drop of the output voltage, and then cause the decrease of the drain and gate voltage of _M2 to make the voltage of point X rise and turn on, which accelerates the discharge speed of the power adjustment tube gate capacitance. Similarly, due to the imbalance between M ₈ and M ₉ , when V _out does not rise, point Y is at a high level, M ₈ is closed until the load current decreases, V _out rises, so that the voltage of point Y drops and turns on, and a large voltage is generated instantaneously. The current rapidly charges the gate capacitance of the _PMOS transistor MP. Because when the LDO is working normally, M ₈ and M ₉ are closed, and the capacitance of C _f is small (0.5-0.8pF), so it does not affect the main loop. Since the circuit directly reflects the change of the output voltage to the gate of the regulator instead of slowly responding through the main loop, the error amplifier does not need a relatively large GBW, which saves power consumption and improves the transient state of the LDO. responsiveness.

It is worth noting that, in order to make misalignment exist between M ₄ and M ₅ , M ₆ and M ₇ , and make X and Y points be low level and high level respectively in steady state, M ₄ and M ₅ , M The width-to-length ratio of ₆ and M ₇ must have the following relationship:

Stability analysis: The equivalent small-signal circuit diagram of the LDO proposed by the present invention is shown in Figure 4, and P ₁ , P ₂ , and P ₃ are respectively the poles at the output of the error amplifier EA, the output of the voltage buffer buffer, and the output of the LDO ; A ₁ , A ₂ , A ₃ are the gain of the error amplifier, voltage buffer and LDO output stage respectively, C ₁ , C ₂ , C _out are the capacitances of the error amplifier, voltage buffer and LDO output respectively, R _EA , R _buffer and R _out are the impedance of the error amplifier, voltage buffer and LDO output respectively, g _m1 , g _m2 and g _m3 are the input transconductance of the three respectively, and C _C is the Miller compensation capacitance.

The gain A _dc of the whole LDO circuit:

Because the voltage buffer used is a super source follower with ultra _- low output impedance, the R _buffer is very small, so the pole P2 is located at high frequency, which does not affect the stability of the circuit. Due to the Miller compensation technique that doubles the capacitance at the output _of the error amplifier, pole P1 is the dominant pole and pole _P3 is the secondary point at heavy loads. While at light load, pole _P3 is the primary pole and pole _P1 is the secondary point. The secondary point is outside the unity-gain bandwidth over the entire load current range. Therefore, the overall circuit of the LDO is stable.

The slew rate enhancement circuit proposed by the present invention can be used in any design that needs to improve the transient response performance of the LDO. The slew rate enhancement technology adopted in the present invention can ensure that when the load of the LDO jumps transiently, the grid of the power adjustment tube is transiently adjusted according to the situation of the output terminal V _out , and the slew rate of the grid of the power adjustment tube is greatly improved. Thereby improving the transient response of the LDO.

Those skilled in the art should realize that the embodiments described here are just to help readers understand the principles of the present invention, and it should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other modifications and combinations based on the technical revelations disclosed in the present invention without departing from the essence of the present invention, and these modifications and combinations are still within the protection scope of the present invention.

Claims (1)

1. A slew rate enhancement circuit applied to LDO, including PMOS transistors M _{0 ,} M ₂ , M ₄ , M ₆ , M ₈ , NMOS transistors M ₁ , M ₃ , M ₅ , M ₇ , M ₉ and capacitors C _f , characterized in that: one end of the capacitor C _f is the input end of the slew rate enhancement circuit, and the other end is respectively connected to the gate and drain of the _PMOS transistor _M2 , the gate of the PMOS transistor M4, and the PMOS transistor M The gate of ₆ and the drain _of NMOS transistor M3 are connected; _The source of the PMOS transistor _M2 is _respectively connected to the source of the PMOS transistor M0, the source of the PMOS transistor M4, the source of the PMOS transistor _M6 , and the source of the PMOS transistor _M8 , and is connected to the external input power supply V _IN , _The drain of the PMOS transistor _M2 is connected to the drain of the NMOS transistor M3, and the gate of the PMOS transistor _M2 is connected to the gate of the PMOS transistor M4 _{; The} drain of the PMOS transistor M4 is connected to the drain of the NMOS transistor _M5 and the gate of the NMOS transistor _{M9 ;} the gate of the NMOS transistor M5 is respectively connected to the gate and drain _of the NMOS transistor M1 and the gate _of the NMOS transistor M3. Grid, the grid of NMOS transistor _M7 ; _The drain of the NMOS transistor M1 is connected to the drain _of the PMOS transistor M0, the source _of the NMOS transistor M1 is connected to the source of the NMOS transistor M3, the source of the NMOS transistor _M5 , the source of the NMOS transistor _M7 and the _NMOS transistor _M9 The source level of the connected and grounded; The gate of the NMOS transistor M3 is connected to the gate of the NMOS transistor _M5 , the gate _of the NMOS transistor M1, and the gate _of the NMOS transistor _M7 . The source _of the NMOS transistor M3 is connected to the source _of the NMOS transistor M1, the NMOS The source level of the tube _M5 , the source level of the NMOS tube _M7 and the source level of the NMOS tube _M9 are connected and grounded; _The drain of the NMOS transistor _M5 is connected to the drain of the PMOS transistor M4 and the gate of the NMOS transistor _M9 , and the source of the NMOS transistor _M5 is connected to the source _of the NMOS transistor M1, the source _of the NMOS transistor M3, and the NMOS transistor M9. The source of M ₇ is connected to the source of NMOS transistor M ₉ and grounded; _The gate of the PMOS transistor _M6 is connected to the gates of the PMOS transistor _M2 and the PMOS transistor M4, the drain of the PMOS transistor _M6 is connected to the drain of the NMOS transistor _M7 and the gate of the PMOS transistor _M8 , and the PMOS transistor M ₆ The source stage is connected to the sources of PMOS transistor M ₀ , PMOS transistor M ₂ , PMOS transistor M ₄ , and PMOS transistor M ₈ , and is connected to an external input power supply V _IN ; _The gate of the NMOS transistor _M7 is connected to the gate _of the NMOS transistor M1, the gate _of the NMOS transistor M3, and the gate of the NMOS transistor _M5 , and the drain of the NMOS transistor M7 is connected to the drain of the PMOS transistor _M6 and the PMOS _The gate of the transistor M8 is connected, the source of the NMOS transistor _M7 is connected to the source _of the NMOS transistor M1, the source _of the NMOS transistor M3, the source of the NMOS transistor _M5 , and the source of the NMOS transistor _M9 and grounded ; _The gate of the PMOS transistor M8 is connected to the drains of the PMOS transistor _M6 and the NMOS transistor _M7 , the drain of the PMOS transistor _M8 is connected to the drain of the NMOS transistor _M9 , and the source of the PMOS transistor _M8 is connected to the PMOS transistor M _{0. The} sources of the PMOS transistor _M2 , the PMOS transistor M4 and the PMOS transistor _M6 are connected, and connected to the external input power supply V _IN ; _The gate of the NMOS transistor _M9 is connected to the drain of the PMOS transistor M4 and the drain of the NMOS transistor _M5 , the source of the NMOS transistor _M9 is connected to the source _of the NMOS transistor M1, the source _of the NMOS transistor M3, the NMOS _The source of the tube _M5 is connected to the source of the NMOS tube M7 and grounded, and the drain of the NMOS tube _M9 is connected to the drain of the PMOS tube _M8 and used as the output terminal of the slew rate enhancement circuit; The drain of the PMOS transistor M ₀ is connected to the drain of the NMOS transistor M ₁ , the source of the PMOS transistor M ₀ is connected to the external input power supply V _IN , and the gate of the PMOS transistor M ₀ is connected to the external bias voltage V _b .