CN204967763U - Wake flow feedback broad tuning voltage controlled oscillator - Google Patents

Abstract

The utility model discloses a wake feedback wide-tuning voltage-controlled oscillator, which comprises an oscillating core circuit, a wake array circuit and two output driving circuits with identical structures. The oscillating core circuit is connected between the first output driving circuit and the second output driving circuit. The first output driver circuit forms one output of the oscillator and the second output driver circuit forms the other output of the oscillator. One end of the wake array circuit is respectively connected to the bias voltage and the first output driving circuit. The other end of the wake array circuit is respectively connected to the bias voltage and the second output drive circuit. The wake source array that changes with the switch capacitor access is used, so that the voltage controlled oscillator can have better phase noise performance in a wide tuning range; at the same time, the drain is driven from the output through the DC blocking capacitor to the main tail tube NM21, The gate of NM22 provides feedback bias, which reduces the flicker noise introduced by the tail tube and further optimizes the phase noise performance.

Description

A Wake Feedback Widely Tuned Voltage Controlled Oscillator

technical field

The utility model belongs to the field of integrated circuit design, in particular to a wake feedback wide-tuning voltage-controlled oscillator.

Background technique

Voltage Controlled Oscillator (VCO, Voltage Controlled Oscillator) is an important module of circuits such as clock recovery, phase-locked loop and frequency synthesizer, and is widely used in electronic systems such as mobile phones, military communication systems, satellite communication terminals, and wireless digital communications. There are generally two types of oscillator circuit structures: ring oscillators and LC oscillators. Due to the simple structure of the LC oscillator circuit and its high phase noise performance, it has been most widely used in high-performance SoCs.

In traditional differential negative-resistance voltage-controlled oscillators, the tail tube has a very large impact on the phase noise, especially in the case of small frequency offsets. In 2001, E.Hegazi et al proposed several methods to suppress the noise brought by the wake source in the literature AfilteringtechniquetolowerLCoscillatorphasenoise, one of which is noise filtering technology. This technique improves the phase noise performance by filtering out the second harmonic of the oscillation frequency, but introduces an additional inductance and increases the chip area, and it is not sure whether it reduces the contribution of flicker noise to the phase noise. In L.Fanori, P.Andreani's literature A2.5-to-3.3GHzCMOSClass-DVCO, the phase noise is reduced by removing the wake source, but the flicker noise of the negative resistance tube will be directly injected into the resonant cavity, and at the same time make the oscillator to the power supply noise sensitive, which affects the phase noise performance.

Utility model content

The technical problem to be solved by the utility model is to provide a wake feedback wide-tuned voltage-controlled oscillator, which can effectively reduce the flicker noise of the wake tube.

In order to solve the above problems, the utility model is achieved through the following technical solutions:

A wake feedback wide-tuning voltage-controlled oscillator, including an oscillator body, wherein the oscillator body includes an oscillating core circuit and two output drive circuits with identical structures; the two ends of the oscillating core circuit are respectively connected to the first output drive circuit and a second output drive circuit; the first output drive circuit forms one output end of the oscillator body, and the second output drive circuit forms the other output end of the oscillator body; wherein the oscillation core circuit includes several parallel switched capacitor branches ; The difference is that it further includes a wake array circuit; wherein the wake array circuit includes several parallel wake branches, and the number of wake branches is the same as the number of switched capacitor branches; One end of the wake array circuit is simultaneously connected to the first output drive circuit and the external bias voltage Vb, and the other end of the wake array circuit is simultaneously connected to the second output drive circuit and the external bias voltage Vb.

The above wake array circuit includes two wake source NMOS transistors and several parallel wake branches. After the drain of the first wake source NMOS transistor NM22 is connected to the drain of the second wake source NMOS transistor NM21, it is connected to the source of the first oscillating NMOS transistor NM1 and the second oscillating NMOS transistor NM2; the first wake source After the NMOS transistor NM22 is connected to the source of the second wake source NMOS transistor NM21, it is then electrically grounded; the gate of the first wake source NMOS transistor NM22 is divided into two routes, one of which is connected to the first output drive circuit, and the other is connected to the bias set the voltage Vb; the gate of the second wake source NMOS transistor NM21 is divided into 2 paths, one path is connected to the second output drive circuit, and the other path is connected to the bias voltage Vb; the number of wake branches and the number of switched capacitor branches The same; each wake branch includes 3 wake NMOS transistors and 1 inverter; the input terminal of the inverter and the gate of the second wake NMOS transistor are connected to the corresponding control voltage at the same time; the second wake NMOS The source of the transistor is connected to the DC bias voltage Vb; the drain of the second wake NMOS transistor, the gate of the first wake NMOS transistor are connected to the drain of the third wake NMOS transistor; the output terminal of the inverter is connected to The gate of the third wake NMOS transistor; the drain of the first wake NMOS transistor is connected to the source of the first oscillating NMOS transistor NM1 and the second oscillating NMOS transistor NM2; the first wake NMOS transistor and the third wake NMOS transistor The source is electrically grounded.

The above-mentioned oscillating core circuit includes a negative resistance oscillating unit, a switched capacitor array unit, a resonant inductance ind and a variable capacitor branch. The negative resistance oscillation unit includes cross-coupled first oscillation NMOS transistor NM1 and second oscillation NMOS transistor NM2, first oscillation PMOS transistor PM1 and second oscillation PMOS transistor PM2; first oscillation PMOS transistor PM1 and first oscillation NMOS transistor NM1 After the drains of the second oscillating PMOS transistor PM2 and the drains of the second oscillating NMOS transistor NM2 are connected, they are connected to the second output driving circuit; the first oscillating PMOS transistor PM1 and the second oscillating PMOS The source of the transistor PM2 is connected to the power supply; the sources of the first oscillating NMOS transistor NM1 and the second oscillating NMOS transistor NM2 are connected to the wake array circuit. One end of the resonant inductor ind is connected to the drains of the second oscillating PMOS transistor PM2 and the second oscillating NMOS transistor NM2 , and the other end is connected to the drains of the first oscillating PMOS transistor PM1 and the first oscillating NMOS transistor NM1 . The switched capacitor array unit includes several parallel switched capacitor branches, and each switched capacitor branch includes a switched NMOS transistor, 2 switched capacitors with equal capacitance and 2 switched resistors with equal resistance; the gate of the switched NMOS transistor Connect the corresponding control voltage; one end of one of the two switched capacitors is connected to the source of the switch NMOS transistor, and the other end is connected to the drain of the second oscillating PMOS transistor PM2 and the second oscillating NMOS transistor NM2; two switched capacitors One end of the other switched capacitor is connected to the drain of the switch NMOS transistor, and the other end is connected to the drains of the first oscillating PMOS transistor PM1 and the first oscillating NMOS transistor NM1; one end of one of the two switched resistors is connected to the switch The source of the NMOS transistor is electrically grounded at the other end; one end of the other switch resistor among the two switch resistors is connected to the drain of the switch NMOS transistor, and the other end is electrically grounded. The variable capacitor branch circuit includes a first variable capacitor Cv1 and a second variable capacitor Cv2; after the first variable capacitor Cv1 and the second variable capacitor Cv2 are connected in series, one end thereof is connected to the second oscillating PMOS transistor PM2 and the second oscillating NMOS The drain of the transistor NM2 is connected, and the other end is connected to the drains of the first oscillating PMOS transistor PM1 and the first oscillating NMOS transistor NM1; the connected ends of the first variable capacitor Cv1 and the second variable capacitor Cv2 are connected to the tuning voltage Vtune.

Each output drive circuit includes 1 drive NMOS transistor, 1 drive PMOS transistor, 2 drive capacitors and 1 drive resistor; the source of the drive PMOS transistor is connected to the power supply; the source of the drive NMOS transistor is electrically grounded; the drive NMOS After the transistor is connected to the gate of the driving PMOS transistor, it is connected to the oscillation core circuit through a driving capacitor; the driving NMOS transistor is connected to the drain of the driving PMOS transistor and then divided into two circuits, and one road passes through another driving capacitor to form the oscillator body. The other end of the output end is connected to the wake array circuit; one end of the driving resistor is connected to the drains of the driving NMOS transistor and the driving PMOS transistor, and the other end is connected to the gates of the driving NMOS transistor and the driving PMOS transistor.

There are 4 switched capacitor branches and wake branches, wherein the ratio of the capacitance of the switched capacitors of the 4 switched capacitor branches is 1:2:4:8, and the switch resistance of these 4 switched capacitor branches The resistance value is equal.

The utility model proposes a wake source structure that can improve the phase noise performance of a voltage-controlled oscillator with a wide tuning range, and adopts a wake source array that changes with the access of the switch capacitor, so that the voltage-controlled oscillator can operate in a wide tuning range It can have better phase noise performance; at the same time, through the DC blocking capacitor, the output drive drain provides feedback bias for the gates of the main tail tubes NM21 and NM22, which reduces the flicker noise introduced by the tail tubes and further optimizes the phase noise performance.

Compared with the prior art, the utility model has the following characteristics:

1. A new wake source array structure with wake feedback is proposed. This circuit achieves better phase noise performance in a wide tuning range of 2GHz without significantly increasing the chip area;

2. The wide tuning range is divided into 16 continuous sub-bands, and the wake array makes each sub-band work at the best current to improve noise performance.

Description of drawings

Fig. 1 is a structural diagram of a circuit of a wake feedback wide tuned voltage controlled oscillator;

Fig. 2 is a tuning curve diagram of a wake feedback wide-tuned voltage-controlled oscillator.

detailed description

A wake feedback wide-tuned voltage-controlled oscillator, as shown in Figure 1, includes an oscillation core circuit, two output drive circuits and a wake array circuit. Two ends of the oscillating core circuit are respectively connected to the first output driving circuit and the second output driving circuit. The first output driving circuit forms one output terminal of the oscillator body, and the second output driving circuit forms the other output terminal of the oscillator body. One end of the wake array circuit is simultaneously connected to the bias voltage Vb and the first output drive circuit, and the other end of the wake array circuit is simultaneously connected to the bias voltage Vb and the second output drive circuit.

The above-mentioned oscillating core circuit is used to realize the coarse adjustment and fine adjustment of the resonant frequency. The oscillating core circuit includes a negative resistance oscillating unit, a switched capacitor array unit, a resonant inductance ind, and a variable capacitor branch.

The negative resistance oscillating unit includes a cross-coupled first oscillating NMOS transistor NM1 and a second oscillating NMOS transistor NM2 , and a first oscillating PMOS transistor PM1 and a second oscillating PMOS transistor PM2 . After the drains of the first oscillating PMOS transistor PM1 and the first oscillating NMOS transistor NM1 are connected, they are connected to the first output driving circuit. After the drains of the second oscillating PMOS transistor PM2 and the second oscillating NMOS transistor NM2 are connected, they are connected to the second output driving circuit. The sources of the first oscillating PMOS transistor PM1 and the second oscillating PMOS transistor PM2 are connected to the power supply. The sources of the first oscillating NMOS transistor NM1 and the second oscillating NMOS transistor NM2 are connected to the wake array circuit.

One end of the resonant inductor ind is connected to the drains of the second oscillating PMOS transistor PM2 and the second oscillating NMOS transistor NM2 , and the other end is connected to the drains of the first oscillating PMOS transistor PM1 and the first oscillating NMOS transistor NM1 .

The switched capacitor array unit includes several parallel switched capacitor branches, and each switched capacitor branch includes a switched NMOS transistor, two switched capacitors with equal capacitance and two switched resistors with equal resistance. The gate of the switching NMOS transistor is connected to the corresponding control voltage a, b, c or d. One end of one of the two switched capacitors is connected to the source of the switching NMOS transistor, and the other end is connected to the drains of the second oscillation PMOS transistor PM2 and the second oscillation NMOS transistor NM2 . One end of the other switched capacitor among the two switched capacitors is connected to the drain of the switching NMOS transistor, and the other end is connected to the drains of the first oscillation PMOS transistor PM1 and the first oscillation NMOS transistor NM1 . One end of one of the two switch resistors is connected to the source of the switch NMOS transistor, and the other end is electrically grounded. One end of the other switch resistor among the two switch resistors is connected to the drain of the switch NMOS transistor, and the other end is electrically grounded. In the present utility model, a switched capacitor array unit includes 4 switched capacitor branches, the ratio of the capacitance of the switched capacitors of these 4 switched capacitor branches is 1:2:4:8, the 4 switched capacitor branches The resistance values of the switch resistors are equal. The switched capacitor array unit is connected in parallel with the resonant inductance ind, and changes its own capacitance value according to the specified rule (control voltage a, b, c or d) to roughly adjust the resonant frequency of the oscillating core circuit.

The variable capacitor branch includes a first variable capacitor Cv1 and a second variable capacitor Cv2. After the first variable capacitor Cv1 and the second variable capacitor Cv2 are connected in series, one end thereof is connected to the drains of the second oscillating PMOS transistor PM2 and the second oscillating NMOS transistor NM2, and the other end is connected to the first oscillating PMOS transistor PM1 and the first oscillating The drains of the NMOS transistor NM1 are connected. Connected ends of the first variable capacitor Cv1 and the second variable capacitor Cv2 are connected to the tuning voltage Vtune. The variable capacitance branch is connected in parallel with the resonant inductance ind, and changes its own capacitance according to a change of a tuning voltage Vtune, so as to fine-tune the resonant frequency of the oscillating core circuit.

The above-mentioned wake array circuit makes the access current change with the access capacitance through the numerical control bit, so as to achieve better phase noise. The wake array circuit includes two wake source NMOS transistors and several parallel wake branches. After the first wake source NMOS transistor NM22 is connected to the drain of the second wake source NMOS transistor NM21 , it is connected to the source of the first oscillation NMOS transistor NM1 and the second oscillation NMOS transistor NM2 . After the first wake source NMOS transistor NM22 is connected to the source of the second wake source NMOS transistor NM21 , it is electrically grounded. The gate of the first tail current source NMOS transistor NM22 is divided into two paths, one path is connected to the first output driving circuit through a capacitor C14, and the other path is connected to the bias voltage Vb through a resistor R11. The gate of the second wake source NMOS transistor NM21 is divided into two paths, one path is connected to the second output driving circuit through another capacitor C13, and the other path is connected to the bias voltage Vb through another resistor R12. The number of wake branches is the same as the number of switched capacitor branches. Each wake branch includes 3 wake NMOS transistors and 1 inverter. The input terminal of the inverter and the gate of the second wake NMOS transistor are simultaneously connected to the corresponding control voltage a, b, c or d. The source of the second wake NMOS transistor is connected to the DC bias voltage Vb. The drain of the second wake NMOS transistor, the gate of the first wake NMOS transistor and the drain of the third wake NMOS transistor are connected. The output terminal of the inverter is connected to the gate of the third wake NMOS transistor. The drain of the first wake NMOS transistor is connected to the sources of the first oscillating NMOS transistor NM1 and the second oscillating NMOS transistor NM2 . Sources of the first wake NMOS transistor and the third wake NMOS transistor are electrically grounded. The second wake NMOS transistor and the third wake NMOS transistor work as MOS switches in opposite switching states, so as to control the turn-on and turn-off of the wake transistor NM9.

The structures of the two output driving circuits are exactly the same, and each output driving circuit includes one driving NMOS transistor, one driving PMOS transistor, two driving capacitors and one driving resistor. The source of the driving PMOS transistor is connected to the power supply. The source of the driving NMOS transistor is electrically grounded. After the gate of the driving NMOS transistor is connected with the gate of the driving PMOS transistor, it is connected with the oscillation core circuit through a driving capacitor. The drains of the driving NMOS transistor and the driving PMOS transistor are connected and then divided into two paths, one path forms the output terminal of the output signal (outL+ or outL-) after passing through another driving capacitor, and the other path is connected to the wake array circuit. One end of the driving resistor is connected to the drains of the driving NMOS transistor and the driving PMOS transistor, and the other end is connected to the gates of the driving NMOS transistor and the driving PMOS transistor.

The working principle of the voltage-controlled oscillator mentioned in the utility model is as follows, the start-up condition of the differential complementary MOS transistor LC voltage-controlled oscillator must meet

${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}<span\; class="notranslate">\; ></span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; p</span>}}}$

In the formula, Rp is the parallel equivalent resistance of the LC resonant circuit, gmn is the transconductance of the NMOS negative resistance transistor, gmp is the transconductance of the PMOS negative resistance transistor, and the current provided by the current source is obtained between the PMOS pair of transistors and the NMOS pair of transistors Multiplexing reduces the power consumption of the circuit; the negative transconductance of the NM1, NM2 tubes and PM1, PM2 tubes can compensate the circuit loss in the oscillation and provide energy for the oscillation. The voltage-controlled voltage Vtune controls the variable capacitor Cv to achieve the purpose of controlling the oscillation frequency; as shown in Figure 2, the coarse tuning of the frequency realized by using a four-bit binary weighted switched capacitor array reduces the number of digits of the digital control signal, a, b , c, d are four digital control signals, which divide the entire frequency range into 16 sub-bands. Since the current required by each sub-band is different, the wake array can make each sub-band work at an appropriate current to achieve better phase noise. Set 1.8V as the high level 1, and the low level as 0. When the values of a, b, c, and d are 1111, the output frequency band of the oscillator is the corresponding curve at the lowest position in Figure 2; when the values are all 0000, the oscillation The output frequency band of the oscillator is the corresponding curve of the highest position in Figure 2; when a, b, c, and d take 1111, the oscillator needs the largest current, and the wake array is all turned on and connected; when the values are all 0000, the oscillator needs The current is the minimum, the wake arrays are all turned off, and the current is only provided by NM21 and NM22.

It should be emphasized that: the above are only preferred embodiments of the present utility model, and are not limitations of the present utility model. Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present utility model are still valid. It belongs to the scope of the technical solution of the utility model.

Claims (4)

1. A wake feedback wide-tuning voltage-controlled oscillator, including an oscillator body, wherein the oscillator body includes an oscillating core circuit and 2 output drive circuits with identical structures; the two ends of the oscillating core circuit are respectively connected to the first An output drive circuit and a second output drive circuit; the first output drive circuit forms one output end of the oscillator body, and the second output drive circuit forms the other output end of the oscillator body; wherein the oscillation core circuit includes several parallel switched capacitors branch; characterized in that: it further includes a wake array circuit; wherein the wake array circuit includes several parallel wake branches, and the number of wake branches is the same as the number of switched capacitor branches; One end of the wake array circuit is simultaneously connected to the first output drive circuit and the external bias voltage Vb, and the other end of the wake array circuit is simultaneously connected to the second output drive circuit and the external bias voltage Vb. 2. A wake feedback wide-tuned voltage-controlled oscillator according to claim 1, characterized in that: the wake array circuit includes two wake source NMOS transistors and several parallel wake branches; After the drain of the first wake source NMOS transistor NM22 is connected to the drain of the second wake source NMOS transistor NM21, it is connected to the source of the first oscillating NMOS transistor NM1 and the second oscillating NMOS transistor NM2; the first wake source After the NMOS transistor NM22 is connected to the source of the second wake source NMOS transistor NM21, it is then electrically grounded; the gate of the first wake source NMOS transistor NM22 is divided into two routes, one of which is connected to the first output drive circuit, and the other is connected to the bias set the voltage Vb; the gate of the second wake source NMOS transistor NM21 is divided into 2 paths, one path is connected to the second output drive circuit, and the other path is connected to the bias voltage Vb; the number of wake branches and the number of switched capacitor branches The same; each wake branch includes 3 wake NMOS transistors and 1 inverter; the input terminal of the inverter and the gate of the second wake NMOS transistor are connected to the corresponding control voltage at the same time; the second wake NMOS The source of the transistor is connected to the DC bias voltage Vb; the drain of the second wake NMOS transistor, the gate of the first wake NMOS transistor are connected to the drain of the third wake NMOS transistor; the output terminal of the inverter is connected to The gate of the third wake NMOS transistor; the drain of the first wake NMOS transistor is connected to the source of the first oscillating NMOS transistor NM1 and the second oscillating NMOS transistor NM2; the first wake NMOS transistor and the third wake NMOS transistor The source is electrically grounded. 3. A wake feedback wide-tuning voltage-controlled oscillator according to claim 1, characterized in that: the above-mentioned oscillation core circuit includes a negative resistance oscillation unit, a switched capacitor array unit, a resonant inductance ind and a variable capacitance branch; The negative resistance oscillation unit includes cross-coupled first oscillation NMOS transistor NM1 and second oscillation NMOS transistor NM2, first oscillation PMOS transistor PM1 and second oscillation PMOS transistor PM2; first oscillation PMOS transistor PM1 and first oscillation NMOS transistor NM1 After the drains of the second oscillating PMOS transistor PM2 and the drains of the second oscillating NMOS transistor NM2 are connected, they are connected to the second output driving circuit; the first oscillating PMOS transistor PM1 and the second oscillating PMOS The source of the transistor PM2 is connected to the power supply; the sources of the first oscillating NMOS transistor NM1 and the second oscillating NMOS transistor NM2 are connected to the wake array circuit; One end of the resonant inductor ind is connected to the drains of the second oscillating PMOS transistor PM2 and the second oscillating NMOS transistor NM2, and the other end is connected to the drains of the first oscillating PMOS transistor PM1 and the first oscillating NMOS transistor NM1; The switched capacitor array unit includes several parallel switched capacitor branches, and each switched capacitor branch includes a switched NMOS transistor, 2 switched capacitors with equal capacitance and 2 switched resistors with equal resistance; the gate of the switched NMOS transistor Connect the corresponding control voltage; one end of one of the two switched capacitors is connected to the source of the switch NMOS transistor, and the other end is connected to the drain of the second oscillating PMOS transistor PM2 and the second oscillating NMOS transistor NM2; two switched capacitors One end of the other switched capacitor is connected to the drain of the switch NMOS transistor, and the other end is connected to the drains of the first oscillating PMOS transistor PM1 and the first oscillating NMOS transistor NM1; one end of one of the two switched resistors is connected to the switch The source of the NMOS transistor is electrically grounded at the other end; one end of the other switch resistor among the two switch resistors is connected to the drain of the switch NMOS transistor, and the other end is electrically grounded; The variable capacitor branch circuit includes a first variable capacitor Cv1 and a second variable capacitor Cv2; after the first variable capacitor Cv1 and the second variable capacitor Cv2 are connected in series, one end thereof is connected to the second oscillating PMOS transistor PM2 and the second oscillating NMOS The drain of the transistor NM2 is connected, and the other end is connected to the drains of the first oscillating PMOS transistor PM1 and the first oscillating NMOS transistor NM1; the connected ends of the first variable capacitor Cv1 and the second variable capacitor Cv2 are connected to the tuning voltage Vtune. 4. A wake feedback wide-tuned voltage-controlled oscillator according to claim 1, characterized in that: each output drive circuit includes a driving NMOS transistor, a driving PMOS transistor, two driving capacitors and a A drive resistor; the source of the drive PMOS transistor is connected to the power supply; the source of the drive NMOS transistor is electrically grounded; after the gate of the drive NMOS transistor is connected to the gate of the drive PMOS transistor, it is connected to the oscillation core circuit through a drive capacitor; the drive NMOS transistor and the gate of the drive PMOS transistor are connected; The drains of the driving PMOS transistors are connected and divided into two circuits, one of which passes through another driving capacitor to form the output terminal of the oscillator body, and the other is connected to the wake array circuit; one end of the driving resistor is connected to the drains of the driving NMOS transistor and the driving PMOS transistor , and the other end is connected to the gates of the driving NMOS transistor and the driving PMOS transistor.