CN103095217B - Low Phase Noise Voltage-controlled Oscillator - Google Patents
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Abstract
Description
技术领域technical field
本发明属于射频无线接收机集成电路技术领域,具体涉及一种低相位噪声压控振荡器。The invention belongs to the technical field of radio frequency wireless receiver integrated circuits, and in particular relates to a voltage-controlled oscillator with low phase noise.
背景技术Background technique
压控振荡器是通信系统中用于产生本振信号的模块,其性能直接决定通信系统的性能。相位噪声作为压控振荡器的一个主要性能指标,影响着接收机的灵敏度和发射机的临近信道干扰。因此设计一个低相位噪声的压控振荡器对现代无线通信系统显的尤为重要。A voltage-controlled oscillator is a module used to generate local oscillator signals in a communication system, and its performance directly determines the performance of the communication system. As a main performance index of the voltage controlled oscillator, the phase noise affects the sensitivity of the receiver and the adjacent channel interference of the transmitter. Therefore, it is particularly important to design a voltage-controlled oscillator with low phase noise for modern wireless communication systems.
压控振荡器的实现形式主要有环形振荡器和电感电容压控振荡器。环形振荡器由于相位噪声性能较差,主要被用于产生片上时钟信号。而电感电容压控振荡器由于其良好的相位噪声性能而广泛应用于无线通信领域。The implementation forms of voltage-controlled oscillators mainly include ring oscillators and inductor-capacitor voltage-controlled oscillators. Ring oscillators are mainly used to generate on-chip clock signals due to their poor phase noise performance. The LC-VCO is widely used in the field of wireless communication because of its good phase noise performance.
根据D.B.Lesson相位噪声模型公式,电感电容压控振荡器的相位噪声L(Δf)可表示为:According to the D.B.Lesson phase noise model formula, the phase noise L(Δf) of the LC voltage-controlled oscillator can be expressed as:
其中Δf为偏移频率,fo为振荡频率,F为噪声指数,k为玻尔兹曼常数,T为绝对温度值,Q为谐振腔品质因数,Vp为谐振腔振荡信号幅度,Rp为谐振腔等效并联电阻。Where Δf is the offset frequency, f o is the oscillation frequency, F is the noise figure, k is the Boltzmann constant, T is the absolute temperature value, Q is the quality factor of the resonant cavity, V p is the oscillation signal amplitude of the resonant cavity, and R p is the equivalent parallel resistance of the resonant cavity.
从式(1)可知,为优化相位噪声性能,可通过提高谐振腔的品质因数Q和提高振荡信号的幅度Vp来实现。由于片上电容的品质因数远远大于片上电感的品质因数,谐振腔的品质因数主要由片上电感决定。然而,趋肤效应及衬底的高损耗等因素的影响,片上电感可获得的品质因数有限。另一方面,随着CMOS工艺特征尺寸的减小,电源电压相应降低,压控振荡器输出信号振幅也随之减小,这使得低相位噪声的优化设计变的十分困难。It can be seen from formula (1) that in order to optimize the phase noise performance, it can be realized by improving the quality factor Q of the resonant cavity and increasing the amplitude V p of the oscillation signal. Since the quality factor of the on-chip capacitor is much greater than that of the on-chip inductor, the quality factor of the resonant cavity is mainly determined by the on-chip inductor. However, due to factors such as the skin effect and the high loss of the substrate, the available quality factor of the on-chip inductor is limited. On the other hand, as the feature size of the CMOS process decreases, the power supply voltage decreases accordingly, and the output signal amplitude of the voltage-controlled oscillator also decreases, which makes the optimal design of low phase noise very difficult.
发明内容Contents of the invention
本发明的目的在于提供一种低相位噪声压控振荡器,采取的技术方案如下:The object of the present invention is to provide a kind of low phase noise voltage controlled oscillator, the technical scheme that takes is as follows:
一种低相位噪声压控振荡器,其特征是:包括负阻电路模块、差分耦合电感电容谐振腔,其中:A voltage-controlled oscillator with low phase noise is characterized in that it includes a negative resistance circuit module and a differentially coupled inductor-capacitor resonant cavity, wherein:
负阻电路模块包括PMOS管Mp、NMOS管Mn、两个电感值相等的源级反馈电感Ls1和Ls2;电源VDD串联源级反馈电感Ls1后连接PMOS管Mp的源极,NMOS管Mn的源极串联源级反馈电感Ls2后接地,PMOS管Mp的栅极连接NMOS管Mn的漏极作为输出端Vp,NMOS管Mn的栅极连接PMOS管Mp的漏极作为输出端Vn;The negative resistance circuit module includes a PMOS transistor M p , an NMOS transistor M n , and two source-level feedback inductors L s1 and L s2 with equal inductance values; the power supply VDD is connected in series with the source-level feedback inductor L s1 to the source of the PMOS transistor M p , The source of the NMOS transistor M n is connected in series with the source feedback inductance L s2 and grounded, the gate of the PMOS transistor M p is connected to the drain of the NMOS transistor M n as the output terminal V p , and the gate of the NMOS transistor M n is connected to the PMOS transistor M p The drain of is used as the output terminal V n ;
差分耦合电感电容谐振腔包括差分电感Ld和差分电感Lc以及两个可变电容Cv;差分电感Ld由电感Ld1与电感Ld2串联组成,且电感Ld1与电感Ld2的电感值相等,电感Ld1与电感Ld2未连接在一起的一端分别与负阻电路模块输出端Vp与输出端Vn连接;差分电感Lc由电感Lc1与电感Lc2串联组成,且电感Lc1与电感Lc2的电感值相等,电感Lc1与电感Lc2对接端与直流偏置电压Vb相连;两个可变电容Cv背靠背对接,对接端与模拟调谐电压Vctrl相连,两个可变电容Cv未连接在一起的一端分别与电感Lc1与电感Lc2未连接在一起的一端连接。The differential coupled inductance-capacitance resonant cavity includes differential inductance L d and differential inductance L c and two variable capacitors C v ; differential inductance L d is composed of inductance L d1 and inductance L d2 in series, and the inductance of inductance L d1 and inductance L d2 The values are equal, the ends of the inductance L d1 and the inductance L d2 that are not connected together are respectively connected to the output terminal V p of the negative resistance circuit module and the output terminal V n ; the differential inductance L c is composed of the inductance L c1 and the inductance L c2 connected in series, and the inductance The inductance values of L c1 and inductor L c2 are equal, and the butt ends of inductor L c1 and inductor L c2 are connected to the DC bias voltage V b ; two variable capacitors C v are connected back to back, and the butt ends are connected to the analog tuning voltage V ctrl . The unconnected ends of the variable capacitors C v are respectively connected to the unconnected ends of the inductance L c1 and the inductance L c2 .
所说差分电感Ld、差分电感Lc、源级反馈电感Ls1和源级反馈电感Ls2均形成于衬底上,差分电感Ld和Lc均采用对称差分结构且电感Lc形成于电感Ld的正下方,源级反馈电感Ls1与Ls2对称形成于差分电感Ld的周围,电感Ld1与电感Lc1、电感Ld2与电感Lc2之间的耦合系数为0.94,电感Ld1与电感Ls1、电感Ld2与电感Ls2之间的耦合系数为0.38,电感Lc1与电感Ls1、电感Lc2与电感Ls2之间的耦合系数为0.37。The differential inductance L d , differential inductance L c , source-level feedback inductance L s1 and source-level feedback inductance L s2 are all formed on the substrate, the differential inductance L d and L c both adopt a symmetrical differential structure and the inductance L c is formed on Directly below the inductance L d , the source feedback inductance L s1 and L s2 are symmetrically formed around the differential inductance L d , the coupling coefficient between the inductance L d1 and the inductance L c1 , the inductance L d2 and the inductance L c2 is 0.94, the inductance The coupling coefficient between L d1 and inductor L s1 , the inductor L d2 and inductor L s2 is 0.38, the coupling coefficient between inductor L c1 and inductor L s1 , inductor L c2 and inductor L s2 is 0.37.
本发明的优点及有益效果:与现有技术相比,本发明所提供的低相位噪声压控振荡器采用耦合电感电容谐振腔以提高谐振腔的有效品质因数。利用源级反馈电感与谐振腔电感之间的磁耦合作为反馈,提高负阻单元电路中MOS管的有效栅-源过驱动电压并增加谐振腔输出信号的振幅。负阻单元电路采用电流复用结构,去除传统负阻单元电路中的共模节点,从而消除传统结构中共模节点的二次谐波对相位噪声的恶化。因此,本发明可有效提高压控振荡器的相位噪声性能。Advantages and beneficial effects of the present invention: Compared with the prior art, the voltage-controlled oscillator with low phase noise provided by the present invention adopts a coupled inductor-capacitor resonant cavity to improve the effective quality factor of the resonant cavity. The magnetic coupling between the source-level feedback inductance and the resonant cavity inductance is used as feedback to increase the effective gate-source overdrive voltage of the MOS transistor in the negative resistance unit circuit and increase the amplitude of the output signal of the resonant cavity. The negative resistance unit circuit adopts a current multiplexing structure to remove the common mode node in the traditional negative resistance unit circuit, thereby eliminating the deterioration of the phase noise caused by the second harmonic of the common mode node in the traditional structure. Therefore, the invention can effectively improve the phase noise performance of the voltage-controlled oscillator.
附图说明Description of drawings
图1为本发明实施例的低相位噪声压控振荡器结构示意图;FIG. 1 is a schematic structural diagram of a low phase noise voltage-controlled oscillator according to an embodiment of the present invention;
图2为传统差分互补结构压控振荡器电路示意图;2 is a schematic diagram of a traditional differential complementary structure voltage-controlled oscillator circuit;
图3为本发明实施例的电感Ld、Lc、Ls1和Ls2布置方式的斜视图;3 is a perspective view of the arrangement of inductors L d , L c , L s1 and L s2 according to an embodiment of the present invention;
图4为本发明的低相位噪声压控振荡器和采用图2所示的压控振荡器在同样输出频率下相位噪声曲线对比示意图。FIG. 4 is a schematic diagram of comparing phase noise curves of the low phase noise voltage controlled oscillator of the present invention and the voltage controlled oscillator shown in FIG. 2 at the same output frequency.
具体实施方式Detailed ways
为了进一步说明本发明的优势所在以及具体采取的技术手段,以下结合各附图详细说明本发明的具体实施例。理解这些实施例仅用于说明本发明而不用于限制本发明的范围,在阅读了本发明之后,本领域技术人员对本发明的各种等价形式的修改均应落于本申请权利要求保护范围。In order to further illustrate the advantages of the present invention and the specific technical means adopted, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It is understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. After reading the present invention, those skilled in the art should fall within the protection scope of the claims of the present application to the amendments of various equivalent forms of the present invention .
参照图1,本发明低相位噪声压控振荡器,包括负阻电路模块、差分耦合电感电容谐振腔,其中:Referring to Fig. 1, the low-phase-noise voltage-controlled oscillator of the present invention includes a negative resistance circuit module and a differentially coupled inductor-capacitor resonant cavity, wherein:
负阻电路模块包括PMOS管Mp、NMOS管Mn,电源VDD串联源级反馈电感Ls1后连接PMOS管Mp的源极,NMOS管Mn的源极串联源级反馈电感Ls2后接地,源级反馈电感Ls1与源级反馈电感Ls2的电感值相等,PMOS管Mp的栅极连接NMOS管Mn的漏极作为输出端Vp,NMOS管Mn的栅极连接PMOS管Mp的漏极作为输出端Vn。The negative resistance circuit module includes PMOS transistor M p and NMOS transistor M n , the power supply VDD is connected in series with the source feedback inductance L s1 and then connected to the source of the PMOS transistor M p , and the source of the NMOS transistor M n is connected in series with the source feedback inductance L s2 and grounded , the inductance value of source feedback inductance L s1 and source feedback inductance L s2 is equal, the gate of PMOS transistor M p is connected to the drain of NMOS transistor M n as the output terminal V p , and the gate of NMOS transistor M n is connected to PMOS transistor The drain of M p serves as the output terminal V n .
差分耦合电感电容谐振腔包括差分电感Ld、差分电感Lc及两个可变电容Cv。其中:The differentially coupled inductor-capacitor resonant cavity includes a differential inductor L d , a differential inductor L c and two variable capacitors C v . in:
差分电感Ld由电感Ld1与电感Ld2串联组成,且电感Ld1与电感Ld2的电感值相等,电感Ld1与电感Ld2未连接在一起的一端分别与输出端Vp与输出端Vn连接。The differential inductance L d is composed of the inductance L d1 and the inductance L d2 connected in series, and the inductance values of the inductance L d1 and the inductance L d2 are equal . Vn connection.
差分电感Lc由电感Lc1与电感Lc2串联组成,且电感Lc1与电感Lc2的电感值相等,电感Lc1与电感Lc2对接端与直流偏置电压Vb相连。The differential inductance L c is composed of an inductance L c1 and an inductance L c2 connected in series, and the inductance values of the inductance L c1 and the inductance L c2 are equal, and the butt ends of the inductance L c1 and the inductance L c2 are connected to the DC bias voltage V b .
两个可变电容Cv背靠背对接,对接端与模拟调谐电压Vctrl相连,两个可变电容Cv未连接在一起的一端分别与电感Lc1与电感Lc2未连接在一起的一端连接。The two variable capacitors C v are connected back to back, the butt ends are connected to the analog tuning voltage V ctrl , and the unconnected ends of the two variable capacitors C v are respectively connected to the unconnected ends of the inductor L c1 and the inductor L c2 .
差分电感Lc形成于差分电感Ld的正下方;源级反馈电感Ls1与源级反馈电感Ls2对称形成于差分电感Ld的周围。The differential inductance L c is formed directly below the differential inductance L d ; the source feedback inductance L s1 and the source feedback inductance L s2 are symmetrically formed around the differential inductance L d .
谐振腔Q值的定义实质上为谐振腔所存储的能量与谐振腔损耗之间的比值,为提高谐振腔Q值,本发明采用两个差分电感Ld与Lc与两个可变电容Cv构成差分耦合电感电容谐振腔,且电感Ld与电感Lc具有耦合系数kdc。相对于图2所示传统压控振荡器结构中所采用的单电感电容谐振腔而言,耦合电感之间耦合效应的存在,使得耦合电感电容谐振腔在谐振频率处具有更多的磁场能量,相应具有较高Q值,从而提升相位噪声性能。The definition of resonant cavity Q value is the ratio between the stored energy of the resonant cavity and the resonant cavity loss in essence. In order to improve the resonant cavity Q value, the present invention adopts two differential inductances L d and L c and two variable capacitors C v constitutes a differentially coupled inductor-capacitor resonant cavity, and the inductor L d and the inductor L c have a coupling coefficient k dc . Compared with the single-inductor-capacitor resonant cavity used in the traditional voltage-controlled oscillator structure shown in Figure 2, the existence of the coupling effect between the coupled inductors makes the coupled-inductor-capacitor resonant cavity have more magnetic field energy at the resonance frequency, Correspondingly, it has a higher Q value, thereby improving the phase noise performance.
在本发明的一个实施例中,采用两个可变电容Cv作为模拟调谐部分。Lc中心抽头接直流偏置电压Vb用以给两个可变电容Cv提供合适的直流偏置,通过调节模拟调谐电压Vctrl从而改变接入到谐振腔的电容值,实现频率的细调。差分振荡信号从输出端Vp和输出端Vn输出。In one embodiment of the present invention, two variable capacitors C v are used as the analog tuning section. The center tap of L c is connected to the DC bias voltage V b to provide a suitable DC bias for the two variable capacitors C v . By adjusting the analog tuning voltage V ctrl , the capacitance value connected to the resonant cavity is changed to achieve fine frequency Tune. The differential oscillation signal is output from the output terminal V p and the output terminal V n .
在本发明中,负阻电路模块采用电流复用结构。采用一个NMOS管Mn与一个PMOS管Mp交叉耦合提供负阻,补充谐振腔的能量损耗。相对于传统的互补交叉耦合差分对管(图2),该结构仅需要一半的偏置电流就可以提供相同的负阻。此外,由于PMOS管与NMOS管在压控振荡器工作时同时导通或者关断,不存在传统结构中的共源节点,这使得其可以避免共源节点中的二次谐波频率对相位噪声所带来的影响。In the present invention, the negative resistance circuit module adopts a current multiplexing structure. An NMOS transistor Mn and a PMOS transistor Mp are used to cross-couple to provide negative resistance and supplement the energy loss of the resonant cavity. Compared with traditional complementary cross-coupled differential pair transistors (Figure 2), this structure requires only half the bias current to provide the same negative resistance. In addition, since the PMOS transistor and the NMOS transistor are turned on or off at the same time when the voltage-controlled oscillator is working, there is no common-source node in the traditional structure, which makes it possible to avoid the second harmonic frequency-to-phase noise in the common-source node the impact.
本发明引入源极反馈电感Ls1与Ls2。利用源极反馈电感Ls1、Ls2与谐振腔中电感Ld、Lc的磁耦合作为反馈,使NMOS管Mn与PMOS管Mp的漏极电压与源极电压同向变化,使得输出端Vp和输出端Vn输出信号振幅不受电源电压VDD和地电位钳制,在同等偏置条件下可获得更高的振荡信号幅度。The present invention introduces source feedback inductors L s1 and L s2 . Using the magnetic coupling between the source feedback inductance L s1 , L s2 and the inductance L d , L c in the resonant cavity as feedback, the drain voltage and the source voltage of the NMOS transistor M n and the PMOS transistor M p change in the same direction, so that the output The output signal amplitude of the terminal V p and the output terminal V n is not clamped by the power supply voltage VDD and the ground potential, and a higher oscillation signal amplitude can be obtained under the same bias condition.
本发明所给出的低相位噪声压控振荡器使用多个电感,这些电感需要很大的版图面积。图3示出了本发明的一个实例,形成于衬底上的电感Ld、Lc、Ls1和Ls2的斜视图。电感Ld和电感Lc均采用对称差分结构且电感Lc形成于电感Ld的正下方,以便重新使用同一版图面积,电感Ld和电感Lc的电感值均为1.0nH。电感Ls1与电感Ls2对称形成于电感Ld的外围,电感Ls1与电感Ls2的电感值均为0.2nH。电感Ld1与电感Lc1、电感Ld2与电感Lc2之间的耦合系数kdc约为0.94。电感Ld1与电感Ls1、电感Ld2与电感Ls2之间的耦合系数kds约为0.38,电感Lc1与电感Ls1、电感Lc2与电感Ls2之间的耦合系数kcs约为0.37。The low phase noise VCO provided by the present invention uses multiple inductors, and these inductors require a large layout area. Fig. 3 shows an example of the present invention, a perspective view of inductors L d , L c , L s1 and L s2 formed on the substrate. Both the inductor L d and the inductor L c adopt a symmetrical differential structure and the inductor L c is formed directly below the inductor L d so as to reuse the same layout area. The inductance values of the inductor L d and the inductor L c are both 1.0nH. The inductance L s1 and the inductance L s2 are symmetrically formed on the periphery of the inductance L d , and the inductance values of the inductance L s1 and the inductance L s2 are both 0.2nH. The coupling coefficient k dc between the inductor L d1 and the inductor L c1 , and between the inductor L d2 and the inductor L c2 is about 0.94. The coupling coefficient k ds between the inductance L d1 and the inductance L s1 , the inductance L d2 and the inductance L s2 is about 0.38, the coupling coefficient k cs between the inductance L c1 and the inductance L s1 , the inductance L c2 and the inductance L s2 is about 0.37.
图4所示为本发明的低相位噪声压控振荡器和采用图2所示的压控振荡器在同样输出频率下相位噪声曲线对比示意图。采用TSMC0.18-μm CMOS工艺,谐振频率均为12GHz,采用本发明结构,在功耗和输出频率均相同的条件下,相位噪声性能获得了极大的提升,在1MHz频偏处,相位噪声降低约8.8dB,在100kHz频偏处,相位噪声降低约13.2dB,这说明本发明结构能有效提升相位噪声性能。FIG. 4 is a schematic diagram showing the comparison of the phase noise curves of the low phase noise voltage-controlled oscillator of the present invention and the voltage-controlled oscillator shown in FIG. 2 at the same output frequency. Using TSMC0.18-μm CMOS technology, the resonant frequency is 12GHz. With the structure of the present invention, under the condition of the same power consumption and output frequency, the phase noise performance has been greatly improved. At 1MHz frequency deviation, the phase noise The reduction is about 8.8dB, and the phase noise is reduced by about 13.2dB at a frequency offset of 100kHz, which shows that the structure of the present invention can effectively improve the phase noise performance.
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US9385652B2 (en) * | 2014-10-29 | 2016-07-05 | Mediatek Singapore Pte. Ltd. | Cross-coupled oscillator, integrated circuit and electronic device |
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