CN204948436U

CN204948436U - A kind of adjusting control circuit

Info

Publication number: CN204948436U
Application number: CN201520668749.3U
Authority: CN
Inventors: 杨靖; 梅当民; 金学成
Original assignee: INTERNATIONAL GREEN CHIP (TIANJIN) CO Ltd
Current assignee: Howell Analog Integrated Circuit Beijing Co ltd
Priority date: 2015-08-31
Filing date: 2015-08-31
Publication date: 2016-01-06
Anticipated expiration: 2025-08-31

Abstract

The utility model relates to a kind of adjusting control circuit, and this circuit comprises: late release module (002), after delay scheduled time, described clamper module (003) is thoroughly closed; Clamper module (003), for by the node voltage clamper in described main amplifier module (001) at predetermined magnitude of voltage; Main amplifier module (001), for giving the charging of described work loop module (006); Maintain loop module (004), for maintaining the normal work of described main amplifier module (001); Shut-off circuit module (005), for completing LED output current from the normal process to closing; Work loop module (006), for completing LED output current from zero to normal process.The utility model can ensure that LED output current rises, fall time is all less, improves whole PWM dimming resolution, and ensure that LED output current does not have larger overshoot, improve the useful life of LED lamp bead.

Description

Dimming control circuit

Technical Field

The utility model relates to a LED drive circuit design field in a poor light especially relates to a dimming control circuit

Background

The LED backlight, which is used for the illumination of the liquid crystal display screen, is gradually replacing the conventional CCFL (cold cathode tube) backlight source due to its low power consumption, high adjustment ratio, fast response, long life, and the like. The LED driving circuit is a control circuit which can ensure constant current output of an LED, high dimming ratio and the like. At present, the domestic market of the products is basically occupied by foreign products, so that the research and design of the drive control circuit have practical significance for realizing the localization of the products and promoting the development of the industry.

With the development of electronic products, the dimming range of electronic display screens is required to be wider and wider, where the dimming refers to PWM (digital) dimming, and as shown in fig. 1, a PWM dimming timing diagram is shown, where PWM is a square wave signal input from the outside, and LED outputs a current waveform. In PWM dimming control, the amount of time TR represents the time required for the output current to transition from 0 to the target current, and the amount of time TF represents the time required for the output current to transition from the target current back to 0. In most cases, the lower the dimming frequency, the higher the contrast ratio, since these fixed delays will only occupy a small fraction of the dimming period. However, if the dimming frequency is too low, audio noise may be caused, which affects the application of electronic products, so that the dimming frequency is generally greater than 20KHz during normal use, the dimming ratio should be increased, and only the TR and TF times should be reduced as much as possible. The upper limit depends on the requirement of minimum contrast, which is generally expressed as the inverse of the minimum on-time.

Fig. 2 shows a conventional PWM dimming driving circuit, and fig. 2 shows two conventional PWM dimming control methods. In example 1, a PWM signal directly controls the operating state of an operational amplifier AMP, when PWM is "high", the AMP operates normally, the operational amplifier charges the gate of an adjusting tube N1, so that the whole loop is established, when AMP "positive" and "negative" input voltages are equal, the adjusting tube N1 reaches a normal set current, and an LED string is connected in series with the adjusting tube N1, so that the LED also reaches a required current; when the PWM is "low", the AMP is inactive, and the AMP output is pulled down to the "ground" potential, thereby turning off the regulator N1. Since the AMP has a limited driving capability, both TR and TF times of the output current are long. In example 2, in order to charge and discharge the gate of the regulating tube through the control switches S1 and S2, the TR and TF times can be made very small, but the AMP is separated from the whole acceleration loop, which causes a large overshoot of the LED output current and easily causes damage to the LED. Therefore, the dimming ratio of the backlight driving products in the market is small.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a dimming control circuit to the above-mentioned not enough that prior art exists. The utility model discloses need design PWM (digital) that has quick response and adjust luminance, can let LED output current from zero to normal to and all have faster response time from normal current to zero, can make PWM have great dimming ratio moreover, and can guarantee that LED output current overshoots the electric current less.

In order to achieve the above object, the present invention provides a dimming control circuit, which includes: a delay closing module 002 for completely closing the clamping module 003 after delaying for a predetermined time; the clamping module 003 is used for clamping the node voltage in the main operational amplifier module 001 to a preset voltage value; the main operational amplifier module 001 is used for charging the working loop module 006; a maintenance loop module 004 for maintaining the normal operation of the main operational amplifier module 001; a shutdown circuit module 005, configured to complete a process of turning off the LED output current from normal; and the work loop module 006 is used for completing the process of making the LED output current from zero to normal.

Preferably, the main operational amplifier module 001 and the working loop module 006 and the maintenance loop module 004 respectively form a feedback loop.

Preferably, the maintenance loop module 004 includes a second N-type MOS transistor N2, a third resistor R3, and a first control switch S1; the drain of the second N-type MOS transistor N2 is connected to an external input voltage source VN1, the gate thereof is connected to the output terminal of the main operational amplifier module 001, and the source thereof is connected to one end of the third resistor R3 and one end of the first control switch S1; the other end of the third resistor R3 is grounded GND; the other end of the first control switch S1 is connected to the negative input terminal of the main operational amplifier module 001.

Preferably, the shutdown circuit module 005 includes a third control switch S3, a fourth control switch S4, and a fourth resistor R4; one end of the fourth control switch S4 is connected to the output end of the main operational amplifier module 001, and the other end is connected to one end of the third control switch S3; the other end of the third control switch S3 is connected to one end of a fourth resistor R4; the other end of the fourth resistor R4 is connected to the ground GND.

Preferably, the work loop module 006 includes a first N-type MOS transistor N1, a second resistor R2, and a second control switch S2; the drain of the first N-type MOS transistor N1 is connected to the LED string to realize the series connection of the first N-type MOS transistor N1 and the LED, the gate thereof is connected to the connection point of the third control switch S3 and the fourth control switch S4 in the shutdown circuit module 005, and the source thereof is connected to one end of the second resistor R2 and one end of the second control switch S2; the other end of the second control switch S2 is connected to the negative input end of the main operational amplifier module 001; the other end of the second resistor R2 is connected to ground GND.

Preferably, in the main operational amplifier module 001, the main operational amplifier is a two-stage folded cascode operational amplifier, the frequency compensation mode of the main operational amplifier is miller compensation, and a gate of an input tube of the second-stage operational amplifier is connected to the output end of the clamping module 003.

Preferably, the delay shutdown module 002 includes a first inverter 021, a second inverter 022, a nand gate 023, a first D flip-flop 024, and a second D flip-flop 025; the PWM input signal is connected with the input end of a first inverter 021, and the output end of the first inverter 021 is connected with the input end of a second inverter 022; the output end of the second inverter 022 is connected to the data input D end of the first D flip-flop 024 and one end of the nand gate 023; the clock input CLK is connected to the CLK terminal of the first D flip-flop 024 and the second D flip-flop 025; the EN is the other end of the chip enable input connected with the NAND gate 023, and the output end of the NAND gate 023 is connected with the reset RSET ends of the first D flip-flop 024 and the second D flip-flop 025; the Q terminal of the first D flip-flop 024 is connected to the input D terminal of the second D flip-flop 025, and the Q terminal of the second D flip-flop 025 outputs the output of the delay shutdown module 002.

Preferably, the clamping module 003 includes a second P-type MOS transistor P2, a third P-type MOS transistor P3, and a fourth P-type MOS transistor P4; wherein, the source of the second P-type MOS transistor P2 is connected to the input power VDD, the gate thereof is connected to the output terminal of the delay shutdown module 002, the line name SHUT is defined herein, and the drain thereof is connected to the source of the third P-type MOS transistor P3; the gate drain of the third P-type MOS transistor P3 is connected with the source of the fourth P-type MOS transistor P4; the grid-drain short circuits of the fourth P-type MOS transistor P4 are used as the output end of the clamping module, and are defined as VPD; the VPD is connected to the gate of the eighth P-type MOS transistor P8 of the second-stage input transistor of the main operational amplifier module 001.

The utility model can ensure that the rising of the LED output current from zero to normal and the falling time from normal to zero are both small, and improve the whole PWM dimming resolution; the accelerating circuit is fused into the main operational amplifier control, so that the LED output current is prevented from being greatly overshot, and the service life of the LED lamp bead is prolonged.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of a PWM dimming timing sequence;

FIG. 2 is a prior art PWM dimming schematic;

fig. 3 is a schematic diagram of a dimming control circuit according to a first embodiment of the present invention;

fig. 4 is a schematic diagram of a dimming control circuit according to a second embodiment of the present invention;

fig. 5 is a schematic diagram of a main operational amplifier AMP1 according to a second embodiment of the present invention;

fig. 6 is a schematic diagram of a switching timing sequence of a dimming control circuit according to a second embodiment of the present invention;

fig. 7 is a schematic diagram of a delayed shutdown module according to a second embodiment of the present invention;

fig. 8 is a schematic diagram of a clamping module according to a second embodiment of the present invention;

fig. 9 is a timing diagram of a PWM delay shutdown module according to a second embodiment of the present invention;

fig. 10 is a schematic diagram of a PWM dimming operation flow provided by the second embodiment of the present invention;

fig. 11 is a schematic diagram of a method of a dimming control circuit according to a third embodiment of the present invention.

Detailed Description

The technical solution of the present invention is further described in detail by the accompanying drawings and examples.

Fig. 3 is a schematic diagram of a dimming control circuit according to a first embodiment of the present invention. A dimming control circuit as shown in fig. 3, the circuit comprising: a main operational amplifier module 001, a delay shutdown module 002, a clamp module 003, a maintenance loop module 004, a shutdown circuit module 005, and a working loop module 006; the delayed closing module 002 is used for completely closing the clamping module 003 after delaying for a preset time; the clamping module 003 is used for clamping the node voltage in the main operational amplifier module 001 to a preset voltage value; the main operational amplifier module 001 is used for charging the working loop module 006; a maintenance loop module 004 for maintaining the normal operation of the main operational amplifier module 001; a shutdown circuit module 005, configured to complete a process of turning off the LED output current from normal; and the work loop module 006 is used for completing the process of making the LED output current from zero to normal.

According to the embodiment, the rising time of the LED output current from zero to normal and the falling time from normal to zero are ensured to be shorter, and the whole PWM dimming resolution is improved; the accelerating circuit is fused into the main operational amplifier control, so that the LED output current is prevented from being greatly overshot, and the service life of the LED lamp bead is prolonged.

Fig. 4 is a schematic diagram of a dimming control circuit according to a second embodiment of the present invention. As shown in fig. 4, the circuit includes a main operational amplifier module 001, a delay shutdown module 002, a clamp module 003, a sustain loop module 004, a shutdown circuit module 005, and an operating loop module 006.

Specifically, as a preferred solution of this embodiment, the maintenance loop module 004 includes a second N-type MOS transistor N2, a third resistor R3, and a first control switch S1; the drain of the second N-type MOS transistor N2 is connected to an external input voltage source VN1, the gate thereof is connected to the output terminal of the main operational amplifier module 001, and the source thereof is connected to one end of the third resistor R3 and one end of the first control switch S1; the other end of the third resistor R3 is grounded GND; the other end of the first control switch S1 is connected to the negative input terminal of the main operational amplifier module 001.

Specifically, as a preferable solution of the present embodiment, the shutdown circuit module 005 includes a third control switch S3, a fourth control switch S4, and a fourth resistor R4; one end of the fourth control switch S4 is connected to the output end of the main operational amplifier module 001, and the other end is connected to one end of the third control switch S3; the other end of the third control switch S3 is connected to one end of a fourth resistor R4; the other end of the fourth resistor R4 is connected to the ground GND.

Specifically, as a preferred solution of this embodiment, the work loop module 006 includes a first N-type MOS transistor N1, a second resistor R2, and a second control switch S2; the drain of the first N-type MOS transistor N1 is connected to the LED string to realize the series connection of the first N-type MOS transistor N1 and the LED, the gate thereof is connected to the connection point of the third control switch S3 and the fourth control switch S4 in the shutdown circuit module 005, and the source thereof is connected to one end of the second resistor R2 and one end of the second control switch S2; the other end of the second control switch S2 is connected to the negative input end of the main operational amplifier module 001; the other end of the second resistor R2 is connected to ground GND.

The PWM dimming working process comprises the following steps: PWM is a square wave signal externally input to the driving circuit, and the PWM dimming acceleration module controls the switches S1, S2, S3, and S4, and the relationship between the switching timing and the PWM can be seen in fig. 6 (a schematic diagram of the switching timing of the dimming control circuit). When the PWM signal changes from "low" to "high", the switches S2, S4 are turned on, and the switches S1, S3 are turned off. At this time, the working loop module 006 and the main operational amplifier module 001 form a feedback loop, and since the LED output current is "zero", and the negative terminal input voltage of the main operational amplifier module AMP1 approaches zero, the main operational amplifier will pull the voltage of the gate VPD node of the second stage input tube P8 to "ground", but due to the action of the clamping module 003, VPD will not drop too low, but will clamp the voltage of the relative power source (BIASP 1-bian 2-bian 1-BIASP2), such voltage will make the second stage input tube P8 in the resistance region, the gate capacitance of the adjusting tube N1 is charged by the second stage input tube P8, since the designed second stage input tube P8 is in the resistance region, its equivalent resistance is small, the gate voltage of the adjusting tube N1 can be charged in a short time, when the gate of the adjusting tube N1 is charged to a certain degree, the adjusting tube N1 is turned on and appears a current, as the current of the regulating tube N1 increases, a voltage appears on the resistor R2, and the main operational amplifier AMP1 starts to enter the amplifier region to work. Since the gate-source voltage of the second-stage input tube P8 is initially clamped to (BIASP 1-bian 2-bian 1-BIASP2) voltage, and the gate-source voltage of the second-stage input tube P8 entering a saturation region is much smaller than the voltage value, the clamping effect of the clamping module on the gate-source voltage of the second-stage input tube P8 is gradually weakened along with the normal operation of the main operational amplifier module 001, so that the second-stage input tube P8 is automatically separated from a resistance region, the charging pull-up effect is weakened, and the phenomenon that the gate of the adjusting tube N1 is excessively charged to cause the overshoot of the large output current of the LED is avoided. The delay closing module 002 delays the rising edge of the PWM signal for a predetermined time, and after the predetermined time, the delay closing module 002 completely closes the clamp module 003, so as to avoid the clamp module 003 from causing a maladjustment effect on the system, and thus, the acceleration process of the current from zero to normal is completed.

When the PWM signal is low, the control switches S2, S4 are open, and the control switches S1, S3 are closed. The loop formed by the maintaining loop module 004 and the main operational amplifier module 001 maintains the normal operation of the main operational amplifier module AMP1, so that the main operational amplifier module AMP1 can operate in a fast response when the next PWM signal comes. The turning off of the LED output current is completed by the turn-off circuit module 005. After the control switch S3 in the shutdown circuit module 005 is closed, the gate capacitance of the adjusting tube N1 is discharged through the resistor R4, so as to turn off the adjusting tube N1, thereby completing the process from normal to shutdown of the LED current.

The delayed shutdown module 002 operation: when the EN or PWM signal is "low", the output of the nand gate 023 is "high", the D flip-flops 024 and 025 are in a reset state, and the output of the Q terminal is "low"; when the EN is high, the chip starts to work normally, and after the PWM signal changes from low to high, the Q terminal of the D flip-flop 025 is enabled to output high by 1 to 2 CLK clocks, and the clamp module is turned off, which is equivalent to that the clamp module can work normally for 1 to 2 CLK clock cycles. The timing variation can be seen in fig. 9(PWM delay off module timing diagram).

Fig. 5 is a schematic diagram of a main operational amplifier AMP1 according to an embodiment of the present invention. As shown in fig. 5, the main operational amplifier module 001 is a conventional two-stage folded cascode operational amplifier, and its frequency compensation is miller compensation, and is mainly characterized in that the gate of the input P8 of the second-stage operational amplifier is connected to the output of the clamping module 003, and the gate line name of the input P8 of the second-stage operational amplifier is VPD.

Fig. 7 is a schematic diagram of a delayed shutdown module according to a second embodiment of the present invention. As shown in fig. 7, the delay locking module 002 includes a first inverter 021, a second inverter 022, a nand gate 023, a first D flip-flop 024, and a second D flip-flop 025.

Specifically, as a preferred solution of the present embodiment, the delay shutdown module 002 includes a first inverter 021, a second inverter 022, a nand gate 023, a first D flip-flop 024, and a second D flip-flop 025; the PWM input signal is connected with the input end of a first inverter 021, and the output end of the first inverter 021 is connected with the input end of a second inverter 022; the output end of the second inverter 022 is connected to the data input D end of the first D flip-flop 024 and one end of the nand gate 023; the clock input CLK is connected to the CLK terminal of the first D flip-flop 024 and the second D flip-flop 025; the EN is the other end of the chip enable input connected with the NAND gate 023, and the output end of the NAND gate 023 is connected with the reset RSET ends of the first D flip-flop 024 and the second D flip-flop 025; the Q terminal of the first D flip-flop 024 is connected to the input D terminal of the second D flip-flop 025, and the Q terminal of the second D flip-flop 025 outputs the output of the delay shutdown module 002.

Fig. 8 is a schematic diagram of a clamping module according to a second embodiment of the present invention. As shown in fig. 8, the clamping module 003 includes a second P-type MOS transistor P2, a third P-type MOS transistor P3, and a fourth P-type MOS transistor P4.

Specifically, as a preferred solution of this embodiment, the source of the second P-type MOS transistor P2 is connected to the input power VDD, the gate thereof is connected to the output terminal of the delay shutdown module 002, a line name SHUT is defined herein, and the drain thereof is connected to the source of the third P-type MOS transistor P3; the gate drain of the third P-type MOS transistor P3 is connected with the source of the fourth P-type MOS transistor P4; the grid-drain short circuits of the fourth P-type MOS transistor P4 are used as the output end of the clamping module, and are defined as VPD; the VPD is connected to the gate of the eighth P-type MOS transistor P8 of the second-stage input transistor of the main operational amplifier module 001.

Fig. 10 is a schematic diagram of a PWM dimming operation flow provided by the second embodiment of the present invention. The PWM dimming as described in fig. 10 specifically includes the following steps:

step S101, when the PWM signal changes from low to high, the switches S2 and S4 are switched on, and the switches S1 and S3 are switched off; at this time, the working loop module 006 and the main operational amplifier module 001 form a feedback loop, and at this time, since the LED output current is zero, the input voltage at the negative terminal of the main operational amplifier AMP1 approaches zero, so that the main operational amplifier pulls the voltage at the gate VPD node of the input tube P8 of the second-stage operational amplifier to the ground potential;

step S102, due to the action of the clamping module 003, VPD does not drop too low, but clamps the voltage of a relative power supply (BIASP1-BIASN2-BIASN1-BIASP2), and the voltage can enable the input tube P8 of the second-stage operational amplifier to be in a resistance region, and the input tube P8 of the second-stage operational amplifier charges the gate capacitance of the adjusting tube N1;

step S103, because the equivalent resistance of the designed input tube P8 of the second-stage operational amplifier is smaller in the resistance region, the gate voltage of the adjusting tube N1 can be charged high in a short time, when the gate of the adjusting tube N1 is charged to a certain degree, the adjusting tube N1 is conducted and current appears, and as the current of the adjusting tube N1 increases, the voltage appears on the resistor R2, the main operational amplifier AMP1 starts to enter the amplifier region to work;

step S104, since the gate voltage of the input tube P8 of the second-stage operational amplifier is initially clamped to (BIASP1-BIASN2-BIASN1-BIASP2) voltage, and after the input tube P8 of the second-stage operational amplifier enters a saturation region, the gate voltage of the input tube P8 of the second-stage operational amplifier is far smaller than the voltage value, the clamping effect of the clamping module on the gate voltage of the input tube P8 of the second-stage operational amplifier can be gradually weakened along with the normal work of the main operational amplifier module 001, so that the input tube P8 of the second-stage operational amplifier is automatically separated from a resistance region, the charging pull-up effect is weakened, and the phenomenon that the gate of the adjusting tube N1 is charged too high to cause the overshoot of the;

step S105, the delay closing module delays the rising edge of the PWM signal for a certain time, and after a set time, the delay closing module 002 completely closes the clamping module 003 to avoid the clamping module 003 from causing maladjustment influence on the system, so that the acceleration process of the current from zero to normal is completed;

specifically, when the EN or PWM signal is "low", the output of the nand gate 023 is "high", the D flip-flops 024 and 025 are in a reset state, the output of the Q terminal is "low", when the EN is "high", the chip starts to operate normally, after the PWM signal changes from "low" to "high", the output of the Q terminal of the D flip-flop 025 is "high" through 1 to 2 CLK clocks, and the clamp module path is closed, which is equivalent to that the clamp module can operate normally for 1 to 2 CLK clock cycles;

specifically, when the PWM signal is input to the delay shutdown unit, it is uncertain whether the PWM signal is "high" or "low", and when the PWM signal is input to the delay shutdown unit, the output of the Q terminal of the D flip-flop 025 is "high" through 1 to 2 CLK clocks, that is, the defined SHUT is at "high", and the clamp module path is SHUT down, as shown in the timing diagram of the PWM delay shutdown module provided in the second embodiment of the present invention in fig. 9;

step S106, after the PWM signal changes from high to low, the control switches S2 and S4 are switched off, and S1 and S3 are switched on;

in step S107, the loop formed by the maintaining loop module 004 and the main operational amplifier module 001 maintains the normal operation of the main operational amplifier AMP1, so that the AMP1 can operate in a fast response when the next PWM signal comes. The turning off of the LED output current is completed by the turn-off circuit module 005;

step S108, after the control switch S3 in the shutdown circuit module 005 is closed, the gate capacitor of the adjusting transistor N1 is discharged through the resistor R4;

in step S109, a segment of the resistor R4 is grounded, and the discharge time through the resistor R4 is short, so that the adjusting tube N1 is turned off, and the process from normal to off of the LED current is completed.

Therefore, the embodiment can ensure that the rising time of the LED output current from zero to normal and the falling time from normal to zero are both small, and the whole PWM dimming resolution is improved; the accelerating circuit is fused into the main operational amplifier control, so that the LED output current is prevented from being greatly overshot, and the service life of the LED lamp bead is prolonged.

Fig. 11 is a schematic diagram of a method of a dimming control circuit according to a third embodiment of the present invention. As shown in fig. 11, the method of the dimming control circuit includes steps S111-S116:

in step S111, clamping the node voltage in the main operational amplifier module AMP1 at a predetermined voltage value according to an input PWM signal;

in step S112, according to the node voltage after the clamping, the main operational amplifier module AMP1 charges the working loop module;

in step S113, after the working loop module is charged, the process of changing the LED output current from zero to normal is completed;

in step S114, when the LED output current is normal, after a predetermined time delay, the clamping function is completely turned off;

in step S115, according to the input PWM signal, the normal operation of the main operational amplifier module AMP1 is maintained;

in step S116, while the main operational amplifier module AMP1 operates normally, the process of turning off the LED output current from normal acceleration is completed.

Preferably, as a possible implementation manner of this example, the step of clamping the node voltage in the main operational amplifier module AMP1 at a predetermined voltage value according to the input PWM signal includes: when the input PWM signal is high, the grid-source voltage of the second input tube of the main operational amplifier module AMP1 is constant in the acceleration stage and is not influenced by changes of the input power supply VDD and the like.

Preferably, as a possible implementation manner of this example, the step of charging, by the main AMP1, the working loop module according to the clamped node voltage includes: the grid source voltage of the second-stage input tube of the main operational amplifier module AMP1 is controlled by the clamped grid electrode VPD node voltage in the PWM dimming conversion process.

Preferably, as a possible implementation manner of this example, after the working loop is charged, voltages of positive and negative input terminals of the main operational amplifier are guaranteed to be equal; when the LED output current is normal, the clamping effect on the voltage of the grid node of the second-stage input tube P8 is weakened, and the clamping effect is completely closed after delay.

Preferably, as a possible implementation manner of this example, the step of maintaining the normal operation of the main operational amplifier module AMP1 according to the input PWM signal includes: when the output current of the LED is turned off by PWM dimming, the normal operation of the main operational amplifier module AMP1 can be maintained, and the main operational amplifier module AMP1 is prevented from deviating from the operation state too much.

The above-mentioned embodiments, further detailed description of the objects, technical solutions and beneficial results of the present invention, it should be understood that the above description is only a detailed description of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A dimming control circuit, the circuit comprising: the circuit comprises a main operational amplifier module (001), a delay shutdown module (002), a clamping module (003), a maintenance loop module (004), a shutdown circuit module (005) and a working loop module (006); the delay shutdown module (002) is connected with the clamping module (003), the clamping module (003) is connected with the main operational amplifier module (001), the shutdown circuit module (005), the maintenance loop module (004) and the main operational amplifier module (001) form a loop, and the shutdown circuit module (005), the working loop module (006) and the main operational amplifier module (001) form a loop; wherein,

a delay turn-off module (002) for completely turning off the clamp module (003) after delaying for a predetermined time;

a clamping module (003) for clamping a node voltage in the main operational amplifier module (001) to a predetermined voltage value;

a main operational amplifier module (001) for charging the working loop module (006);

a maintenance loop module (004) for maintaining normal operation of the main operational amplifier module (001);

a shutdown circuit module (005) for completing the process of turning off the LED output current from normal;

and the work loop module (006) is used for completing the process of enabling the LED output current to be from zero to normal.

2. The circuit of claim 1, wherein the main operational amplifier module (001) forms a feedback loop with the operating loop module (006) and the maintenance loop module (004), respectively.

3. A circuit according to claim 1 or 2, wherein:

the maintaining loop module (004) comprises a second N-type MOS tube (N2), a third resistor (R3) and a first control switch (S1); wherein,

the drain electrode of the second N-type MOS tube (N2) is connected with an external input voltage source (VN1), the grid electrode of the second N-type MOS tube is connected with the output end of the main operational amplifier module (001), and the source electrode of the second N-type MOS tube is connected with one end of a third resistor (R3) and one end of a first control switch (S1); the other end of the third resistor (R3) is Grounded (GND); the other end of the first control switch (S1) is connected with the negative input end of the main operational amplifier module (001);

the shutdown circuit module (005) includes a third control switch (S3), a fourth control switch (S4), and a fourth resistor (R4); wherein,

one end of the fourth control switch (S4) is connected with the output end of the main operational amplifier module (001), and the other end is connected with one end of the third control switch (S3); the other end of the third control switch (S3) is connected to one end of a fourth resistor (R4); the other end of the fourth resistor (R4) is Grounded (GND);

the working loop module (006) comprises a first N-type MOS (metal oxide semiconductor) transistor (N1), a second resistor (R2) and a second control switch (S2); wherein,

the drain electrode of the first N-type MOS tube (N1) is connected with the LED string to realize the series connection of the first N-type MOS tube (N1) and the LED, the grid electrode of the first N-type MOS tube is connected with the connection point of a third control switch (S3) and a fourth control switch (S4) in the turn-off circuit module (005), and the source electrode of the first N-type MOS tube is connected with one end of a second resistor (R2) and one end of a second control switch (S2); the other end of the second control switch (S2) is connected with the negative input end of the main operational amplifier module (001); the other end of the second resistor (R2) is Grounded (GND).

4. The circuit of claim 1 or 2, wherein:

and the main operational amplifier is a two-stage folded cascode operational amplifier, the frequency compensation mode of the main operational amplifier is Miller compensation, and the grid electrode of an input tube of the second-stage operational amplifier is connected with the output end of the clamping module (003).

5. The circuit of claim 1 or 2, wherein:

the delay shutdown module (002) comprises a first inverter (021), a second inverter (022), a nand gate (023), a first D flip-flop (024), and a second D flip-flop (025); wherein,

the PWM input signal is connected with the input end of a first inverter (021), and the output end of the first inverter (021) is connected with the input end of a second inverter (022); the output end of the second inverter (022) is connected with the data input D end of the first D flip-flop (024) and one end of the NAND gate (023); the clock input CLK is connected with the CLK terminal of the first D flip-flop (024) and the second D flip-flop (025); EN is the other end of the chip enable input connected with the NAND gate (023), and the output end of the NAND gate (023) is connected with the reset RSET ends of the first D flip-flop (024) and the second D flip-flop (025); the Q end of the first D flip-flop (024) is connected with the input D end of the second D flip-flop (025), and the Q end of the second D flip-flop (025) outputs the output of the delay closing module (002);

the clamping module (003) comprises a second P-type MOS transistor (P2), a third P-type MOS transistor (P3) and a fourth P-type MOS transistor (P4); wherein,

the source of the second P-type MOS transistor (P2) is connected to the input power (VDD), the gate thereof is connected to the output terminal of the delay turn-off module (002), the line name SHUT is defined herein, and the drain thereof is connected to the source of the third P-type MOS transistor (P3); the gate drain of the third P-type MOS transistor (P3) is connected with the source of the fourth P-type MOS transistor (P4); the grid-drain short circuit of a fourth P type MOS (P4) transistor is used as the output end of the clamping module, and is defined as VPD; the VPD is connected with the grid electrode of an eighth P-type MOS (P8) of a second-stage input tube of the main operational amplifier module (001).