JP4473662B2 - Power-on reset circuit and power-on reset method - Google Patents

Description

  The present invention relates to a power-on reset circuit and a power-on reset method using a semiconductor integrated circuit.

  The conventional power-on reset circuit controls the potential of the liquid crystal drive output terminal to a low level until a predetermined time elapses after the power is turned on, and the shift register signal in the integrated circuit is also set so that the liquid crystal drive output terminal is at a low level. , Was fixed at a predetermined potential.

  As described above, after a predetermined time elapses after the power is turned on, a start signal is input to the shift register, and a predetermined liquid crystal driving voltage is sequentially applied to the liquid crystal driving output terminals.

For example, in a conventional power-on reset circuit, the potential of the output stage of the shift register is controlled to a low level until a predetermined time elapses after the power is turned on, a start signal is propagated to a plurality of shift registers, Can be stably output to the output terminal, the malfunction of the vertical and horizontal shift registers connected to the previous stage of the driven device can be prevented, and the output signals of the vertical and horizontal shift registers can be prevented from changing all at once. The generation of excessive current was prevented (see Patent Document 1).
JP 2003-346492 A (column 9, FIG. 1)

  The present invention provides a power-on reset circuit and a power-on reset method for causing a power-on reset circuit to detect a power-on sequence and stably outputting a reset signal to an output terminal.

One embodiment of the present invention is a power-on reset circuit in which a high-level logic power supply voltage generated by a logic power supply circuit and a high-level power supply voltage generated by a power supply circuit provided separately from the logic power supply circuit are supplied from the outside. A first conductivity type channel having a first control electrode that is electrically connected between a high-level logic power supply and an output terminal and has a first control electrode connected to a high-level power supply that rises later than a voltage rise of the high-level logic power supply upon power-on. A second conductivity type having a second control electrode connected in series with the first MIS transistor and the first MIS transistor at the output terminal, electrically connected between the output terminal and the low level logic power supply, and connected to the high level power supply A second MIS transistor of the channel, and the first MIS transistor is turned on in response to a voltage increase of the high-level logic power To transition, and summarized in that a power-on reset circuit for supplying a reset signal to the output terminal from the higher logic supply.

One embodiment of the present invention is based on a power-on reset circuit in which a high-level power supply voltage generated by a logic power supply circuit and a high-level power supply voltage generated by a power supply circuit provided separately from the logic power supply circuit are supplied from the outside. A power-on reset method in which a first MIS transistor of a first conductivity type channel is changed to a conductive state in response to a voltage increase of a high-level logic power supply due to power-on, and a reset signal is supplied from the high-level logic power supply to an output terminal When the steps of shifting the voltage of the higher power supply to rise slower than the voltage of the high logic power to the cutoff state a 1MIS transistor is detected by the control electrode of the first 1MIS transistor, the voltage of the higher power supply from power, at the output terminal of the second conductivity type channel connected first MIS transistor in series with the 2MIS While detecting with the second control electrode of the transistor, the second MIS transistor is transitioned to the conductive state at the stage of maintaining the cutoff state of the second MIS transistor until it rises to the threshold voltage and when the voltage of the high power supply reaches the threshold voltage. And a step of drawing a reset signal from the output terminal to the low-order logic power source.

  According to the present invention, it is possible to provide a power-on reset circuit and a power-on reset method that cause a power-on reset circuit to detect a power-on sequence and stably output a reset signal to an output terminal.

  Next, first to second embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals.

  The first to second embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is The material, shape, structure, arrangement, etc. are not specified below. The technical idea of the present invention can be variously modified within the scope of the claims.

(First embodiment)
The power-on reset circuit according to the first embodiment of the present invention is electrically connected between the high-level logic power supply 10 and the output terminal 11 as shown in FIG. Electrically between the first MIS transistor P01 of the first conductivity type channel (p-channel) having the first control electrode 13 connected to the high-level power supply 14 that rises later than the voltage rise, and between the output terminal 11 and the low-level logic power supply 15 And a second MIS transistor N01 of a second conductivity type channel (n-channel) having a second control electrode 16 connected to the high level power supply 14, and in response to a voltage rise of the high level logic power supply 10, the first MIS transistor P01 is changed to a conductive state, and a reset signal is supplied from the high-level logic power supply 10 to the output terminal 11.

  The high-level power supply 14 is generated by a DC / DC converter (not shown) provided separately from the logic power supply circuit that generates the high-level logic power supply 10. In this case, the high-level power supply 14 rises with a delay from the high-level logic power supply 10 due to the coupling effect due to the internal parasitic capacitance of the DC / DC converter and the Vf effect due to the parasitic diode (so-called Vf drop phenomenon of the power supply). In other words, the first embodiment uses the characteristic that the high-level power supply 14 starts up later than the high-level logic power supply 10 due to the time constant of the power supply circuit.

  The “MIS transistor” used in the first embodiment is intended for a switching element having a metal, insulator, or semiconductor structure, and includes, for example, a MOS transistor having a metal, oxide, or semiconductor structure.

  Here, the “higher-level logic power supply” targets, for example, a power supply potential VDD of 3 V in a MOS logic circuit. In addition, the “low-order logic power supply” targets a reference potential GND of 0 V in the MOS logic circuit. Further, the “high potential power source” targets a driving potential VGG of 5 to 20 V that is a positive potential with respect to the reference potential GND applied to the liquid crystal substrate electrode of the liquid crystal display device.

  Note that the reference potential GND, the power supply potential VDD, the drive potential VGG, and the negative drive potential VEE are supplied from the outside of the power-on reset circuit.

  In the power-on sequence, as shown in the “power-on sequence” in the upper part of FIG. 5, first, the reference potential GND of the low-level logic power source 15 is stabilized at the logic power source “L”, and then the power source potential of the high-level logic power source 10. The VDD is stabilized at the logic power supply “H”, the drive potential VGG of the high potential power supply 14 is subsequently stabilized at the liquid crystal power supply “H”, and the negative drive potential VEE is the low potential power supply of the liquid crystal power supply “L”. Stable at a negative potential of 10 to 20 V with respect to GND.

  In the first embodiment, the first control electrode 13 of the first MIS transistor P01 and the second control electrode 16 of the second MIS transistor N01 are commonly connected to the high-level power supply 14.

In addition, the first MIS transistor P01 is changed to the cut-off state by detecting the voltage rise of the high-level power supply 14, and the second MIS transistor N01 is changed to the conductive state when the voltage of the high-level power supply 14 reaches the threshold voltage, and a reset signal is output. The first and second MIS transistors P01 and N01 configured to be pulled out from the terminal 11 to the low-level logic power supply 15 detect the potential of the high-level power supply 14, operate in a complementary manner, and generate a reset signal at the output terminal 11.

  FIG. 2 is a block diagram in which the power-on reset circuit according to the first embodiment is applied to the scanning line driving circuit of the liquid crystal display device. The power-on reset circuit 18 is connected to the plurality of shift registers 21a to 21c.

  The shift register 21a is connected to the next level conversion circuit 22a, the inverter 23a is connected to the next stage of the level conversion circuit 22a, the first conductivity type (p-channel) MIS transistor P02 and the second stage are connected to the next stage of the inverter 23a. A liquid crystal driving circuit composed of a conductive type (n-channel) MIS transistor N02 is connected, and one of the driving potentials VGG and VEE is output to the liquid crystal output pad 24a (abbreviated as “G1” in the figure).

  Here, the “level conversion circuit” may be a DC / DC converter that boosts and lowers the logic level potential to a driving potential capable of driving the liquid crystal display device.

  Further, in the liquid crystal driving circuit, for example, when the output of the inverter 23a is a high level potential, the first conductivity type (p channel) MIS transistor P02 is turned off, and the second conductivity type (n channel) MIS transistor N02. Is turned on, and the drive potential VEE is output to the liquid crystal output pad 24a.

  In the liquid crystal driving circuit, for example, when the output of the inverter 23a is a low level potential, the first conductivity type (p channel) MIS transistor P02 is turned on and the second conductivity type (n channel) MIS transistor N02 is turned off. Then, the drive potential VGG is output from the liquid crystal output circuit including the first and second MIS transistors P02 and N02 to the liquid crystal output pad 24a (abbreviated as “G1” in the drawing).

  Therefore, the liquid crystal driving circuit outputs one of the driving potentials VGG and VEE corresponding to the output of the inverter 23a.

  Similarly, in the liquid crystal driving circuit, the shift register 21b is connected to the next level conversion circuit 22b, the inverter 23b is connected to the next stage of the level conversion circuit 22b, and the first conductivity type (p-channel) is connected to the next stage of the inverter 23b. ) And the second conductivity type (n-channel) MIS transistor N03 are connected, and the drive potential VGG or VEE is applied to the liquid crystal output pad 24b (abbreviated as “G2” in the figure). One voltage is output.

  Similarly, in the liquid crystal driving circuit, the shift register 21c is connected to the next level conversion circuit 22c, the inverter 23c is connected to the next stage of the level conversion circuit 22c, and the first conductivity type (p-channel) is connected to the next stage of the inverter 23c. ) And the second conductivity type (n-channel) MIS transistor N04 are connected, and the drive potential VGG or VEE is applied to the liquid crystal output pad 24c (abbreviated as “G3” in the figure). One voltage is output.

  The shift registers 21a to 21c are commonly connected to the clock signal line 20, and input / output data in synchronization with the vertical shift clock signal CK.

  The shift register 21a is provided at the first stage in the figure, and outputs the vertical shift data fetched from the serial input terminal Sin as a serial output signal SRO1 to the input terminal IN of the level conversion circuit 22a through the serial output terminal Sout. The serial output signal SRO1 is transferred to the serial input terminal Sin of the shift register 21b at the next stage.

  The shift register 21b is provided at the second stage in the figure, and outputs the vertical shift data fetched from the serial input terminal Sin as a serial output signal SRO2 to the input terminal IN of the level conversion circuit 22b through the serial output terminal Sout. The serial output signal SRO2 is transferred to the serial input terminal Sin of the shift register 21c at the next stage.

  The shift register 21c is provided at the third stage in the figure, and outputs the vertical shift data fetched from the serial input terminal Sin as a serial output signal SRO3 to the input terminal IN of the level conversion circuit 22c through the serial output terminal Sout.

  The level conversion circuit 22a is connected to the output of the shift register 21a and outputs the serial output signal SRO1 input from the input terminal IN to the inverter 23a of the next stage through the output terminal OUT.

  The level conversion circuit 22b is connected to the output of the shift register 21b, and outputs the serial output signal SRO2 input from the input terminal IN to the inverter 23b of the next stage through the output terminal OUT.

  The level conversion circuit 22c is connected to the output of the shift register 21c, and outputs the serial output signal SRO3 input from the input terminal IN to the next stage inverter 23c through the output terminal OUT.

  The inverter 23a outputs OUT of the level conversion circuit 22a to a liquid crystal output circuit connected to the next stage, and outputs a voltage of either the drive potential VGG or VEE to the liquid crystal output pad 24a of each liquid crystal output circuit.

  The inverter 23b outputs OUT of the level conversion circuit 22b to a liquid crystal output circuit connected to the next stage, and outputs one of the driving potentials VGG and VEE to the liquid crystal output pad 24b of each liquid crystal output circuit.

  The inverter 23c outputs OUT of the level conversion circuit 22c to a liquid crystal output circuit connected to the next stage, and outputs either one of the drive potential VGG or VEE to the liquid crystal output pad 24c of each liquid crystal output circuit.

  The operation of the liquid crystal drive circuit to which the power-on reset circuit according to the first embodiment is applied will be described with reference to FIGS.

  The power-on reset circuit 18 supplies a reset signal to the plurality of shift registers 21a to 21c at the time of power-on.

  The shift registers 21a to 21c transfer the vertical shift data DI in synchronization with the vertical shift clock signal CK having a predetermined cycle supplied from the clock signal line 20 when the reset signal is released after a predetermined time has elapsed since power-on. .

  For example, the first-stage shift register 21a receives the vertical shift data DI at the serial input terminal Sin, and outputs the serial output signal SRO1 to the output terminal OUT at time t1 in synchronization with the vertical shift clock signal CK.

  Based on the serial output signal SRO1, the shift register 21a transits the potential of the liquid crystal output pad 24a from the negative drive potential VEE to the positive drive potential VGG via the level conversion circuit 22a, the inverter 23a, and the liquid crystal drive circuit. Let

  The shift register 21a causes the serial output signal SRO1 of the output terminal OUT to fall at time t2 in synchronization with the vertical shift clock signal CK, and the potential of the liquid crystal output pad 24a is changed from the positive drive potential VGG to the negative drive potential VEE. Transition.

  For example, the second-stage shift register 21b receives the serial output signal SRO1 to the serial input terminal Sin, and outputs the serial output signal SRO2 to the output terminal OUT at time t2 in synchronization with the vertical shift clock signal CK.

  Based on the serial output signal SRO2, the shift register 21b transits the potential of the liquid crystal output pad 24b from the negative drive potential VEE to the positive drive potential VGG via the level conversion circuit 22b, the inverter 23b, and the liquid crystal drive circuit. Let

  The shift register 21b causes the serial output signal SRO2 of the output terminal OUT to fall at time t3 in synchronization with the vertical shift clock signal CK, and the potential of the liquid crystal output pad 24b is changed from the positive drive potential VGG to the negative drive potential VEE. Transition.

  For example, the third-stage shift register 21c receives the serial output signal SRO2 at the serial input terminal Sin, and outputs the serial output signal SRO3 to the output terminal OUT at time t3 in synchronization with the vertical shift clock signal CK.

  Based on the serial output signal SRO3, the shift register 21c causes the potential of the liquid crystal output pad 24c to transition from the negative drive potential VEE to the positive drive potential VGG via the level conversion circuit 22c, the inverter 23c, and the liquid crystal drive circuit. .

  The shift register 21c causes the serial output signal SRO3 at the output terminal OUT to fall in synchronization with the vertical shift clock signal CK, and transitions the potential of the liquid crystal output pad 24c from the positive drive potential VGG to the negative drive potential VEE.

  As described above, in the first embodiment, the power-on reset circuit 18 automatically releases the reset signal after supplying the reset signal to the plurality of shift registers 21a to 21c at the time of power-on, and the clock signal. In synchronization with the vertical shift clock signal CK supplied from the line 20, the vertical shift data DI is transferred from the first-stage shift register 21a to the subsequent-stage shift registers 21b and 21c in order.

  Therefore, since stable serial output signals SRO1 to SRO3 can be supplied from the outputs of the shift registers 21a to 21c to the level conversion circuits 22a to 22c, a charging current flowing to the liquid crystal display electrode is generated, and the VGG potential is generated on the liquid crystal output side. Even though the output voltage V is output, a through current flowing from the VGG potential to the negative drive potential VEE flows between the first conductivity type (p-channel) MIS transistor and the second conductivity type (n-channel) MIS transistor. Can be prevented.

  Further, since the level conversion circuits 22a to 22c are not turned on at the same time, the plurality of liquid crystal output pads 24a to 24c do not change to the VGG potential at the time of turning on the power, so that the charging current flowing to the liquid crystal display electrodes can also be suppressed. .

  As shown in FIG. 4, the power-on reset circuit according to the first embodiment is provided in the preceding stage of the shift register, generates an internal reset signal at the time of power-on, and passes through the liquid crystal drive circuit and the liquid crystal display. The charging current to the electrode can be suppressed.

  The power-on reset circuit includes a first conductivity type channel (p channel) first MIS transistor P01 and a second conductivity type channel (n channel) second MIS transistor N01 between a high level logic power source 10 and a low level logic power source 15. Connect in series.

  The first control electrode 13 of the first MIS transistor P01 and the second control electrode 16 of the second MIS transistor N01 are connected in common to the high-level power supply 14 and controlled from the high-level power supply 14 that increases in voltage later than the voltage increase of the high-level logic power supply 10 when the power is turned on. Supply voltage.

  The first and second MIS transistors P01 and N01 detect an increase in the voltage of the high-level logic power supply 10, generate an internal reset signal from the connection node of the first and second MIS transistors, and NOR as logic gates provided in the subsequent shift register. An internal reset signal is supplied to one input terminal of the circuits 28a and 28b and the NAND circuits 29a and 29b.

  For example, the potential of each serial signal SRn + 1 to +2 is stabilized at a low level (L), and the output of the inverter 23a (see FIG. 2) at the next stage is held at a high level (H).

  Since the liquid crystal output pad 24a (see FIG. 2) holds the drive potential VEE, the charging current flowing to the liquid crystal display electrode is suppressed.

  The synchronous inverter 30a receives the serial signal SRn of the vertical shift data DI, connects the output to the other input terminal of the NAND circuit 29a at the next stage, and outputs a negative logical product with the inverted internal reset signal from the NAND circuit 29a. Let

  The NAND circuit 29a outputs the value of the negative logical product to the synchronous inverter 30d that is feedback-connected to the output of the synchronous inverter 30a, and synchronizes the negative logical product value as it is when the inverted internal reset signal is at a high level (H). To the output of the type inverter 30a. On the other hand, when the inverted internal reset signal is at the low level (L), the negative logical product value (H) is held.

  The synchronous inverter 30b receives the value of the negative logical product from the NAND circuit 29a, connects the output to the other input terminal of the next-stage NOR circuit 28a, and outputs the negative logical sum with the internal reset signal from the NOR circuit 28a. Let

  The NOR circuit 28a outputs the value of the negative logical sum as the serial signal SRn + 1, and simultaneously outputs the serial signal SRn + 1 to the synchronous inverter 30c connected in feedback to the output of the synchronous inverter 30b.

  When the internal reset signal is at a low level (L), the synchronous inverter 30c holds the negative OR value as it is at the output of the synchronous inverter 30b. On the other hand, when the internal reset signal is at a high level (H), the value of negative logical sum (H) is held at the output of the synchronous inverter 30b.

  The synchronous inverter 30e receives the serial signal SRn + 1, connects the output to the other input terminal of the NAND circuit 29b at the next stage, and outputs a negative logical product with the inverted internal reset signal from the NAND circuit 29b.

  The NAND circuit 29b outputs the value of the negative logical product to the synchronous inverter 30g that is feedback-connected to the output of the synchronous inverter 30e, and synchronizes the value of the negative logical product as it is when the inverted internal reset signal is at a high level (H). To the output of the type inverter 30e. On the other hand, when the inverted internal reset signal is at the low level (L), the negative logical product value (H) is held.

  The synchronous inverter 30f receives the negative logical product value from the NAND circuit 29b, connects the output to the other input terminal of the next-stage NOR circuit 28b, and outputs a negative logical sum with the internal reset signal from the NOR circuit 28b. Let

  The NOR circuit 28b outputs the value of the negative logical sum as the serial signal SRn + 2, and simultaneously outputs the serial signal SRn + 2 to the synchronous inverter 30h that is feedback connected to the output of the synchronous inverter 30f.

  When the internal reset signal is at a low level (L), the synchronous inverter 30h holds the negative OR value as it is at the output of the synchronous inverter 30f. On the other hand, when the internal reset signal is at a high level (H), a negative logical sum (L) is held at the output of the synchronous inverter 30f.

  The synchronous inverters 30a and 30e are driven by a common clock signal CPVB, and the synchronous inverters 30b and 30f are driven by a common clock signal CPV.

  The clock signal CPV can use a clock that transitions at the same phase as the vertical shift clock signal CK, and the clock signal CPVB can use a clock that transitions at a phase opposite to the vertical shift clock signal CK. The clock signals CPVB and CPV do not transition to the same logic state at the same time, thereby preventing a penetration phenomenon between data held in the input stage and data held in the output stage of each shift register.

  The power-on reset circuit supplies a high level (H) internal reset signal to the inputs of the NOR circuits 28a and 28b and supplies a high level (H) internal reset signal at the time of power-on. The serial signals SRn + 1 and SRn + 2 are fixed at a low level (L).

  The power-on reset circuit supplies a low-level (L) internal reset signal to the inputs of the NAND circuits 29a and 29b through the inverter 31 and supplies a low-level (L) internal reset signal at the power-on time. In this state, the outputs of the NAND circuits 29a and 29b are fixed to a high level (H).

  The operation of the shift register including the power-on reset circuit according to the first embodiment will be described with reference to FIGS.

  In the power-on sequence, the reference potential GND as the low-order logic power supply 15, the power supply potential VDD as the high-order logic power supply 10, and the drive potential VGG as the high-order power supply 14 are arranged in this order from the power supply circuit provided outside the power-on reset circuit. The power supply is output stably.

  The first MIS transistor P01 detects the drive potential VGG of the high-level power supply 14 through its control electrode, detects the voltage rise of the high-level logic power supply 10 from the power-on time t1, and makes the first MIS transistor P01 transition to the conductive state. The potential at the connection node of the first and second MIS transistors P01 and N01 is raised to the power supply potential VDD, and an internal reset signal is generated.

  The first MIS transistor P01 detects the drive potential VGG of the high level power supply 14 through the first control electrode 13, and outputs an internal reset signal until the drive potential VGG of the high level power supply 14 rises from the reference potential GND.

  The second MIS transistor N01 detects the drive potential VGG of the high potential power supply 14 through the second control electrode 16 at the time t2 when the power is turned on, and when the drive potential VGG of the high potential power supply 14 reaches a threshold voltage higher than the reference potential GND. The internal reset signal is extracted to the low-order logic power supply 15 and the internal reset signal is changed to the low level (L).

  Both the NOR circuits 28a and 28b output a low level (L) as the value of the negative logical sum based on the internal reset signal, and hold the serial output signals SRO1 to SRO3 at the reference potential GND.

  The power-on reset circuit keeps the potentials of the liquid crystal output pads G1 to G3 of the liquid crystal drive power supply system at the reference potential GND until the power-on time t1 to t3, thereby preventing the occurrence of unnecessary through current and charging current.

  The liquid crystal output pads G1 to G3 output the drive potential VEE as the negative drive potential VEE decreases with respect to the reference potential GND from time t3.

  At time t4 when the power is turned on, the driving potential VGG as the high level power supply 14 that supplies the liquid crystal power is high (H), the driving potential VEE as the low level power supply that supplies the liquid crystal power is low (L), and the high level logic power 10 Is at a high level (H) and the low-level logic power supply 15 is at a low level (L) and is stably output from the power supply circuit.

  The NOR circuit 28a transfers the vertical shift data DI and outputs it as a serial output signal SRO1.

  The NOR circuit 28b transfers the serial output terminal SRO1 and outputs it as a serial output signal SRO2.

  Thus, the shift register including the power-on reset circuit according to the first embodiment automatically generates a high-level (H) internal reset signal using the power-on sequence, and automatically Since the liquid crystal drive power supply can be supplied to the liquid crystal electrodes after the internal reset signal is changed to the low level (L), overcurrent and charging current of the liquid crystal drive power supply system can be prevented.

(Second Embodiment)
The power-on reset circuit according to the second embodiment of the present invention is connected between the high-level logic power supply 10 and the output terminal 11 as shown in FIG. The first MIS transistor P01 of the first conductivity type channel (p channel) connected to the high-level power supply 14 whose voltage rises slowly, and is connected between the output terminal 11 and the low-level logic power supply 15, and the second control electrode 16 is connected to the high-level power supply. 14, while detecting the voltage rise of the high-level power supply 14, while maintaining the cutoff state until the threshold voltage rises, transition to the conductive state when the voltage of the high-level power supply 14 reaches the threshold voltage, and reset signal And a second MIS transistor N01 of the second conductivity type channel (n channel) that pulls out from the output terminal 11 to the low-order logic power supply 15.

  The voltages of the first conductivity type (p-channel) third MIS transistor P05 and the fourth MIS transistor P06, which are electrically connected between the first control electrode 13 of the first MIS transistor P01 and the high level power supply 14, and the voltage of the high level power supply 14 are set. The threshold voltage is lowered to be supplied to the first control electrode 13, the state is changed to a conductive state in response to the voltage rise of the high level logic power supply 10, the reset signal is supplied from the high level logic power supply 10 to the output terminal 11, and the first A second conductivity type (n-channel) fifth MIS transistor N05 is further provided between the control electrode 13 and the low-level logic power source 15, and the control electrode of the fifth MIS transistor N05 is connected to the high-level logic power source 10a. The voltage rise of 14 is detected and a transition is made to the cut-off state.

  In the first embodiment, when the high-level logic power supply 10 transitions from the reference potential GND to the high level (L), the high-level power supply 14 also has the power supply potential VDD or power supply potential of the high-level logic power supply from the reference potential GND due to the Vf effect. In some cases, the voltage transitions to a voltage close to VDD.

  In this case, both the high-level power supply 14 and the high-level logic power supply 10 rise to 3V, the gate bias of the first MIS transistor P01 of the first conductivity type (p channel) is 0V, and the second conductivity type (n channel) second state. Since the gate bias of the 2MIS transistor N01 is turned on at 3V and the output terminal 11 becomes the low level (L) of the reference potential GND, an internal reset signal is not generated and the shift register malfunctions, and the liquid crystal driving circuit Through current is generated in

  Thus, in the power-on reset circuit according to the second embodiment, the voltage applied to the first control electrode 13 of the first MIS transistor P01 when the high-level power supply 14 is at the same level as or close to the high-level logic power supply 10. Is supplied by lowering the threshold voltage from the high-level power supply 14 so that the first MIS transistor P01 is turned on early and a reset signal is output to the output terminal 11 to stabilize the operation of the shift register and to reduce the through current of the liquid crystal drive power supply. Prevent in advance.

  That is, the power-on reset circuit sets the gate bias of the first MIS transistor P01 to the threshold voltage if the high-level power supply 14 does not reach the liquid crystal drive potential VGG and is the power-supply potential VDD of the high-level logic power supply 10 at the time of power-on. Therefore, the internal reset signal can be generated with high reliability.

  More specifically, a potential obtained by subtracting the threshold voltage from the drive potential VGG of the high-level power supply 14 is applied to the first control electrode 13 of the first MIS transistor P01 of the first conductivity type (p channel), and the second conductivity type (p channel) is applied. By applying a potential of 3 V to the second control electrode 16 of the second MIS transistor N01 and the control electrode of the fifth MIS transistor N05, the first MIS transistor P01 is turned on and an internal reset signal is output from the output terminal 11 Can be made.

  Further, when the power-on time elapses and the potential of the high-level power supply 14 rises higher than the power-supply potential VDD of the high-level logic power supply 10 by the threshold voltage, the first MIS transistor P01 is turned off and the potential of the output terminal 11 is the reference level. Transition to the potential GND.

  The operation of the power-on reset circuit according to the second embodiment will be described with reference to the timing chart of FIG. The overlapping description of elements common to the first embodiment is omitted.

  The first MIS transistor P01 detects the gate bias and the potential applied to the first control electrode 13, transitions to ON at time t1 when the power is turned on, and starts supplying an internal reset signal to the output terminal 11.

  Subsequently, the first MIS transistor P01 detects that the potential applied to the first control electrode 13 rises by a threshold voltage from the power supply potential VDD of the high-level logic power supply 10, and turns off at the power-on time t2. The supply of the internal reset signal of high level (H) to 11 is cut off.

  Since the second MIS transistor N01 is on, the internal reset signal is extracted to the low-order logic power supply 15 to complete the power-on reset sequence.

  Further, since the power-on times t3 and t4 operate in the same manner as in the first embodiment, redundant description is omitted.

  According to the power-on reset circuit shown in FIG. 6, even if the drive potential VGG of the high-level power supply 14 and the power-supply potential VDD of the high-level logic power supply 10 are approximate or rise with the same locus, the first MIS transistor P01 Since the potential applied to one control electrode 13 is reduced by the threshold voltage, it is easy to make the transition to the ON state, and it is possible to prevent the problem that the internal reset signal is not generated.

(Modification of the second embodiment)
As shown in FIG. 7, in the power-on reset circuit according to the modification of the second embodiment, the control electrode of the second conductivity type (n-channel) fifth MIS transistor N05 is the first and second MIS transistors P01, By applying the internal reset signal output from the connection node N01 via the inverter 36 and inverter 37 connected in series, the reset signal is supplied from the output terminal 11a to control the on / off operation.

  With this configuration, the period in which the fifth MIS transistor N05 is simultaneously turned on while the third MIS transistor P05 and the fourth MIS transistor P06 are on is shortened, and the currents of the third, fourth, and fifth MIS transistors P05, P06, and N05 are reduced. The through current due to the path can be reduced.

  More specifically, after the power-on time t2 shown in FIG. 8, the internal reset signal transitions to the reference potential GND, and the reset signal via the inverters 36 and 37 is applied to the control electrode of the fifth MIS transistor N05. Therefore, it is possible to provide a power-on reset circuit with higher reliability, since it is possible to prevent the through current from the high-level power supply 14 to the low-level logic power supply 15 by transitioning to the off state.

  Note that the actions and effects described in the embodiments of the present invention only list the most preferable actions and effects resulting from the present invention, and the actions and effects according to the present invention are included in the embodiments of the present invention. It is not limited to what has been described.

1 is a circuit diagram of a power-on reset circuit according to a first embodiment of the present invention. The block diagram of the application circuit of the power-on reset circuit which concerns on the 1st Embodiment of this invention. 2 is a timing chart of the power-on reset circuit according to the first embodiment of the present invention. 1 is a circuit diagram of a utility circuit including a power-on reset circuit according to a first embodiment of the present invention. 2 is a timing chart of the power-on reset circuit according to the first embodiment of the present invention. The circuit diagram of the power-on reset circuit which concerns on the 2nd Embodiment of this invention. The circuit diagram of the power-on reset circuit which concerns on the modification of the 2nd Embodiment of this invention. The timing chart of the power-on reset circuit which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

P01: First MIS transistor N01: Second MIS transistor P05: Third MIS transistor P06: Fourth MIS transistor N05: Fifth MIS transistor 10: High-level logic power supply 11: Output terminal 13: First control electrode 14: High-level power supply 15: Low-level logic power supply 16 ... second control electrode 18 ... power-on reset circuit 21a-21c ... shift register 22a-22c ... level conversion circuit 23a-23c ... inverter 24a-24c ... liquid crystal output pad 28a, 28b ... NOR circuit 29a, 29b ... NAND circuit 30a- 30h ... Synchronous inverter 31 ... Inverter 36, 37 ... Inverter

Claims (5)

A power-on reset circuit in which a high-level logic power supply voltage generated by a logic power supply circuit and a high-level power supply voltage generated by a power supply circuit provided separately from the logic power supply circuit are supplied from the outside,
Wherein the electrical connection between the high logic power supply and the output terminal, of the first conductivity type channel having a first control electrode connected to the high potential power supply to slow voltage rises above the voltage rise of the high logic power by the power-on A first MIS transistor;
A second conductivity type channel connected in series with the first MIS transistor at the output terminal, electrically connected between the output terminal and a low-level logic power supply, and having a second control electrode connected to the high-level power supply A second MIS transistor of
A power-on reset circuit, wherein the first MIS transistor transitions to a conductive state in response to a voltage rise of the high-level logic power supply, and a reset signal is supplied from the high-level logic power supply to the output terminal.   The first control electrode of the first MIS transistor is electrically connected to the third and fourth MIS transistors of the first conductivity type channel between the first power supply and the higher power supply, and reduces the voltage of the higher power supply by a threshold voltage. The power-on reset circuit according to claim 1, wherein the power-on reset circuit is supplied to a first control electrode of the first MIS transistor.   The first control electrode of the first MIS transistor is connected to the fifth MIS transistor of a second conductivity type channel between the first logic electrode and the low logic power source, and supplies the high logic power source to the control electrode of the fifth MIS transistor. The power-on reset circuit according to claim 2.   The first control electrode of the first MIS transistor is connected to the fifth MIS transistor of a second conductivity type channel between the first logic MIS transistor and the lower logic power supply, and the reset signal that has passed through a plurality of logic gates from the output terminal is transmitted to the fifth MIS transistor. The power-on reset circuit according to claim 2, wherein the power-on reset circuit is supplied to a control electrode of the transistor. A power-on reset method using a power-on reset circuit in which a high-level logic power supply voltage generated by a logic power supply circuit and a high-level power supply voltage generated by a power supply circuit provided separately from the logic power supply circuit are externally supplied. And
The first 1MIS transistor of the first conductivity type channel to transition to a conducting state in response due to power-on the voltage rise of the high logic power, and supplying a reset signal to the output terminal from the high logic power,
A step of shifting the voltage of the high power rises slower than the voltage of the high logic power to the cutoff state the first 1MIS transistor is detected by the first control electrode of the first 1MIS transistor,
The voltage of the high-level power supply is increased to the threshold voltage while being detected by the second control electrode of the second MIS transistor of the second conductivity type channel connected in series with the first MIS transistor at the output terminal after the power is turned on. and maintaining the cut-off state of the first 2MIS transistor to,
Transitioning the second MIS transistor to a conductive state when the voltage of the high-level power supply reaches the threshold voltage, and extracting the reset signal from the output terminal to a low-level logic power supply;
Including a power-on reset method.

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