CN201886234U - Liquid crystal display base plate and liquid crystal display (LCD) - Google Patents
Liquid crystal display base plate and liquid crystal display (LCD) Download PDFInfo
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- CN201886234U CN201886234U CN2010206401120U CN201020640112U CN201886234U CN 201886234 U CN201886234 U CN 201886234U CN 2010206401120 U CN2010206401120 U CN 2010206401120U CN 201020640112 U CN201020640112 U CN 201020640112U CN 201886234 U CN201886234 U CN 201886234U
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Abstract
The utility model discloses a liquid crystal display base plate and a liquid crystal display (LCD). The liquid crystal display base plate comprises a substrate base plate which at least comprises pattern of a signal wire, wherein the signal wire comprises a first signal wire layer and a second signal wire layer; an insulating layer is formed between the first signal wire layer and the second signal wire layer; and the two ends of the first signal wire layer and the second signal wire layer are electrically connected with each other by connecting via holes in the insulating layer. The signal wire is set into at least two layers, namely, signal wires which are in a parallel connection form can be formed, so that the resistance is obviously reduced after parallel connection; therefore, the resistance of the signal wire can be reduced, and the picture display quality is improved.
Description
Technical field
The utility model relates to lcd technology, relates in particular to a kind of liquid crystal display substrate and LCD.
Background technology
LCD is a flat-panel monitor commonly used at present, and wherein Thin Film Transistor-LCD (ThinFilm Transistor Liquid Crystal Display is called for short TFT-LCD) is the main product in the LCD.
The liquid crystal panel of LCD is mainly become box-like with array base palte by color membrane substrates, and color membrane substrates and array base palte all can be described as liquid crystal display substrate, can be formed with signal wire on it, for example data line, grid line and public electrode wire etc.Along with TFT-LCD liquid crystal panel size is increasing, the signal delay of various signal wires causes picture quality to descend along with the increase of line resistance becomes more and more serious.Especially for the data line of grid line that transmits sweep signal and transmission of data signals, signal delay is particularly outstanding to the influence of picture display quality.This just requires to adopt lower resistance material as metal wiring, present optimal metal material is aluminium and copper metal material, though copper and aluminium have lower resistance, at larger sized requirement, still can produce signal delay and increase, the shortcoming that picture quality descends.
The utility model content
The utility model provides a kind of liquid crystal display substrate and LCD, to reduce the line resistance of signal wire on the liquid crystal display substrate, reduces signal delay, improves picture quality.
The utility model embodiment provides a kind of liquid crystal display substrate, comprises underlay substrate, comprises the pattern of signal wire on the described underlay substrate at least, wherein:
Described signal wire comprises first signal line layer and secondary signal line layer, be formed with insulation course between described first signal line layer and the secondary signal line layer, and the two ends of described first signal line layer and secondary signal line layer are electrically connected by the via hole that is connected in the described insulation course.
Aforesaid liquid crystal display substrate, preferably:
Described signal wire is a data line;
Described first signal line layer is formed on the described underlay substrate, covers under the described insulation course, and described first signal line layer and grid line form with layer, and first signal line layer is provided with the compartment of terrain piecemeal;
Described secondary signal line layer is formed on the described insulation course, and the two ends of every section described first signal line layer are electrically connected with described secondary signal line layer respectively.
Aforesaid liquid crystal display substrate, preferably:
Described signal wire is a grid line;
Described first signal line layer is formed on the described underlay substrate, covers under the described insulation course;
Described secondary signal line layer is formed on the described insulation course, forms with layer with data line, and the setting at interval piecemeal of secondary signal line layer, the two ends of every section described secondary signal line layer are electrically connected with described first signal line layer respectively.
Aforesaid liquid crystal display substrate, preferably:
The side of described first signal line layer is formed with connecting portion, and described connecting portion exceeds the coverage of described secondary signal line layer;
Be coated with passivation layer on the described secondary signal line layer, be formed with pixel electrode on the described passivation layer and be connected lead-in wire;
The first connection via hole that described connection lead-in wire passes described secondary signal line layer pattern top is connected via hole with second of described connecting portion top, to be electrically connected described first signal line layer and secondary signal line layer.
Aforesaid liquid crystal display substrate, preferably:
Be coated with passivation layer on the described secondary signal line layer, also be formed with the 3rd signal line layer on the described passivation layer, described the 3rd signal line layer is electrically connected with described secondary signal line layer by the connection via hole in the described passivation layer.
The utility model embodiment also provides a kind of LCD, comprise framework, drive unit and liquid crystal panel, wherein: described liquid crystal panel comprises two liquid crystal display substrates that box is provided with, at least one liquid crystal display substrate that described liquid crystal display substrate adopts the utility model any embodiment to be provided.
Liquid crystal display substrate and LCD that the utility model embodiment is provided, be set to two-layer at least by signal wire, be equivalent to form the signal wire of parallel form, first signal line layer and secondary signal line layer are parallel with one another, back in parallel resistance can significantly reduce, therefore can reduce the line resistance of signal wire itself, improve the picture display quality.
Description of drawings
The plan structure synoptic diagram of the liquid crystal display substrate that Figure 1A provides for the utility model embodiment one;
Figure 1B is that A-A among Figure 1A is to the sectional structure synoptic diagram;
Form the plan structure synoptic diagram behind the grid line layer in the liquid crystal display substrate that Fig. 2 A provides for the utility model embodiment one;
Fig. 2 B is that A-A among Fig. 2 A is to the sectional structure synoptic diagram;
Form the plan structure synoptic diagram after the data line layer in the liquid crystal display substrate that Fig. 3 A provides for the utility model embodiment one;
Fig. 3 B is that A-A among Fig. 3 A is to the sectional structure synoptic diagram;
The plan structure synoptic diagram of the liquid crystal display substrate that Fig. 4 A provides for the utility model embodiment two;
Fig. 4 B is that B-B among Fig. 4 A is to the sectional structure synoptic diagram;
Form the plan structure synoptic diagram behind the grid line layer in the liquid crystal display substrate that Fig. 5 A provides for the utility model embodiment two;
Fig. 5 B is that B-B among Fig. 5 A is to the sectional structure synoptic diagram;
Form the plan structure synoptic diagram after the data line layer in the liquid crystal display substrate that Fig. 6 A provides for the utility model embodiment two;
Fig. 6 B is that B-B among Fig. 6 A is to the sectional structure synoptic diagram.
Reference numeral:
The 1-underlay substrate; The 2-grid line; 21-first grid line layer;
22-second grid line layer; The 3-gate electrode; The 4-gate insulation layer;
The 5-data line; 51-first data line layer; 52-second data line layer;
The 6-active layer; 7-source electrode; The 8-drain electrode;
The 9-passivation layer; 10-drain electrode via hole; The 11-pixel electrode;
The 12-connecting portion; 13-first connects via hole; 14-second connects via hole;
15-connects lead-in wire.
Embodiment
For the purpose, technical scheme and the advantage that make the utility model embodiment clearer, below in conjunction with the accompanying drawing among the utility model embodiment, technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the utility model protection.
The utility model embodiment provides a kind of liquid crystal display substrate, comprise underlay substrate, at least the pattern that comprises signal wire on this underlay substrate, and, this signal wire comprises first signal line layer and secondary signal line layer, be formed with insulation course between first signal line layer and the secondary signal line layer, and the two ends of first signal line layer and secondary signal line layer are electrically connected by the via hole that is connected in the insulation course.
The liquid crystal display substrate that the utility model embodiment is provided, be set to two-layer at least by signal wire, be equivalent to form the signal wire of parallel form, first signal line layer and secondary signal line layer are parallel with one another, as everyone knows, back in parallel resistance can significantly reduce, and therefore can reduce the line resistance of signal wire itself.
Liquid crystal display substrate of the present utility model can be color membrane substrates, also can be array base palte, and signal wire can be the circuit of transmission currents such as public electrode wire, grid line and/or data line or voltage signal.Because the conductive pattern on the liquid crystal display substrate is generally multi-level film layer structure, so when signal wire occurs with multilayer form, can utilize existing level to form pattern, need not to increase film layer structure, less to the influence of existing technology.Situation when specifying grid line and data line as signal wire below by embodiment.
Embodiment one
The plan structure synoptic diagram of the liquid crystal display substrate that Figure 1A provides for the utility model embodiment one, Figure 1B are that A-A among Figure 1A is to the sectional structure synoptic diagram.The liquid crystal display substrate of present embodiment is specially array base palte, comprises underlay substrate 1, is formed with horizontal vertical data line crossing 5 and grid line 2 on it, encloses the pixel cell that forms matrix form, comprises TFT on-off element and pixel electrode 11 in each pixel cell.Typical hierarchical structure is that grid line 2 and gate electrode 3 are formed on the underlay substrate 1, covering gate insulation course 4 on it; Data line 5, active layer 6, source electrode 7 and drain electrode 8 are formed on the gate insulation layer 4, cover passivation layer 9 on it; Form pixel electrode 11 on the passivation layer 9.
This signal wire is a data line 5 in the present embodiment, comprises first signal line layer and secondary signal line layer, is designated as first data line layer 51 and second data line layer 52.First data line layer 51 is formed on the underlay substrate 1, covers gate insulation layer 4 times, and first data line layer 51 forms with layer with grid line 2, and the compartment of terrain setting piecemeal of first data line layer 51, shown in Fig. 2 A and 2B.Second data line layer 52 is formed on the gate insulation layer 4, this second data line layer 52 and existing data line 5 generation types and similar, promptly in this layer, can form patterns such as second data line layer 52, source electrode 7, drain electrode 8 and active layer 6, shown in Fig. 3 A and 3B.The two ends of every section first data line layer 51 are electrically connected with second data line layer 52 respectively.
In concrete the application, first data line layer 51 can directly link to each other by the via hole that is connected in the gate insulation layer 4 with second data line layer 52, also can link to each other by the connection via hole in the passivation layer 9.Preferably utilize the material of pixel electrode 11 to connect first data line layer 51 and second data line layer 52.Concrete structure is shown in Figure 1A and 1B, and the side of first data line layer 51 is formed with connecting portion 12, and connecting portion 12 exceeds the coverage of second data line layer 52; Be coated with passivation layer 9 on second data line layer 52, be formed with pixel electrode 11 on the passivation layer 9 and be connected lead-in wire 15; Connect the 15 first connection via holes 13 that pass second data line layer, 52 patterns top that go between and be connected via hole 14, to be electrically connected first data line layer 51 and second data line layer 52 with second of connecting portion 12 tops.
Above-mentioned connected mode is easier realization in actual process, and connects via hole and can form simultaneously with original drain electrode via hole 10 in the passivation layer 9, so need not to increase extra formation step on technology.
The technical scheme of present embodiment can adopt the mode of parallel resistance to reduce the line resistance of data line, thereby reduces signal delay, improves image displaying quality.
Embodiment two
The plan structure synoptic diagram of the liquid crystal display substrate that Fig. 4 A provides for the utility model embodiment two, Fig. 4 B are that B-B among Fig. 4 A is to the sectional structure synoptic diagram.The liquid crystal display substrate of present embodiment is specially array base palte, is that with the difference of embodiment one this signal wire is a grid line 2 in the present embodiment, comprises first signal line layer and secondary signal line layer, is designated as first grid line layer 21 and second grid line layer 22.First grid line layer 21 is formed on the underlay substrate 1, covers gate insulation layer 4 times, and this first grid line layer 21 and existing grid line 2 generation types and similar promptly form structures such as grid line 2 and gate electrode 3, shown in Fig. 5 A and 5B in this layer.Second grid line layer 22 is formed on the gate insulation layer 4, forms with layer with data line 5, and the compartment of terrain setting piecemeal of second grid line layer 22, shown in Fig. 6 A and 6B.The two ends of every section second grid line layer 22 are electrically connected with first grid line layer 21 respectively.
In concrete the application, first grid line layer 21 can directly link to each other by the via hole that is connected in the gate insulation layer 4 with second grid line layer 22, also can link to each other by the connection via hole in the passivation layer 9.Preferably utilize the material of pixel electrode 11 to connect first grid line layer 21 and second grid line layer 22.Concrete structure is shown in Fig. 4 A and 4B, and the side of first grid line layer 21 is formed with connecting portion 12, and connecting portion 12 exceeds the coverage of second grid line layer 22; Be coated with passivation layer 9 on second grid line layer 22, be formed with pixel electrode 11 on the passivation layer 9 and be connected lead-in wire 15; Connect the 15 first connection via holes 13 that pass second grid line layer, 22 patterns top that go between and be connected via hole 14, to be electrically connected first grid line layer 21 and second grid line layer 22 with second of connecting portion 12 tops.
Above-mentioned connected mode is easier realization in actual process, and connects via hole and can form simultaneously with original drain electrode via hole 10 in the passivation layer 9, so need not to increase extra formation step on technology.
The technical scheme of present embodiment can adopt the mode of parallel resistance to reduce the line resistance of grid line, thereby reduces signal delay, improves image displaying quality.
The foregoing description one and embodiment two have provided the situation that realizes data line or grid line with parallel way respectively, it will be appreciated by those skilled in the art that, can also adopt the mode of two-layer at least signal line layer to realize data line and grid line simultaneously, and other signal wires such as public electrode wire, do not repeat them here.The signal wire level is not limited to the double-layer structure among the embodiment, for example can also comprise the 3rd signal line layer.Be coated with passivation layer on the secondary signal line layer, also be formed with the 3rd signal line layer on the passivation layer, the 3rd signal line layer is electrically connected with secondary signal line layer by the connection via hole in the passivation layer.Preferably adopt the material of pixel electrode as the 3rd signal line layer, so that further reduce line resistance by parallel connection, the 3rd signal line layer can be that straight line connects, and also can be to be provided with at interval piecemeal.
The utility model embodiment also provides a kind of LCD, comprise framework, drive unit and liquid crystal panel, wherein, this liquid crystal panel comprises two liquid crystal display substrates that box is provided with, at least one liquid crystal display substrate that liquid crystal display substrate adopts the utility model any embodiment to be provided.Two liquid crystal display substrates are typically and comprise color membrane substrates and array base palte, preferably with liquid crystal display substrate of the present utility model as array base palte.Liquid crystal panel is fixed in the framework, links to each other display image under the driving of drive unit with drive unit.
The technical scheme of the utility model embodiment can adopt the mode of parallel resistance to reduce the line resistance of signal wire, thereby reduce signal delay, improve image displaying quality, especially can satisfy the large scale liquid crystal panel requirement and, the manufacturing process of technique scheme is simple, can utilize existing technological process, need not to increase extra production cost.
It should be noted that at last: above embodiment only in order to the explanation the technical solution of the utility model, is not intended to limit; Although the utility model is had been described in detail with reference to previous embodiment, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of each embodiment technical scheme of the utility model.
Claims (6)
1. a liquid crystal display substrate comprises underlay substrate, comprises the pattern of signal wire on the described underlay substrate at least, it is characterized in that:
Described signal wire comprises first signal line layer and secondary signal line layer, be formed with insulation course between described first signal line layer and the secondary signal line layer, and the two ends of described first signal line layer and secondary signal line layer are electrically connected by the via hole that is connected in the described insulation course.
2. liquid crystal display substrate according to claim 1 is characterized in that:
Described signal wire is a data line;
Described first signal line layer is formed on the described underlay substrate, covers under the described insulation course, and described first signal line layer and grid line form with layer, and first signal line layer is provided with the compartment of terrain piecemeal;
Described secondary signal line layer is formed on the described insulation course, and the two ends of every section described first signal line layer are electrically connected with described secondary signal line layer respectively.
3. liquid crystal display substrate according to claim 1 is characterized in that:
Described signal wire is a grid line;
Described first signal line layer is formed on the described underlay substrate, covers under the described insulation course;
Described secondary signal line layer is formed on the described insulation course, forms with layer with data line, and the setting at interval piecemeal of secondary signal line layer, the two ends of every section described secondary signal line layer are electrically connected with described first signal line layer respectively.
4. according to claim 2 or 3 described liquid crystal display substrates, it is characterized in that:
The side of described first signal line layer is formed with connecting portion, and described connecting portion exceeds the coverage of described secondary signal line layer;
Be coated with passivation layer on the described secondary signal line layer, be formed with pixel electrode on the described passivation layer and be connected lead-in wire;
The first connection via hole that described connection lead-in wire passes described secondary signal line layer pattern top is connected via hole with second of described connecting portion top, to be electrically connected described first signal line layer and secondary signal line layer.
5. according to claim 2 or 3 described liquid crystal display substrates, it is characterized in that:
Be coated with passivation layer on the described secondary signal line layer, also be formed with the 3rd signal line layer on the described passivation layer, described the 3rd signal line layer is electrically connected with described secondary signal line layer by the connection via hole in the described passivation layer.
6. LCD, comprise framework, drive unit and liquid crystal panel, it is characterized in that: described liquid crystal panel comprises two liquid crystal display substrates that box is provided with, and at least one described liquid crystal display substrate adopts the arbitrary described liquid crystal display substrate of claim 1～5.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010206401120U CN201886234U (en) | 2010-11-29 | 2010-11-29 | Liquid crystal display base plate and liquid crystal display (LCD) |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010206401120U CN201886234U (en) | 2010-11-29 | 2010-11-29 | Liquid crystal display base plate and liquid crystal display (LCD) |
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| CN201886234U true CN201886234U (en) | 2011-06-29 |
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