CN102708771B - Array substrate, manufacturing method and display unit thereof - Google Patents

Abstract

The invention discloses an array substrate, a manufacturing method thereof, and a display device, and relates to the design field of the display device, which is used for realizing the test of any data line signal in the display device. The array substrate includes: a display area and a non-display area, the non-display area includes at least one data line lead pattern unit; each data line lead pattern unit is provided with a plurality of data line leads, and the data line leads include a first connection portion, The first connecting part is used for electrical connection with the chip, and at least one test line is also arranged in each of the data line lead pattern units, and each test line is arranged to cross all the data line leads located in the same data line lead pattern unit, And an insulating layer is arranged between the test line and the lead of the data line; wherein, the test line includes a second connection part, which is used to electrically connect with the chip and connect the test point of the printed circuit board through the chip. The invention is used in the design and manufacture of array substrates.

Description

Array substrate, manufacturing method thereof, and display device

technical field

The present invention relates to the design field of display devices, in particular to an array substrate, a manufacturing method thereof, and a display device.

Background technique

As shown in FIG. 1 , the current display panel structure of TFT-LCD (Thin Film Field Effect Transistor-Liquid Crystal Display) includes: an array substrate 11 and a color filter substrate 12 formed in a box, and liquid crystal between the two substrates. Since both the data lines and the gate lines on the array substrate need to be connected to the driving circuit, the array substrate 11 is slightly larger than the color filter substrate 12 to leave space required for connecting the driving circuit. The above two substrates are bonded by a sealant, and the inside of the sealant is filled with liquid crystals for displaying images. Therefore, the area inside the sealant on the array substrate can be called a display area, and other areas can be called a non-display area. For clarity of description, the data lines located in the non-display area are referred to as data line leads, and the gate lines located in the non-display area are referred to as gate line leads. The following will further describe the data line leads.

Referring to the enlarged view shown in FIG. 2, in the non-display area, the area where a group of closely arranged data line leads is located is called a data line lead pattern unit, and the data line leads 31 in each data line lead pattern unit need A chip 13 is electrically connected to a PCB (Printed Circuit Board, printed circuit board) 14; wherein, the chip carries an IC (integrated circuit, integrated circuit), and the more commonly used chip is COF (Chip On Film, thin film chip).

In order to realize the test of the data line signal, the current common method is to use the wiring design on the chip to electrically connect the corresponding data line on the both sides of each chip to the test point on the PCB board 14, so as to realize the test of the data line. Line signal test. Obviously, the above method only implements the test function for individual data lines, which brings a lot of inconvenience to the later failure analysis and performance test of the panel.

Contents of the invention

Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device, which are used to test any data line signal in the display device, so as to improve the working efficiency of late-stage defect analysis and panel performance testing.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

In one aspect, the present invention provides an array substrate, including: a display area and a non-display area, the non-display area includes at least one data line lead pattern unit; each of the data line lead pattern units is provided with a plurality of data wire lead, the data wire lead includes a first connection part, and the first connection part is used for electrical connection with the chip, and at least one test line is also arranged in each of the data line lead pattern units, and each test line is located with the All the data line leads of the same data line lead pattern unit are arranged crosswise, and an insulating layer is arranged between the test line and the data line lead; wherein, the test line includes a second connection part, and the second connection part is used for The chip is electrically connected to the chip, and connected to the test point of the printed circuit board through the chip.

On the other hand, the present invention also provides a method for manufacturing an array substrate, including:

Fabricate a gate line metal thin film on the base substrate, and form a gate line metal layer pattern through a patterning process. The gate line metal layer pattern includes: a gate line, a gate line lead, and at least one test line located in each data line lead pattern unit line; the test line includes a second connection part, the second connection part is used to electrically connect with the chip, and connect the test point of the printed circuit board through the chip;

Continue to form a gate insulating layer, an active layer, and a data line metal layer pattern; the data line metal layer pattern includes: a data line, a data line lead, wherein the data line lead includes a first connection portion, and the first connection portion Used for electrical connection with the chip;

making a passivation layer, and forming via holes at least at the positions of the first connection part and the second connection part through a patterning process;

Making a first transparent conductive film, and forming a first transparent electrode, a first contact part connected to the first connection part, and a second contact part connected to the second connection part through a patterning process.

In yet another aspect, the present invention also provides a display device, including: a color filter substrate, and the above-mentioned array substrate, chip, and printed circuit board;

The chip is electrically connected to the first connection part and the second connection part of the array substrate, and the second connection part of the chip is electrically connected to the test point of the printed circuit board.

In an array substrate, its manufacturing method, and a display device provided by an embodiment of the present invention, at least one test line is arranged in each of the data line lead pattern units, and each test line is located in the same data line lead pattern unit. All the leads of the data lines are set crosswise, so that when the signal of one of the data lines needs to be tested, the data line leads of the data line are connected with the test line, and then disconnected after the test is completed; thus, the display device can be realized Test any data line signal, thereby improving the efficiency of post-defect analysis and panel performance testing.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a schematic structural diagram of a display panel in the prior art;

Figure 2 is a partial enlarged schematic view of Figure 1;

FIG. 3 is a schematic structural view of an array substrate provided by the present invention;

Fig. 4 is a partial enlarged schematic diagram of Fig. 3;

Fig. 5 is another partially enlarged schematic diagram of Fig. 3;

Fig. 6 is another partially enlarged schematic diagram of Fig. 3;

FIG. 7 is a partially enlarged schematic diagram of another array substrate provided by the present invention;

8-12 are cross-sectional views during the manufacturing method of the array substrate shown in FIG. 4 .

Reference signs:

11-array substrate, 12-color film substrate, 13-chip, 14-PCB board;

21-display area, 22-non-display area, 221-data line lead pattern unit, 222-gate line lead pattern unit;

31-data line lead, 311-first connection part, 32-gate line lead, 33-test line, 331-second connection part;

41 - the first contact part, 43 - the second contact part;

51 - gate insulation layer, 52 - passivation layer.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

As shown in FIGS. 3-7 , an embodiment of the present invention provides an array substrate, including: a display area 21 and a non-display area 22, the non-display area 22 includes at least one data line lead pattern unit 221; A plurality of data line leads 31 are provided in the data line lead pattern unit 221, and the data line leads 31 include a first connection portion 311, and the first connection portion 311 is used for electrical connection with the chip. Of course, the non-display area also includes at least one gate line pattern unit 222 , and each gate line pattern unit 222 is provided with a plurality of gate lines 32 .

In all embodiments of the present invention, the display area refers to the area of the array substrate inside the sealant when the cell is assembled, and this area is used to fill liquid crystals to display images, and other areas are called non-display areas. For the convenience of description, the part of the data line in the display area is still called the data line, and the part in the non-display area is called the data line lead. Similarly, the part of the gate line in the display area is still called the gate line. That part of the display area is called a gate line lead. In the non-display area, the area where a group of closely arranged data line leads is called a data line lead pattern unit, and the area where a group of closely arranged gate line leads is located is called a gate line lead pattern unit.

In the embodiment of the present invention, improvements are mainly made in the data line lead pattern unit 221 . Each of the data line lead pattern units 221 is also provided with at least one test line 33, and each test line 33 is intersected with all the data line leads 31 located in the same data line lead pattern unit, and the test line 33 and all the test lines An insulating layer is provided between the data line lead wires 31; wherein, the test line 33 includes a second connection portion 331, which is used to electrically connect with the chip, and connect the printed circuit board through the chip the test point.

It should be noted that the insulating layer refers to a layer structure having an insulating function.

Figures 3-6 take setting one test line as an example, and Figure 7 takes setting two test lines as an example. Since n (n≧1) test lines 33 are set, the signals of n data lines can be tested at the same time, that is to say, the more test lines are set, the more data line signals can be tested at the same time. However, considering the limitation of the space of the lead pattern unit of the data line, it is preferable to set one or two test lines.

In the array substrate provided by the embodiment of the present invention, at least one test line is arranged in each of the data line lead pattern units, and each test line is arranged to cross all the data line leads in the same data line lead pattern unit, so that when When the signal of one of the data lines needs to be tested, the data line lead of the data line is connected to the test line, and then disconnected after the test is completed; thus, the test of any data line signal in the display device can be realized, and then Improve the work efficiency of post-defect analysis and panel performance testing.

Further, the second connecting portion 331 of the test line 33 is located at one end of the test line 33 . In this way, test lines can be added without changing the distribution of the lead wires of the data lines.

Further, in the same data line lead pattern unit, the intersection position of the test line 33 and the data line lead 31 can refer to FIG. 4 and FIG. It coincides with the first connection portion 311 of the data line lead 31 , and may also refer to FIG. 6 inside the first connection portion 311 of the data line lead 31 . In the embodiment of the present invention, for one data line lead 31, it is divided into two sides by the first connection part 311, wherein the side close to the edge of the array substrate is called the outside of the first connection part 311, and the other side is the outer side of the first connection part 311. The side is referred to as the inner side of the first connection part 311 .

Referring to FIG. 5 , in the same data line lead pattern unit, the intersection position of the test line 33 and the data line lead 31 coincides with the first connecting portion 311 of the data line lead. When the data line signal needs to be tested, the signals of each data line lead 31 are tested sequentially in the order from farthest to the second connecting portion 331 (that is, from left to right in the figure). For the signal test of one of the data line leads 31, specifically, first adopt laser technology to connect the test line 33 with the data line lead 31 to be tested at the crossing position (i.e. the welding position) of the two, so that the data line to be tested can be The signal of the lead 31 is introduced into the test point of the PCB; after the test is completed, the test line 33 between the tested data line lead 31 and the next data line lead 31 to be tested needs to be cut off by laser technology.

Referring to FIG. 6 , in the same data line lead pattern unit, the intersection position of the test line 33 and the data line lead 31 is inside the first connecting portion 311 of the data line lead. When it is necessary to test the data line signal, refer to the above test method, which will not be repeated here.

Preferably, referring to FIG. 4 and FIG. 7 , in the same data line lead pattern unit, the intersection position of the test line 33 and the data line lead 31 is located outside the first connecting portion 311 of the data line lead. When any data line signal in the data line lead pattern unit needs to be tested, laser technology is used to connect the test line 33 with the data line lead 31 to be tested at the crossing position (i.e. the welding position) of the two. After the test, it is only necessary to use laser technology to switch the data line leads 31 between the intersection position and the first connecting portion 311 . This solution does not need to test the data line signals in a fixed order, which is more flexible.

Furthermore, the test lines and the gate lines in the display area are arranged on the same layer. The so-called arrangement on the same layer refers to at least two patterns, and refers to a structure in which at least two patterns are arranged on the same layer of film. Specifically, the pattern is formed on a layer of film made of the same material through a patterning process. At least two patterns. This only changes the pattern formed by the patterning process without increasing the manufacturing steps.

Preferably, the test lines are parallel to the grid lines in the display area.

Since the general gate lines and data line leads are covered by at least one layer of insulating layer, the data line leads and the test lines arranged on the same layer as the gate lines all need to pass through the insulating layer so as to be able to connect to the chip; so in the embodiment of the present invention , Preferably, the first connection part 311 is connected to the first contact part 41 through a via hole, and the first connection part 311 is used to electrically connect with the chip, including: the first connection part 311 is used to pass the first The contact portion 41 is electrically connected to the chip; the second connection portion 331 is connected to the second contact portion 43 through a via hole, and the second connection portion 331 is used to electrically connect to the chip including: the second connection portion 331 is used is electrically connected to the chip through the second contact portion 43 .

Wherein, the materials of the first contact portion 41 and the second contact portion 43 are both conductive materials.

Further preferably, the first contact portion 41 and the second contact portion 43 are arranged on the same layer as the upper transparent electrode in the display area. It should be noted that the upper transparent electrode refers to the transparent electrode that is farthest from the array substrate from the base substrate, that is, the transparent electrode that is fabricated last according to the fabrication sequence. Specifically, for an array substrate provided with only one kind of transparent electrode, such as a TN (Twist Nematic, twisted nematic) type LCD array substrate, which only includes pixel electrodes, the transparent electrode is the upper layer transparent electrode. For an array substrate provided with two kinds of transparent electrodes (pixel electrode and common electrode), such as an array substrate of FFS (Fringe Field Switching, fringe field switching) type LCD, at this time, the upper transparent electrode is a transparent electrode away from the base substrate.

An embodiment of the present invention also provides a method for manufacturing an array substrate. It should be noted that the drawings of the manufacturing method take the cross-sectional view at the section C-C in FIG. 4 as an example. The manufacturing method includes:

S101. As shown in FIG. 8 , fabricate a gate line metal thin film on the base substrate, and form a gate line metal layer pattern through a patterning process, the gate line metal layer pattern includes: gate lines, gate line leads, and At least one test line of the lead pattern unit; the test line includes a second connection part 331, which is used to electrically connect the chip and connect the test point of the printed circuit board through the chip;

S102, as shown in FIG. 9 , continue to form the gate insulating layer 51 and the active layer;

S103. As shown in FIG. 10 , form a data line metal layer pattern; the data line metal layer pattern includes: a data line, a data line lead, wherein the data line lead includes a first connection part 311, and the first connection part 311 is used for electrical connection with the chip;

S104, as shown in FIG. 11 , forming a passivation layer 52, and forming via holes at least at the positions of the first connecting portion 311 and the second connecting portion 331 through a patterning process;

S104, as shown in FIG. 12 , fabricate a first transparent conductive film, and form a first transparent electrode, a first contact portion 41 connected to the first connection portion 311 , and a first contact portion 41 connected to the second connection portion 331 through a patterning process The second contact portion 43.

It should be noted that each figure only shows the structure at each A-A cut plane, and although other parts are not shown in the figures, those skilled in the art can clearly determine the structure of the entire array substrate according to the above description.

The above is the manufacturing method of the array substrate of TN-type LCD, and the array substrate comprising two kinds of transparent electrodes, such as the array substrate of FFS-type LCD, its manufacturing method is after the above-mentioned formation of the pattern of the active layer and the metal layer of the data line Between, that is, at least between steps S102 and S103:

S105, forming a second transparent conductive film, and forming a second transparent electrode through a patterning process.

The embodiment of the present invention also provides a display device, including: a color filter substrate, any array substrate chip mentioned above, and a printed circuit board;

The chip is electrically connected to the first connection part and the second connection part of the array substrate, and the second connection part of the chip is electrically connected to the test point of the printed circuit board.

The array substrate manufactured according to the above manufacturing method and the display device including the array substrate, when the signal of one of the data lines needs to be tested, the data line lead of the data line is connected to the test line, and disconnected after the test is completed. That is enough; thus, the test of any data line signal in the display device can be realized, thereby improving the working efficiency of later failure analysis and panel performance test.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (9)

1. an array base palte, comprising: viewing area and non-display area, and described non-display area comprises at least one data line lead pattern unit; Be provided with a plurality of data lines lead-in wire in each described data line lead pattern unit, described data cable lead wire comprises the first connecting portion, and this first connecting portion is used for connecing with chip electrical, it is characterized in that,

At least one p-wire is also provided with in each described data line lead pattern unit, every bar p-wire is positioned at same data line lead pattern unit all data cable lead wires with it are arranged in a crossed manner, and are provided with insulation course between described p-wire and described data cable lead wire; Wherein, described p-wire comprises the second connecting portion, and this second connecting portion is used for connecing with described chip electrical, and connects the test point of printed circuit board (PCB) by described chip;

In same data line lead pattern unit, the crossover location of p-wire and data cable lead wire is positioned at the outside of the first connecting portion of this data cable lead wire.

2. array base palte according to claim 1, is characterized in that, the second connecting portion of described p-wire is in one end of this p-wire.

3. array base palte according to claim 1 and 2, is characterized in that, the grid line in described p-wire and described viewing area is arranged with layer.

4. array base palte according to claim 3, is characterized in that, described p-wire is parallel with described grid line.

5. array base palte according to claim 4, it is characterized in that, described first connecting portion connects the first contact site by via hole, and described first connecting portion is used for connecing with chip electrical comprising: described first connecting portion is used for being connect by described first contact site and chip electrical;

Described second connecting portion connects the second contact site by via hole, and described second connecting portion is used for connecing with described chip electrical comprising: described second connecting portion is used for being connect by described second contact site and described chip electrical.

6. array base palte according to claim 5, is characterized in that, the top transparent electrode in described first contact site, described second contact site and described viewing area is arranged with layer.

7. a manufacture method for array base palte, is characterized in that, comprising:

Underlay substrate makes grid line metallic film, and forms grid line metal layer pattern by patterning processes, described grid line metal layer pattern comprises: grid line, grid line go between and be positioned at least one p-wire of each data line lead pattern unit; Described p-wire comprises the second connecting portion, and this second connecting portion is used for connecing with chip electrical, and connects the test point of printed circuit board (PCB) by described chip;

Continue to form gate insulation layer, active layer, data wire metal layer pattern; Described data wire metal layer pattern comprises: data line, data cable lead wire, and wherein, described data cable lead wire comprises the first connecting portion, and this first connecting portion is used for connecing with chip electrical; In same data line lead pattern unit, the crossover location of p-wire and data cable lead wire is positioned at the outside of the first connecting portion of this data cable lead wire;

Make passivation layer, and at least form via hole in the position of described first connecting portion and described second connecting portion by patterning processes;

Make the first transparent conductive film, and form the first transparency electrode, the first contact site be connected with described first connecting portion, the second contact site of being connected with described second connecting portion by patterning processes.

8. manufacture method according to claim 7, is characterized in that, between the described active layer of formation and described data wire metal layer pattern, at least also comprises:

Form the second transparent conductive film, and form the second transparency electrode by patterning processes.

9. a display device, is characterized in that, comprising: color membrane substrates and the array base palte described in any one of claim 1-6, chip, printed circuit board (PCB);

First connecting portion and second connecting portion of described chip and described array base palte are electrically connected, and are electrically connected with the test point of described printed circuit board (PCB) by the second connecting portion of described chip.