CN102998865B - Array substrate, as well as manufacture method and display device thereof - Google Patents
Array substrate, as well as manufacture method and display device thereof Download PDFInfo
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- CN102998865B CN102998865B CN201210465328.1A CN201210465328A CN102998865B CN 102998865 B CN102998865 B CN 102998865B CN 201210465328 A CN201210465328 A CN 201210465328A CN 102998865 B CN102998865 B CN 102998865B
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 239000000758 substrate Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- 230000002093 peripheral effect Effects 0.000 claims abstract description 11
- 238000000059 patterning Methods 0.000 claims description 38
- 238000009413 insulation Methods 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 8
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 9
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract 6
- 239000010408 film Substances 0.000 description 26
- 239000002184 metal Substances 0.000 description 15
- 238000002161 passivation Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 230000003467 diminishing effect Effects 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 239000012528 membrane Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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Abstract
The embodiment of the invention relates to the field of display panels, and provides an array substrate, as well as a manufacture method and a display device thereof for reducing the possibility of uneven display of a liquid crystal screen. The array substrate comprises a display space and a peripheral routing space, wherein grid lead wires and data lead wires are formed in the peripheral routing space, the grid lead wires are connected with grid wires in the display space, and the data lead wires are connected with data wires in the display space; the grid lead wires comprise a first grid lead wire and a second grid lead wire; the first grid lead wire and the grid wires are arranged in the same layer, while the second grid lead wire and the data wires are arranged in the same layer; the first grid lead wire is connected with the second grid lead wire through a via hole.
Description
Technical field
The present invention relates to display panel field, particularly relate to a kind of array base palte and preparation method thereof, display device.
Background technology
Display panel is formed after box by array base palte and color membrane substrates, as shown in Figure 1, described array base palte comprises viewing area 1 and peripheral wiring region 2, described viewing area 1 comprises grid line 11 arranged in a crossed manner and data line 12, and thin film transistor (TFT) in the pixel region that limits of grid line 11 and data line 12 and pixel electrode (not shown).Described peripheral wiring region 2 comprises grid lead-in wire 21 and data lead 22, and described grid 21 one end that go between connect grid lines 11, and the other end connects grid driving chip 31, described data lead 22 one end connection data line 12, other end connection data driving chip 32.
In the prior art, in order to realize narrow frame, adjacent grid lead-in wire takes two-layer wiring i.e. n-th grid lead-in wire to be first layer metal circuit, article (n+1)th, grid lead-in wire is second layer metal circuit, in like manner also adopt two-layer wiring between described data lead, article n-th, data lead is first layer metal circuit, and (n+1)th data lead is second layer metal circuit.Owing to making the differences such as the live width of two sandwich circuits in the difference of the metal material, technique etc. of first layer metal circuit and second layer metal circuit and actual product, the resistance of two sandwich circuits can be caused also different.Like this when two-layer line transmissions, will occur owing to transmitting the difference of resistance the situation that the Signal transmissions of adjacent grid lead-in wire or adjacent data lead is inconsistent, it is uneven that this will cause liquid crystal display to show.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and preparation method thereof, display device, can reduce the uneven possibility occurred of liquid crystal display display.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of array base palte, comprise: viewing area and peripheral wiring region, described peripheral wiring region is formed with grid lead-in wire and data lead, described grid lead-in wire connects the grid line of described viewing area, described data lead connects the data line of described viewing area, and described grid lead-in wire comprises first grid lead-in wire and second gate lead-in wire, and described first grid lead-in wire is arranged with layer with described grid line, described second gate lead-in wire is arranged with layer with described data line, and described first grid lead-in wire is connected by the first via hole with described second gate lead-in wire;
Preferably, in n-th grid lead-in wire, described first grid lead-in wire is between described second gate lead-in wire and described grid line, and described first grid lead-in wire is directly connected with described grid line; During (n+1)th grid going between adjacent with described n-th grid go between, described second gate lead-in wire is between described first grid lead-in wire and described grid line, and described second gate lead-in wire is connected with described grid line by the 3rd via hole.
Further, described data lead comprises the first data lead and the second data lead, described first data lead and the described first grid go between and to arrange with layer, described second data lead and described second gate go between and to arrange with layer, and described first data lead is connected by the second via hole with described second data lead;
Wherein, in n-th data lead, described first data lead is between described second data lead and described data line, and described first data lead is connected with described data line by the 4th via hole; In (n+1)th data lead be adjacent, described second data lead is between described first data lead and described data line, and described second data lead is directly connected with described data line.
Preferably, the length of described first grid lead-in wire and described second gate lead-in wire is equal, and the length of described first data lead and described second data lead is equal.
A method for making for array base palte, comprising:
Substrate makes the first metallic film, at least forms first grid lead-in wire and grid line by patterning processes;
Aforesaid substrate makes insulation film, is formed the insulation course at least including the first via hole by patterning processes;
The substrate being formed with described insulation course makes the second metallic film, at least forms second gate lead-in wire and data line by patterning processes; Wherein, described first grid lead-in wire is connected by the first via hole with described second gate lead-in wire.
Preferably, describedly on aforesaid substrate, make insulation film, form by patterning processes the insulation course at least including the first via hole and comprise:
Aforesaid substrate makes insulation film, is formed the insulation course at least including the first via hole and the 3rd via hole by patterning processes;
Article n-th, in described grid lead-in wire, described first grid lead-in wire is between described second gate lead-in wire and described grid line, and described first grid lead-in wire is directly connected with described grid line; In (n+1)th described grid lead-in wire, described second gate lead-in wire is between described first grid lead-in wire and described grid line, and described second gate lead-in wire is connected with described grid line by the 3rd via hole.
Preferably, describedly on substrate, make the first metallic film, at least form first grid lead-in wire and grid line by patterning processes, comprising:
Substrate makes the first metallic film, is formed the pattern comprising first grid lead-in wire, the first data lead and grid line by patterning processes;
Describedly on aforesaid substrate, make insulation film, formed the insulation course at least including the first via hole by patterning processes, comprising:
Aforesaid substrate makes insulation film, is formed the insulation course comprising the first via hole, the second via hole, the 3rd via hole and the 4th via hole by patterning processes;
The described substrate being formed with described insulation course making the second metallic film, at least forming second gate lead-in wire and data line by patterning processes, comprising:
The substrate being formed with described insulation course makes the second metallic film, is formed the pattern comprising second gate lead-in wire, the second data lead and data line by patterning processes;
Wherein, in n-th data lead, described first data lead is between described second data lead and described data line, and described first data lead is connected with described data line by the 4th via hole; In (n+1)th data lead adjacent with described n-th data lead, described second data lead is between described first data lead and described data line, and described second data lead is directly connected with described data line.
A kind of display device, described display device comprises above-mentioned array base palte.
Array base palte that technique scheme provides and preparation method thereof, display device, by being divided into the first grid to go between in described grid lead-in wire and second gate goes between two sandwich circuits, further described data line is divided into the first data lead and described second data lead two sandwich circuit, double layer of metal lead-in wire is all included in every bar grid lead-in wire and every bar data lead, even if the manufacture craft of double layer of metal lead-in wire like this, the difference such as material or live width, go between with every bar grid that prior art provides or every bar data lead respectively for compared with independent layer of metal goes between, resistance difference between described grid lead-in wire provided by the invention diminishes, resistance difference between data lead also diminishes, signal delay difference is also along with diminishing, thus reduce the uneven possibility of liquid crystal display display.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of a kind of array base palte of the prior art;
The structural representation of a kind of array base palte that Fig. 2 provides for the embodiment of the present invention;
Fig. 3 is the cut-open view of n-th grid lead-in wire in the array base palte shown in Fig. 2;
Fig. 4 is the cut-open view of (n+1)th grid lead-in wire in the array base palte shown in Fig. 2.
Reference numeral:
1-viewing area, the peripheral wiring region of 2-; 11-grid line, 12-data line, 21-grid go between, 22-data lead, 31-grid driving chip, 32-data driving chip; The 211-first grid goes between, and 212-second gate goes between, 213-first via hole, 214-the 3rd via hole, 221-first data lead, 222-second data lead, 223-second via hole, 224-the 4th via hole; 21a-n-th grid lead-in wire, 21b-(n+1)th grid lead-in wire, 22a-n-th data lead, 22b-(n+1)th data lead.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.
Embodiments provide a kind of array base palte, be illustrated in figure 2 the vertical view of described array base palte, described array base palte comprises: viewing area 1 and peripheral wiring region 2, described peripheral wiring region 2 is formed with grid lead-in wire 21 and data lead 22, described grid lead-in wire 21 connects the grid line 11 of described viewing area 1, and described data lead 22 connects the data line 12 of described viewing area 1.Described grid lead-in wire 21 comprises first grid lead-in wire 211 and second gate lead-in wire 212, described first grid lead-in wire 211 is arranged with layer with described grid line 11, described second gate lead-in wire 212 is arranged with layer with described data line 12, and described first grid lead-in wire 211 is connected by the first via hole 213 with described second gate lead-in wire 212.
Described same layer is arranged at least two kinds of patterns; Particularly, at least two kinds of patterns arrange with layer and refer to: same film is formed at least two kinds of patterns by patterning processes.Such as, described first grid lead-in wire 211 arranges with layer with described grid line 11 and refers to: form the described first grid by metallic film by patterning processes and to go between 211 and described grid line 11; Described second gate lead-in wire 212 arranges with layer with described data line 12 and refers to: form described second gate by metallic film by patterning processes and to go between 212 and described data line 12.
The array base palte that the embodiment of the present invention provides is by being divided into the first grid to go between in described grid lead-in wire and second gate goes between two sandwich circuits, every bar grid lead-in wire all includes double layer of metal lead-in wire, even if the difference such as manufacture craft, material or live width of double layer of metal lead-in wire like this, go between respectively for compared with independent layer of metal goes between with every bar grid that prior art provides, resistance difference between described grid lead-in wire provided by the invention diminishes, between grid lead-in wire, the delay difference of signal is also along with diminishing, thus reduces the uneven possibility of liquid crystal display display.
Preferably, for all grid lead-in wires, article n-th, in grid lead-in wire 21a, described first grid lead-in wire 211 is between described second gate lead-in wire 212 and described grid line 11, described first grid lead-in wire 211 is directly connected with described grid line 11, described first grid lead-in wire 211 is connected by the first via hole 213 with described second gate lead-in wire 212, and its diagrammatic cross-section as shown in Figure 3.Go between in 21b with n-th grid adjacent (n+1)th grid of 21a that go between, described second gate lead-in wire 212 is between described first grid lead-in wire 211 and described grid line 11, described second gate lead-in wire 212 is connected with described grid line 11 by the 3rd via hole 214, described second gate lead-in wire 212 is gone between by the first via hole 213 and the described first grid and 211 to be connected, and its diagrammatic cross-section as shown in Figure 4.
Like this, it is different that first grid lead-in wire 211 in grid lead-in wire 21a and described second gate go between that 212 positions and grid go between in 21b, between the first grid lead-in wire that can prevent from being in same layer or contact with each other between second gate lead-in wire, and then the distance that can reduce between adjacent grid lead-in wire 21a and 21b, realize narrow frame.
In like manner, described data lead 22 comprises the first data lead 221 and the second data lead 222, described first data lead 221 and the described first grid go between and 211 to arrange with layer, described second data lead 222 and described second gate go between and 212 to arrange with layer, and described first data lead 221 is connected by the second via hole 223 with described second data lead 222.
Wherein, article n-th, in data lead 22a, described first data lead 221 is between described second data lead 222 and described data line 12, described first data lead 221 is connected with described data line 12 by the 4th via hole 224, and described first data lead 221 is connected by the second via hole 223 with described second data lead 222; In (n+1)th data lead 22b adjacent with described n-th data lead 22a, described second data lead 222 is between described first data lead 221 and described data line 12, described second data lead 222 is directly connected with described data line 12, and described first data lead 221 is connected by the second via hole 223 with described second data lead 222.
Described first grid lead-in wire 211 and described first data lead 221, arranged with layer with described grid line 11 in embodiments of the present invention; Described second gate lead-in wire 212 and described second data lead 222, arranged with layer with described data line 12.Grid lead-in wire and data lead can be produced like this when not increasing manufacture craft.
Simultaneously, described data lead is also divided into the first data lead and the second data lead two sandwich circuit by the array base palte in the embodiment of the present invention, every bar data lead all includes double layer of metal lead-in wire, even if the difference such as manufacture craft, material or live width of double layer of metal lead-in wire like this, go between respectively for compared with independent layer of metal goes between with every bar grid that prior art provides, resistance difference between described data lead provided by the invention also diminishes, signal delay difference between data lead also along with diminishing, thus reduces the uneven possibility of liquid crystal display display more.
Structure shown in Fig. 2 only represents two kinds of structures that the embodiment of the present invention provides array base palte, and those skilled in the art the structure shown in analogy Fig. 2 can draw other structures of the array base palte that the embodiment of the present invention provides easily.
Preferably, the length of described first grid lead-in wire 211 and described second gate lead-in wire 212 is equal, and the length of described first data lead 221 and described second data lead 222 is equal.
Suppose that the resistance of grid lead-in wire in prior art is respectively R1 or R2, then when the length of the described first grid lead-in wire 211 that the embodiment of the present invention provides and described second gate lead-in wire 212 is equal, the resistance of described grid lead-in wire 21 is approximately all (R1+R2)/2, resistance difference between grid lead-in wire 21 is minimum, ensure the homogeneous of the resistance between grid lead-in wire, in like manner, the resistance value between described data lead is also homogeneous, reduces the possibility that liquid crystal display display is uneven better.
In the embodiment of the present invention, the material of described first grid lead-in wire and described first data lead is for mostly being AlNd or Mo, and the material of described second gate lead-in wire and described second data lead mostly is Mo.
The embodiment of the present invention additionally provides a kind of method for making of array base palte, and described method for making comprises the following steps:
S1, on substrate, make the first metallic film, at least form first grid lead-in wire and grid line by patterning processes.
S2, on aforesaid substrate, make insulation film, formed the insulation course at least including the first via hole by patterning processes.
S3, on the substrate being formed with described insulation course, make the second metallic film, at least form second gate lead-in wire and data line by patterning processes; Wherein, described first grid lead-in wire is connected by the first via hole with described second gate lead-in wire.
Preferably, step S2 comprises: on aforesaid substrate, make insulation film, is formed the insulation course at least including the first via hole and the 3rd via hole by patterning processes; Wherein, in n-th described grid lead-in wire, described first grid lead-in wire is between described second gate lead-in wire and described grid line, and described first grid lead-in wire is directly connected with described grid line; In (n+1)th described grid lead-in wire, described second gate lead-in wire is between described first grid lead-in wire and described grid line, and described second gate lead-in wire is connected with described grid line by the 3rd via hole.
Further, step S1 comprises: on substrate, make the first metallic film, is formed the pattern comprising first grid lead-in wire, the first data lead and grid line by patterning processes; Step S2 comprises: on aforesaid substrate, make insulation film, is formed the insulation course comprising the first via hole, the second via hole, the 3rd via hole and the 4th via hole by patterning processes; Step S3 comprises: on the substrate being formed with described insulation course, make the second metallic film, is formed the pattern comprising second gate lead-in wire, the second data lead and data line by patterning processes; Wherein, in n-th data lead, described first data lead is between described second data lead and described data line, and described first data lead is connected with described data line by the 4th via hole; In (n+1)th data lead adjacent with described n-th data lead, described second data lead is between described first data lead and described data line, and described second data lead is directly connected with described data line.
While making grid line, produce first grid lead-in wire and the first data lead like this, while making data line, produce second gate lead-in wire and the second data lead, do not increase existing manufacture craft, cost-saving.
Example, the manufacture method of above-mentioned array base palte can comprise:
(1) make the first metallic film on the transparent substrate, at least formed the pattern of first grid lead-in wire, the first data lead and grid line and grid by patterning processes, example, the material of described metallic film is AlNd or Mo.
(2) on the substrate of completing steps (1), make insulating layer of thin-film, at least form the first via hole, the second via hole, the 3rd via hole and the 4th via hole by patterning processes.
(3) on the substrate of completing steps (2), make semiconductive thin film, be formed with active layer by patterning processes.
(4) on the substrate of completing steps (3), the second metallic film is made, second gate lead-in wire, the second data lead and data line and source-drain electrode is at least formed by patterning processes, described second gate lead-in wire to be gone between with the described first grid by the first via hole and is connected, described second data lead is connected with described first data lead by the second via hole, the described second gate lead-in wire of part is connected with grid line by the 3rd via hole, and described first data lead of part is connected with data line by the 4th via hole.
(5) on the substrate of completing steps (4), make passivation layer film, and form the passivation layer with via hole by patterning processes.
(6) on the transparency carrier of described formation passivation layer pattern, make transparent conductive film, at least form electrode pattern by patterning processes, described electrode pattern is connected with drain electrode by the via hole on passivation layer.
The embodiment of the present invention additionally provides a kind of display device, and described display device comprises liquid crystal indicator, organic light emitting display etc.Exemplarily, described display device can comprise the color membrane substrates after to box and array base palte, and wherein, described array base palte can be any one above-mentioned array base palte.Described display device can be any product or parts with Presentation Function such as liquid crystal display, LCD TV, digital camera, mobile phone, panel computer.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (10)
1. an array base palte, comprising: viewing area and peripheral wiring region, and described peripheral wiring region is formed with grid lead-in wire and data lead, and described grid lead-in wire connects the grid line of described viewing area, and described data lead connects the data line of described viewing area, it is characterized in that,
Described grid lead-in wire comprises first grid lead-in wire and second gate lead-in wire, and described first grid lead-in wire is arranged with layer with described grid line, and described second gate lead-in wire is arranged with layer with described data line, and described first grid lead-in wire is connected by the first via hole with described second gate lead-in wire.
2. array base palte according to claim 1, is characterized in that,
Article n-th, in grid lead-in wire, described first grid lead-in wire is between described second gate lead-in wire and described grid line, and described first grid lead-in wire is directly connected with described grid line;
During (n+1)th grid going between adjacent with described n-th grid go between, described second gate lead-in wire is between described first grid lead-in wire and described grid line, and described second gate lead-in wire is connected with described grid line by the 3rd via hole.
3. array base palte according to claim 1 and 2, is characterized in that,
Described data lead comprises the first data lead and the second data lead, described first data lead and the described first grid go between and to arrange with layer, described second data lead and described second gate go between and to arrange with layer, and described first data lead is connected by the second via hole with described second data lead.
4. array base palte according to claim 3, is characterized in that,
Article n-th, in data lead, described first data lead is between described second data lead and described data line, and described first data lead is connected with described data line by the 4th via hole;
In (n+1)th data lead adjacent with described n-th data lead, described second data lead is between described first data lead and described data line, and described second data lead is directly connected with described data line.
5. array base palte according to claim 4, is characterized in that, the length of described first grid lead-in wire and described second gate lead-in wire is equal, and the length of described first data lead and described second data lead is equal.
6. array base palte according to claim 5, is characterized in that,
The material of described first grid lead-in wire and described first data lead is A1Nd or Mo, and the material of described second gate lead-in wire and described second data lead is Mo.
7. a method for making for array base palte, is characterized in that, comprising:
Substrate makes the first metallic film, at least forms first grid lead-in wire and grid line by patterning processes;
Aforesaid substrate makes insulation film, is formed the insulation course at least including the first via hole by patterning processes;
The substrate being formed with described insulation course makes the second metallic film, at least forms second gate lead-in wire and data line by patterning processes; Wherein, described first grid lead-in wire is connected by the first via hole with described second gate lead-in wire.
8. method for making according to claim 7, is characterized in that, describedly on aforesaid substrate, makes insulation film, forms the insulation course at least including the first via hole comprise by patterning processes:
Aforesaid substrate makes insulation film, is formed the insulation course at least including the first via hole and the 3rd via hole by patterning processes;
Wherein, in n-th described grid lead-in wire, described first grid lead-in wire is between described second gate lead-in wire and described grid line, and described first grid lead-in wire is directly connected with described grid line; During (n+1)th the described grid going between adjacent with described n-th grid go between, described second gate lead-in wire is between described first grid lead-in wire and described grid line, and described second gate lead-in wire is connected with described grid line by the 3rd via hole.
9. the method for making according to claim 7 or 8, is characterized in that, describedly on substrate, makes the first metallic film, at least forms first grid lead-in wire and grid line, comprising by patterning processes:
Substrate makes the first metallic film, is formed the pattern comprising first grid lead-in wire, the first data lead and grid line by patterning processes;
Describedly on aforesaid substrate, make insulation film, formed the insulation course at least including the first via hole by patterning processes, comprising:
Aforesaid substrate makes insulation film, is formed the insulation course comprising the first via hole, the second via hole, the 3rd via hole and the 4th via hole by patterning processes;
The described substrate being formed with described insulation course making the second metallic film, at least forming second gate lead-in wire and data line by patterning processes, comprising:
The substrate being formed with described insulation course makes the second metallic film, is formed the pattern comprising second gate lead-in wire, the second data lead and data line by patterning processes;
Wherein, in n-th data lead, described first data lead is between described second data lead and described data line, and described first data lead is connected with described data line by the 4th via hole; In (n+1)th data lead adjacent with described n-th data lead, described second data lead is between described first data lead and described data line, and described second data lead is directly connected with described data line.
10. a display device, is characterized in that, described display device comprises the array base palte described in any one of claim 1 ~ 6.
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| CN103474435A (en) * | 2013-09-17 | 2013-12-25 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof |
| CN103560134B (en) * | 2013-10-31 | 2016-11-16 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, and display device |
| CN104076567A (en) * | 2014-07-22 | 2014-10-01 | 深圳市华星光电技术有限公司 | Array substrate, manufacturing method of array substrate and display device |
| CN105096753A (en) | 2015-09-01 | 2015-11-25 | 京东方科技集团股份有限公司 | Array base plate, manufacturing method of array base plate and display device |
| CN106782270A (en) * | 2017-01-09 | 2017-05-31 | 厦门天马微电子有限公司 | A kind of display panel and display device |
| CN106707646A (en) * | 2017-02-07 | 2017-05-24 | 厦门天马微电子有限公司 | Array base plate and display panel |
| CN106918970A (en) * | 2017-05-05 | 2017-07-04 | 武汉华星光电技术有限公司 | Array base palte, liquid crystal display panel and liquid crystal display device |
| CN107561798A (en) * | 2017-10-26 | 2018-01-09 | 惠科股份有限公司 | Fan-out line structure and manufacturing method thereof |
| CN107808864A (en) * | 2017-10-26 | 2018-03-16 | 惠科股份有限公司 | Fan-out line structure and manufacturing method thereof |
| CN108957885A (en) * | 2018-07-20 | 2018-12-07 | 深圳市华星光电技术有限公司 | Array substrate |
| US10861881B2 (en) | 2018-07-20 | 2020-12-08 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Array substrate |
| CN111627965A (en) * | 2020-05-26 | 2020-09-04 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
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| US8325311B2 (en) * | 2008-07-07 | 2012-12-04 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
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| CN101872092A (en) * | 2009-04-24 | 2010-10-27 | 上海天马微电子有限公司 | Liquid crystal display panel |
| CN102231028A (en) * | 2011-04-13 | 2011-11-02 | 友达光电股份有限公司 | Lead structure and display panel with same |
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