CN1953205A - Silicon-based one-electron transistor with quantum limit by oxygen injection and its manufacture method - Google Patents
Silicon-based one-electron transistor with quantum limit by oxygen injection and its manufacture method Download PDFInfo
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- CN1953205A CN1953205A CN 200510086640 CN200510086640A CN1953205A CN 1953205 A CN1953205 A CN 1953205A CN 200510086640 CN200510086640 CN 200510086640 CN 200510086640 A CN200510086640 A CN 200510086640A CN 1953205 A CN1953205 A CN 1953205A
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 154
- 239000010703 silicon Substances 0.000 title claims abstract description 154
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 148
- 229910052760 oxygen Inorganic materials 0.000 title claims abstract description 34
- 239000001301 oxygen Substances 0.000 title claims abstract description 34
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims description 26
- 238000002347 injection Methods 0.000 title claims description 6
- 239000007924 injection Substances 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title description 6
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 26
- 230000003647 oxidation Effects 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 230000005641 tunneling Effects 0.000 claims abstract description 9
- 239000002096 quantum dot Substances 0.000 claims description 50
- -1 oxygen ions Chemical class 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 150000003376 silicon Chemical class 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims 1
- 238000001465 metallisation Methods 0.000 claims 1
- 239000002070 nanowire Substances 0.000 claims 1
- 230000005611 electricity Effects 0.000 description 73
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 21
- 238000010276 construction Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 9
- 238000010894 electron beam technology Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
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- 238000005260 corrosion Methods 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229910000464 lead oxide Inorganic materials 0.000 description 5
- YEXPOXQUZXUXJW-UHFFFAOYSA-N oxolead Chemical compound [Pb]=O YEXPOXQUZXUXJW-UHFFFAOYSA-N 0.000 description 5
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
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- 230000008859 change Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 239000002159 nanocrystal Substances 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
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- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
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- 239000007943 implant Substances 0.000 description 1
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- 229910052698 phosphorus Inorganic materials 0.000 description 1
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Abstract
一种通过注氧进行量子限制的硅基单电子晶体管，包括：一硅衬底；一氧化物绝缘层制作在硅衬底上；一硅纳米电导细线制作在氧化物绝缘层上；一源极和漏极分别制作在氧化物绝缘层上，分别位于硅纳米电导细线的两端，并与硅纳米电导细线连接；一平面栅电极制作在氧化物绝缘层上；一氧化物薄层包裹在源极、漏极、硅纳米电导细线和平面栅电极的表面；二个氧化物隧穿结是通过注氧和热氧化形成的，埋于硅纳米电导细线的内部，并由氧化物隧穿结所限制；二个掩膜窗口包裹在硅纳米电导细线表面的氧化物薄层上，位于氧化物隧穿结上面。
A silicon-based single-electron transistor capable of quantum confinement by injecting oxygen, comprising: a silicon substrate; an oxide insulating layer fabricated on the silicon substrate; a silicon nanoconductive thin wire fabricated on the oxide insulating layer; a source The electrode and the drain are respectively fabricated on the oxide insulating layer, respectively located at the two ends of the silicon nanoconductive thin wire, and connected with the silicon nanoconductive thin wire; a planar gate electrode is fabricated on the oxide insulating layer; a thin oxide layer Wrapped on the surface of the source, drain, silicon nanoconductive thin wire and planar gate electrode; the two oxide tunnel junctions are formed by injecting oxygen and thermal oxidation, buried in the interior of the silicon nanoconductive fine wire, and formed by oxidation The object tunneling junction is limited; the two mask windows are wrapped on the oxide thin layer on the surface of the silicon nanoconductive thin wire, and are located on the oxide tunneling junction.
Description
Technical field
The present invention relates to a kind ofly, belong to the nanoelectronic technical field by annotating the new construction silicon based single electron transistor that oxygen carries out quantum limit.
Background technology
Along with the develop rapidly of CMOS large scale integrated circuit, the power dissipation capabilities trend limit that reduces to force chip of the growth of number of transistors and size.If can not in time dispel the heat, the temperature of device will constantly raise, and work in non-equilibrium state, so that device is destroyed, and the electron amount of therefore necessary minimizing work.Reduce the electronics flow area of conducting channel, increase resistance, can control the quantity of electronics effectively.When the electron transport bulk of leading when electricity is reduced to nanometer scale, will cause the remarkable enhancing of device quantum mechanical effects.According to uncertainty principle, electronics will be showed by electric current significantly in the momentum change in local space, and the uncertainty of signal can appear in device.The resistance of leading local space on the fine rule when electricity is greater than quantum resistance e
2During/h (=25.8k Ω), electronic motion will be restricted, and must tunnelling pass through, and quantum noise is also suppressed effectively.Single-electronic transistor (SET) is exactly to lead at the nanometer electricity to produce this pair of tunneling barrier or tunnel junctions on the fine rule, forms quantum dot (or coulomb island) structure.Because electronics exists coulomb blockade and resonance tunneling effect in transport process, electricity is led the periodic swinging along with the variation of grid voltage.As long as charge into electronics in the quantum dot, device just can conducting or is ended once.The power consumption of single-electronic transistor depends on the single electron electric current, if can high density integrated, its power consumption will only be 100,000 of present microelectronic transistors circuit/.
Obtained quantum-dot structure [Phys.Rev.Lett.65,771 (1990)] by two splitting bar door back bias voltage restrictions on the two-dimensional electron gas of nineteen ninety U.S. scientist in the GaAs/AlGaAs heterojunction.The potential energy distribution that back bias voltage on two division metal gates forms is smooth, and depletion widths is big, and the size of quantum dot is difficult to control smallerly, otherwise not conducting of transistor, so working temperature is very low.Even utilize narrow waveguiding structure to limit two-dimensional electron gas, utilize two grid that enclose to exhaust and limit out quantum dot again, improve working temperature and remain very limited.This is that depleted region is difficult to little of nanometer scale, and introduces electric charge to rise and fall easily and the generation noise because the negative voltage potential barrier is a kind of " soft " restriction.The sidewall surfaces density of states of the GaAs sill of etching is big, has a large amount of defectives, and this also has very big influence to transporting of single electron.And electron channel reality forms by horizontal depletion layer gesture, and this quantum passage by the restriction of " soft " gesture is very sensitive for temperature.When temperature was high, the gesture of surface state and blemish distributes, and great changes will take place in meeting, changes the quantum passage.Thermal excitation and the ambient noise of electronics in transport process also can be flooded quantum effect simultaneously.As far as we know, the single-electron device of GaAs base still can only be worked at present at low temperatures.
Characteristic and ripe process advantages such as silica-based single-electron device dependence silicon materials are oxidable in less than the time in 10 years, have been realized working and room temperature with regard to having produced diameter less than the crystalline silicon quantum dot of 10nm.The electricity of the narrow one dimension channel structure that the discoveries such as Scott-Thomas of U.S. MIT in 1989 are made of the silicon inversion layer is led to change with grid voltage and is presented periodic swinging behavior [Phys.Rev.Lett.62,583 (1989)], become the pioneer who in silicon, observes the coulomb blockade effect.To the later stage nineties in last century, Nippon Telegraph and Telephone (NTT) [Electronics Lett.31 (2), 136 (1995), Microelectron.Eng.35,261 (1997)], Minnesota ,USA (Minnesota) university (1998) [Appl.Phys.Lett.72 (10), 1205 (1998)] etc. has developed the single-electronic transistor based on thin silicon films SOI substrate of working and room temperature in succession.They utilize electron beam exposure and nanometer etching technology, lead two tunnel junctions of producing the point-contact junction structure on the fine rule at the silicon electricity and limit quantum dot.The quantum dot that this method obtains depends on mask pattern edge and etching situation, and process repeatability is bad.In recent years, [the Appl.Phys.Lett.73 (21) of Korea S university, 3129 (1998)], [J.Appl.Phys.94 (1) such as Cambridge University of Britain, 633 (2003)] utilize the silica-based self-organized quantum dot (being silicon nanocrystal) of growing on the silica, on this nano-crystal film, make metal electrode, utilize the energy level of side grid-control system quantum dot to distribute.The working temperature of the single-electronic transistor of preparing has also reached room temperature.Though the quantum dot that this method obtains is small-sized, can't control the quantity and the density distribution of quantum dot effectively, its uniformity and repeatability are also poor.And the single-electronic transistor of this structure is because the coupling of a plurality of quantum dots, and current characteristics is difficult to obtain the single electron characteristic of single quantum dot with more complicated.People such as Japan NTT laboratory Y.Ono utilize figure to rely on the single-electronic transistor that oxidizing process (PADOX) has prepared working and room temperature, its quantum dot controllable number [IEEE Trans.ElectronDevices, 47 (1), 147 (2000)].Concrete grammar is to utilize electron beam lithography and lithographic technique to make the electric lead of a band groove on the thin silicon films of SOI, carry out thermal oxidation then, in oxidizing process, because the stress between silicon and the silica is in the accumulation of the both sides of groove, oxidation rate reduces, automatically generate two silicon quantum dots that oxide is isolated, form two single-electronic transistors.The groove thickness of this method is thinner, could guarantee the formation of oxidation tunnel junction.The tunnel junctions position that this method is made and the size of quantum dot depend on the stress distribution that the etching figure forms.Tokyo Univ Japan is by the simple process of electron beam exposure and anisotropy chemistry corrosion, obtained the single-electronic transistor [Jp.J.Appl.Phys, 43 (2A), L210 (2004)] of working and room temperature on the thick P type thin silicon films of the 15nm of SOI.The conducting channel width has reached 5nm, and silicon quantum dot and tunnel junctions chain form naturally after the thermal oxidation.Though the restive quantum dot quantity of this method.But because quantum limit is fine, this single-electronic transistor shows more significant negative differential conductivity characteristic.
China had also carried out the research work of silicon based single electron device in recent years.Inst. of Physics, CAS has developed the silicon based single electron transistor [Appl.Phys.Lett.78,2160 (2001)] under the 90K temperature.Technologies such as electron beam lithography and reactive ion etching are adopted in Xi'an University of Technology and Hong Kong University of Science and Thchnology's cooperation, made the silicon single-electronic transistor on the p type SIMOX, can be in low-temperature working under the 77K [Chin.J.Semiconductors 23 (3), 246 (2002)].Yet the manufacture method of above single-electron device all can't effectively be controlled the nano-scale and the quantity of quantum dot.
Semiconductor single-electronic transistor that at present can working and room temperature is mainly all made successfully on the SOI substrate.This be because, silicon materials realize that easily oxidation isolates, the oxide isolated buried regions of SOI is opened device and substrate isolation, alleviated of the influence of substrate charge carrier to device, reduce the parasitic capacitance effect of silicon device, be easy to realize full dielectric isolation, avoided the interaction between device and the substrate.The silicon fiml of SOI substrate that is used to make single-electron device is all enough thin, is beneficial to and makes small tunnel junction and quantum dot.Utilizing thermal oxidation process to make the structure that small bis oxide tunnel junction limits quantum dot, is the production program of following very promising silicon based single electron transistor.
Summary of the invention
The present invention a kind ofly is characterized in that by annotating the silicon based single electron transistor that oxygen carries out quantum limit, comprising:
One silicon substrate;
The monoxide insulating barrier, this oxide insulating layer is produced on the silicon substrate;
One silicon nanometer electricity is led fine rule, and this silicon nanometer electricity is led fine rule and is produced on the oxide insulating layer;
One source pole and drain electrode, this source electrode and drain electrode are produced on the oxide insulating layer, lay respectively at the two ends that silicon nanometer electricity is led fine rule, and lead fine rule with silicon nanometer electricity and be connected, and this silicon nanometer electricity is led fine rule, source electrode and drain electrode and is formed an I-shape construction;
One planar gate electrodes, this planar gate electrodes is produced on the oxide insulating layer, and this planar gate electrodes is positioned at the side that silicon nanometer electricity is led fine rule;
Monoxide thin layer, this thin oxide layer are wrapped in the surface that source electrode, drain electrode, silicon nanometer electricity are led fine rule and planar gate electrodes, and silicon nanometer electricity is led fine rule form the quantum wire restriction;
Two oxide tunnel junctions, these two oxide tunnel junctions form by annotating oxygen and thermal oxidation, these two oxide tunnel junctions are embedded in the inside that silicon nanometer electricity is led fine rule, form quantum dot between these two oxide tunnel junctions, and are limited by the oxide tunnel junctions;
Two mask windows, these two mask windows are wrapped in silicon nanometer electricity and lead on the thin oxide layer on fine rule surface, are positioned at above the oxide tunnel junctions.
Wherein be embedded in silicon nanometer electricity and lead oxide tunnel junctions in the fine rule, form electricity in vertical direction and lead quantum point contact construction between fine rule and quantum dot.
Wherein source electrode and drain electrode are that the N type is heavily doped, and the electrode of this source electrode and drain electrode is an ohmic contact, and this ohmic contact is by polysilicon or metal deposit and annealing realization.
The present invention is a kind of to be is characterized in that by annotating the manufacture method that oxygen carries out the silicon based single electron transistor of quantum limit, comprises the steps:
1) gets a SOI substrate;
2) carrying out N type ion on the silicon thin layer of this SOI substrate injects;
3) on the silicon thin layer of SOI substrate, produce source electrode, drain electrode, silicon nanometer electricity and lead fine rule and planar gate electrodes, this source electrode and drain electrode lay respectively at the two ends that silicon nanometer electricity is led fine rule, and lead fine rule with silicon nanometer electricity and be connected, this silicon nanometer electricity is led fine rule, source electrode and drain electrode and is formed an I-shape construction, and planar gate electrodes is positioned at the side that silicon nanometer electricity is led fine rule;
4) lead two mask windows of making on the fine rule at silicon nanometer electricity, oxonium ion is injected in the mask window;
5) device is carried out thermal oxidation, form silicon quantum dot and oxide on surface thin layer by two oxide tunnel junctions restrictions;
6) by the electrode of polysilicon or metal deposit source electrode and drain electrode, annealing realizes ohmic contact.
Wherein be embedded in silicon nanometer electricity and lead oxide tunnel junctions in the fine rule, form electricity in vertical direction and lead quantum point contact construction between fine rule and quantum dot.
Wherein the spacing of the window that injected by the oxygen on the mask of the size of the quantum dot that is limited by the oxide tunnel junctions is controlled, and the quantity of quantum dot injects adjacent window apertures quantity by oxygen and determines.
Wherein lead fine rule and wrapped up, form the quantum wire restriction by oxide with the silicon nanometer electricity that source electrode links to each other with drain electrode.
Description of drawings
For further specifying content of the present invention and characteristics, the present invention is explained in detail below in conjunction with drawings and Examples:
Fig. 1 is the perspective view of silicon based single electron transistor of the present invention;
Fig. 2 is the planar structure schematic diagram of silicon based single electron transistor of the present invention;
Fig. 3 is an oxide tunnel junctions cross section stereo schematic diagram;
Fig. 4 is an oxide tunnel junctions sectional plane schematic diagram;
Embodiment
See also Fig. 1 to Fig. 4, the present invention is a kind of to be is characterized in that by annotating the silicon based single electron transistor that oxygen carries out quantum limit, comprising:
One silicon substrate 1;
One silicon nanometer electricity is led fine rule 5, and this silicon nanometer electricity is led fine rule 5 and is produced on the oxide insulating layer 2;
One source pole 3 and drain electrode 4, this source electrode 3 and drain electrode 4 are produced on the oxide insulating layer 2, lay respectively at the two ends that silicon nanometer electricity is led fine rule 5, and lead fine rule 5 with silicon nanometer electricity and is connected, and this silicon nanometer electricity is led fine rule 5, source electrode 3 and is drained 4 formation, one I-shape construction; Wherein source electrode 3 and drain electrode 4 are that the N type is heavily doped, and the electrode of this source electrode 3 and drain electrode 4 is an ohmic contact, and this ohmic contact is to realize with annealing by polysilicon or metal deposit;
One planar gate electrodes 6, this planar gate electrodes 6 is produced on the oxide insulating layer 2, and this planar gate electrodes 6 is positioned at the side that silicon nanometer electricity is led fine rule 5;
Monoxide thin layer 7, this thin oxide layer 7 are wrapped in source electrode 3, drain electrode 4, the silicon nanometer electricity surface of leading fine rule 5 and planar gate electrodes 6, and silicon nanometer electricity is led fine rule 5 form the quantum wires restriction;
Two oxide tunnel junctions 9, these two oxide tunnel junctions 9 form by annotating oxygen and thermal oxidation, these two oxide tunnel junctions 9 are embedded in the inside that silicon nanometer electricity is led fine rule 5, form quantum dot 10 between these two oxide tunnel junctions 9, and are limited by oxide tunnel junctions 9; Wherein be embedded in silicon nanometer electricity and lead oxide tunnel junctions 9 in the fine rule 5, form the quantum point contact construction that electricity is led 10 of fine rule 5 and quantum dots in vertical direction;
Two mask windows 8, these two mask windows 8 are formed on and are wrapped in silicon nanometer electricity and lead on the thin oxide layer 7 on fine rule 5 surfaces, are positioned at above the oxide tunnel junctions 9.
Please again in conjunction with consulting Fig. 1 to Fig. 4, the present invention is a kind of to be is characterized in that by annotating the manufacture method that oxygen carries out the silicon based single electron transistor of quantum limit, comprises the steps:
1) gets a SOI substrate;
2) carrying out N type ion on the silicon thin layer of this SOI substrate injects;
3) on the silicon thin layer of SOI substrate, produce source electrode 3, drain electrode 4, silicon nanometer electricity leads fine rule 5 and planar gate electrodes 6, this source electrode 3 and drain electrode 4 lay respectively at the two ends that silicon nanometer electricity is led fine rule 5, and lead fine rule 5 with silicon nanometer electricity and be connected, this silicon nanometer electricity is led fine rule 5, source electrode 3 and 4 formation, one I-shape construction that drains, and planar gate electrodes 6 is positioned at the side that silicon nanometer electricity is led fine rule 5; Wherein lead fine rule 5 with the drain electrode 4 silicon nanometer electricity that link to each other and wrapped up, form the quantum wire restriction by oxide 7 with source electrode 3;
4) lead two mask windows 8 of making on the fine rule 5 at silicon nanometer electricity, oxonium ion is injected in the mask window 8;
5) device is carried out thermal oxidation, form silicon quantum dot 10 and oxide on surface thin layer 7 by 9 restrictions of two oxide tunnel junctions; Wherein be embedded in silicon nanometer electricity and lead oxide tunnel junctions 9 in the fine rule 5, form the quantum point contact construction that electricity is led 10 of fine rule 5 and quantum dots in vertical direction; Wherein the spacing of the window 8 that injected by the oxygen on the mask of the size of the quantum dot 10 that is limited by oxide tunnel junctions 9 is controlled, and the quantity of quantum dot injects adjacent window apertures 8 quantity by oxygen and determines;
6) by the electrode of polysilicon or metal deposit source electrode 3 and drain electrode 4, annealing realizes ohmic contact.
Embodiment
See also Fig. 1 to shown in Figure 4, the silicon based single electron transistor of a kind of new construction of the present invention, it is characterized in that: this structure comprises that quantum dot 10 is limited by oxide tunnel junctions 9, being embedded in silicon nanometer electricity by the oxide tunnel junctions 9 of annotating oxygen and thermal oxidation formation leads in the fine rule 5, silicon nanometer electricity is led fine rule 5 and is linked to each other with drain electrode 4 with source electrode 3, planar gate electrodes 6 is positioned at electricity and leads fine rule 5 one sides, constitutes the side grating structure.
Described silicon based single electron transistor, it is characterized in that: be embedded in the oxide tunnel junctions 9 that silicon nanometer electricity leads in the fine rule 5 and form as follows: the mask window 8 of oxonium ion by the nano-scale width is injected into the silicon electricity and leads the fine rule bottom, through thermal oxidation, that near mask window 8 silicon electricity is led fine rule 5 tops is oxidized, has removed the lattice damage that the silicon electricity is led injection zone simultaneously.
Described silicon based single electron transistor is characterized in that: be embedded in silicon nanometer electricity and lead oxide tunnel junctions 9 in the fine rule 5, form quantum dot contact (Quantum Point Contact) structure in vertical direction.
Described silicon based single electron transistor is characterized in that: controlled by window 8 spacings that the oxygen on the mask injects by quantum dot 10 sizes that oxide tunnel junctions 9 is limited, the quantity of quantum dot injects the decision of adjacent window apertures 8 quantity by oxygen.
Described silicon based single electron transistor is characterized in that: lead fine rule 5 with source electrode 3 with the drain electrode 4 silicon nanometer electricity that link to each other and wrapped up by oxide 7, form the quantum wire restriction.
Described silicon based single electron transistor is characterized in that: the ohmic contact of two electrodes 3,4 is leaked by polysilicon or metal deposit and annealing realization in the source.
Described silicon based single electron transistor is characterized in that: be positioned at the planar gate electrodes 6 that electricity is led fine rule 5 one sides, by forming at the heavily doped silicon thin layer of the N of SOI surface of insulating layer type.
Described silicon based single electron transistor is characterized in that: single-electronic transistor uses the material of silicon thin layer-oxide 2-substrate 1 (being SOI) structure, and the surface silicon thin layer is used to make electricity and leads fine rule 5 and leakage the two poles of the earth 3,4, source, has the heavy doping of N type.
Please in conjunction with consulting Fig. 1 to shown in Figure 4, the invention provides a kind of new process and prepare silicon based single electron transistor, have that technology is fast and convenient, quantum dot is controlled, stable electrical properties, be suitable for superiority such as production in enormous quantities, make the extensive quantum logic circuit of preparation become possibility, and compatible mutually with silica-based microelectronic integrated circuit technology.It is characterized in that this method comprises the steps: that (1) is injected by phosphorus SOI top layer silicon thin layer is carried out the heavy doping of N type; (2) attenuate SOI top layer silicon thin layer; (3) the two poles of the earth contact table top is leaked in the source that etches, the quantum electricity is led fine rule and planar side gate electrode.(4) deposit medium mask is made double nano grid window, after oxygen injection and thermal oxidation, forms the two tunnel junctions of nano-oxide, limits out the quantum dot of nano-scale.(5) make source drain contact electrode.
Described step (1) is carried out: be injected into top layer silicon surface 10 as follows to the N type heavy doping of SOI top layer silicon thin layer
14/ cm
2Phosphonium ion, the degree of depth is 50nm, annealing can be eliminated lattice damage.
The attenuate of described step (2) SOI top layer silicon thin layer, carry out as follows: select the thick silicon thin layer of 100nm-200nm for use, 1000 ℃ of high-temperature thermal oxidation surfaces obtain the thick silica of 30nm, lead fine line region with photoetching and chemical corrosion at electricity and leave window, further high-temperature thermal oxidation surface, chemical corrosion stays required silicon thin layer thickness, and is thick as 30nm-50nm.
The two poles of the earth contact table top is leaked in described step (3) source and the quantum electricity is led fine rule, carries out as follows: the preparation electricity is led the photolithography plate of table top; On sample, cover negative photoresist, carry out ultraviolet photolithographic, utilize wet etching or ICP dry etching again, obtain the wide electricity in the 1 μ m left and right sides and lead the fine rule figure.Utilize electron beam exposure, carry out alignment, the ICP dry etching, the silicon electricity that obtains nano-scale is led fine rule, and is wide as 30nm-40nm.Through high-temperature thermal oxidation, the silicon electricity is led the fine rule passage and is further obtained restriction.
The quantum dot size of described step (4) and the control of quantity, carry out as follows: the certain thickness medium mask of thermal oxidation (as 20nm), utilize electron beam exposure and ICP lithographic technique to prepare the mask window (as 10nm) of nano-scale width, be used for oxygen and inject.The spacing of window and electricity are led the size that the fine rule width has determined quantum dot, the quantity of the quantity decision quantum dot of adjacent window apertures.
The oxide tunnel junctions of described step (4) is embedded in silicon nanometer electricity as follows and leads in the fine rule: oxonium ion is injected into the silicon electricity by mask window and leads the fine rule bottom, is annotating the oxide barrier that the oxygen zone forms the grid window width.Pass through high-temperature thermal oxidation again, removed the silicon electricity and led the damage of injection zone, the thin-layer silicon zone lattice of annotating upper strata, oxygen district is restored, and it is oxidized that near the silicon electricity mask window is led fine rule top simultaneously, forms the oxide tunnel junctions of the point-contact junction structure of quantum.If the zone below the window is oxidized fully, can't form tunneling barrier.Therefore to control annotating the oxygen degree of depth and dosage, oxidizing temperature and time.
The making of the electrode of described step (5), carry out as follows: deposit medium mask, photoetching deposit polysilicon or metal electrode window, annealing realizes ohmic contact.
In the embodiments of the invention, concrete processing step comprises:
Choose SOI (or SIMOX) sheet of silicon (100nm)-insulating barrier 2 (100nm)-substrate 1 (400 μ m) structure, be injected into top layer silicon surface 10
14/ cm
2Phosphonium ion, the degree of depth is 50nm;
900 ℃ of thermal oxidations obtain the thick silicon oxide layer of 30nm to the thick top layer silicon of 100nm;
It is thick to cover photoresist PMMA 950K 100nm on sample, dries 90 seconds for 180 ℃; Leave 2 * 4 μ m with electron beam exposure
2Window;
The silica of BHF corrosion removing window region;
Remove the photoresist that covers;
To 2 * 4 μ m
2900 ℃ of thermal oxidations of silicon of window region obtain the thick silicon oxide layer of 20nm; Corrode the silica that removes surface coverage with BHF, stay the thick silicon layer of 50nm;
Cover negative photoresist;
Photoetching obtains source-drain area 3,4, electric lead 5 (1 μ m wide * 1 μ m long) and side grid 6 silicon bench figures;
Chemical corrosion silicon obtains silicon bench;
It is thick to cover photoresist PMMA 950K 100nm, dries 90 seconds for 180 ℃;
Leave the alignment figure that electricity is led fine rule 5 (30nm wide * 300nm long) with electron beam exposure;
ICP etches electricity and leads fine rule 5 and side grid 6 graphic structures;
Remove photoresist PMMA;
900 ℃ of thermal oxidations obtain the thick silicon oxide layer of 30nm 7 to top layer silicon, as the mask of oxonium ion injection;
Carve perpendicular to the oxonium ion of electric lead with the electron beam exposure cover and to inject window 8 (20nm wide * 1 μ m is long) figure;
ICP etching oxidation silicon obtains oxonium ion and injects window 8;
Oxonium ion is injected in the silicon quantum fine rule 5;
High-temperature oxydation forms oxide tunnel junctions 9 and silicon quantum dot 10, eliminates implant damage;
Cover photoresist;
Make the electrode window through ray figure of source region 3, drain region 4, side grid 6 by lithography;
BHF erodes silica at electrode 3,4,6 window regions;
Deposit polysilicon or Metal Contact electrode; Short annealing realizes the electrode ohmic contact.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200510086640XA CN100409454C (en) | 2005-10-20 | 2005-10-20 | Quantum confinement of silicon-based single-electron transistors by oxygen implantation |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101359684B (en) * | 2007-08-01 | 2010-06-23 | 中国科学院半导体研究所 | Silicon based single electron transistor of wrap gate control construction and manufacturing method thereof |
| CN101383285B (en) * | 2007-09-05 | 2010-09-22 | 中国科学院微电子研究所 | A method for preparing a single-electron transistor |
| CN101359683B (en) * | 2007-08-01 | 2011-05-04 | 中国科学院半导体研究所 | Silicon based single electron device having double quantum point contact construction and producing method thereof |
| FR3033665A1 (en) * | 2015-03-11 | 2016-09-16 | Commissariat Energie Atomique | SINGLE ELECTRONIC TRANSISTOR AND METHOD FOR MAKING SAME |
| CN110148622A (en) * | 2019-05-06 | 2019-08-20 | 中国科学院半导体研究所 | Foreign atom transistor and preparation method thereof based on silicon nanocrystal constraint |
| CN113725362A (en) * | 2020-05-25 | 2021-11-30 | 国家纳米科学中心 | Carbon nano tube film suspended field effect transistor and transistor manufacturing method |
Family Cites Families (5)
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| JP2586834B2 (en) * | 1994-09-30 | 1997-03-05 | 日本電気株式会社 | Single electronic device and manufacturing method thereof |
| US5604154A (en) * | 1994-10-27 | 1997-02-18 | Nippon Telegraph And Telephone Corporation | Method of manufacturing coulamb blockade element using thermal oxidation |
| US5731598A (en) * | 1995-06-23 | 1998-03-24 | Matsushita Electric Industrial Co. Ltd. | Single electron tunnel device and method for fabricating the same |
| US7122413B2 (en) * | 2003-12-19 | 2006-10-17 | Texas Instruments Incorporated | Method to manufacture silicon quantum islands and single-electron devices |
| TWI227516B (en) * | 2003-12-26 | 2005-02-01 | Ind Tech Res Inst | Nano-electronic devices using discrete exposure method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359684B (en) * | 2007-08-01 | 2010-06-23 | 中国科学院半导体研究所 | Silicon based single electron transistor of wrap gate control construction and manufacturing method thereof |
| CN101359683B (en) * | 2007-08-01 | 2011-05-04 | 中国科学院半导体研究所 | Silicon based single electron device having double quantum point contact construction and producing method thereof |
| CN101383285B (en) * | 2007-09-05 | 2010-09-22 | 中国科学院微电子研究所 | A method for preparing a single-electron transistor |
| FR3033665A1 (en) * | 2015-03-11 | 2016-09-16 | Commissariat Energie Atomique | SINGLE ELECTRONIC TRANSISTOR AND METHOD FOR MAKING SAME |
| US9911841B2 (en) | 2015-03-11 | 2018-03-06 | Commissariat à l'énergie atomique et aux énergies alternatives | Single-electron transistor and its fabrication method |
| CN110148622A (en) * | 2019-05-06 | 2019-08-20 | 中国科学院半导体研究所 | Foreign atom transistor and preparation method thereof based on silicon nanocrystal constraint |
| CN113725362A (en) * | 2020-05-25 | 2021-11-30 | 国家纳米科学中心 | Carbon nano tube film suspended field effect transistor and transistor manufacturing method |
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| CN100409454C (en) | 2008-08-06 |
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