CN1921018A - Shift Register and Liquid Crystal Display with Reduced Coupling Effect - Google Patents

Abstract

A shift register for a liquid crystal display, wherein the output end has a lower coupling effect to provide a better gate drive signal. The output stage circuit of the shift register comprises two switches. The control end of the first switch is coupled to the control end of the second switch. One end of the first switch is used to receive a clock signal, and the other end of the first switch is coupled to one end of the second switch. The other end of the second switch is used to output a gate drive signal. The first switch and the second switch are simultaneously controlled to be turned on and off by a control signal.

Description

Shift Register and Liquid Crystal Display with Reduced Coupling Effect

technical field

The invention relates to a shift register with lower coupling effects. More precisely, the invention relates to a shift register for a liquid crystal display with low coupling effects.

Background technique

Please refer to Figure 1. FIG. 1 is a schematic diagram of a conventional liquid crystal display 100 . The liquid crystal display 100 includes a pixel circuit 110 and a shift register area 120 . The pixel circuit 110 includes a plurality of pixels 111 . The shift register area 120 includes a plurality of shift registers S1-Sn, which are used to receive the voltage level signal VSS, clock signals XCK and CK, and the start signal ST transmitted from the outside, and transmit the gate drive according to the above signals. The signals G1-Gn are given to the pixel circuit 110 . The pixel circuit 110 respectively drives the included pixels 111 according to the gate driving signals G1 - Gn transmitted from the shift register 120 to display images.

Please refer to Figure 2. FIG. 2 is a schematic diagram of a prior art shift register section 120 . As shown in the figure, the shift registers S1-Sn all receive the voltage level signal VSS, and the clock signals XCK and CK. The first shift register S1 is used to receive the start signal ST, and transmit the first gate driving signal G1 to the pixel circuit 110 according to the voltage level signal VSS, clock signals XCK and CK, and also transmit to the second pixel circuit 110 at the same time. A shift register S2. The second shift register S2 is used to receive the first gate driving signal G1, and transmit the second gate driving signal G2 to the pixel area 110 according to the voltage level signal VSS, clock signals XCK and CK, and at the same time It is also transferred to the second shift register S3, and so on. Therefore, each shift register in the shift register area 120 can sequentially send gate driving signals to drive the pixels 111 in the pixel circuit 110 .

Please refer to Figure 3. FIG. 3 is a signal schematic diagram of the shift register section 120 in the prior art. As shown in the figure, when the first shift register S1 receives the start signal, it will start to trigger the action of the shift register area 120 . Start to generate the gate driving signal G1, then generate the gate driving signal G2, and so on. Therefore, the way of generating the gate driving signal in this way can sequentially activate the pixels 111 of the pixel circuit 110 to complete the purpose of displaying images.

Please refer to Figure 4. FIG. 4 is a block diagram of a prior art shift register 400 . The shift register 400 includes switches Q1 - Q7 , control circuits 410 - 430 , and an output stage circuit 440 . The output stage circuit 440 includes a switch Q8. The control circuit 410 controls the potentials of the nodes B and C respectively through the switches Q2 and Q3 according to the clock signal CK. When the control circuit 410 turns on the switches Q2 and Q3 according to the clock signal CK, the potentials of the nodes B and C are pulled to the voltage level VSS. The control circuit 420 controls the potentials of the nodes B and C respectively through the switches Q4 and Q5 according to the clock signal XCK. When the control circuit 420 turns on the switches Q4 and Q5 according to the clock signal XCK, the potentials of the nodes B and C are pulled to the voltage level VSS. The control circuit 430 controls the potentials of the nodes B and C respectively through the switches Q6 and Q7 according to the gate driving signal Gn+1 of the next stage. When the control circuit 430 turns on the switches Q6 and Q7 according to the gate driving signal Gn+1 of the next stage, the potentials of the nodes B and C will be pulled to the voltage level VSS. The output circuit 440 transmits the clock signal CK to the node C as the gate driving signal Gn according to the potentials of the nodes B and C. In this way, when the gate driving signal Gn-1 of the previous stage is input into the shift register 400, the shift register 400 can output the gate driving signal Gn after a delay for a period of time according to the operation mode shown in FIG. 3 .

Please refer to Figure 5. FIG. 5 is a schematic diagram of a gate driving signal Gn of a shift register in the prior art. Because the switch Q8 in the output stage circuit 440 has a parasitic capacitance C1 between the node B and the node A, it will make the current in the node A flow to the node B, and affect the switching action of the switch Q8, resulting in the switch Q8 When it is turned off, the signal cannot be completely turned off, and there is a phenomenon of leakage current. That is to say, when the switch Q8 is in the off state, part of the clock signal CK still flows to the node C, thereby affecting the gate driving signal Gn. In the above-mentioned situation, after the switch Q8 has been used for a long time, the aging phenomenon will occur, and the shape will become more serious. As shown in Figure 5, the gate drive signal Gn will be poor when it is output, causing malfunction and reducing the quality of the display screen. .

Contents of the invention

The present invention provides a shift register for reducing the coupling effect, including a first node; a first switch, including a first end, coupled to the output end of a previous stage shift register; a second end, coupled connected to the first node; and a control terminal coupled to the output terminal of the previous stage shift register; an output terminal; a first control circuit comprising a first input terminal for receiving a first clock signal; a second input end, used to receive a second clock signal; a third input end, coupled to the output end of the previous stage shift register; a first output end, coupled to the first node and a second output terminal coupled to the output terminal of the shift register; a second control circuit comprising: a first input terminal for receiving the second clock signal; a second input terminal coupled to at the output end of the previous stage shift register; a first output end coupled to the first node; and a second output end coupled to the output end of the shift register; a third control circuit, Including: an input terminal coupled to the output terminal of the next stage shift register; a first output terminal coupled to the first node; and a second output terminal coupled to the output terminal of the shift register ; a second switch, including: a first end, used to receive the first clock signal; a second end; and a control end, coupled to the first node; and a third switch, including: a first One terminal is coupled to the second terminal of the second switch; a second terminal is coupled to the output terminal of the shift register; and a control terminal is coupled to the first node.

The present invention also provides a liquid crystal display with reduced coupling effect, which includes a first glass substrate, including a plurality of stacked and coupled shift registers, each shift register includes: a first node; a first switch, including: A first terminal, coupled to the output terminal of a previous stage shift register; a second terminal, coupled to the first node; and a control terminal, coupled to the output terminal of the previous stage shift register ; An output terminal; a first control circuit, including a first input terminal, used to receive a first clock signal; a second input terminal, used to receive a second clock signal; a third input terminal, coupled to at the output end of the previous stage shift register; a first output end coupled to the first node; and a second output end coupled to the output end of the shift register; a second control circuit, Including: a first input end, used to receive the second clock signal; a second input end, coupled to the output end of the previous stage shift register; a first output end, coupled to the first node and a second output terminal coupled to the output terminal of the shift register; a third control circuit comprising: an input terminal coupled to the output terminal of the next-stage shift register; a first output terminal, coupled to the first node; and a second output terminal coupled to the output terminal of the shift register; a second switch comprising: a first terminal for receiving the first clock signal; a second end; and a control end, coupled to the first node; and a third switch, including: a first end, coupled to the second end of the second switch; a second end, coupled to the shift an output terminal of the bit register; and a control terminal coupled to the first node; and a pixel circuit coupled to the output terminal of at least one shift register among the plurality of stacked coupled shift registers; a second a glass substrate; and a liquid crystal layer interposed between the first glass substrate and the second glass substrate.

Description of drawings

FIG. 1 is a schematic diagram of a prior art liquid crystal display.

FIG. 2 is a schematic diagram of a shift register area in the prior art.

FIG. 3 is a signal schematic diagram of a shift register area in the prior art.

FIG. 4 is a block diagram of a prior art shift register.

FIG. 5 is a schematic diagram of gate driving signals of a shift register in the prior art.

FIG. 6 is a schematic diagram of the output stage circuit of the present invention.

FIG. 7 is a schematic block diagram of a shift register of the present invention.

FIG. 8 is a schematic diagram of another embodiment of the output stage circuit of the present invention.

FIG. 9 is a schematic circuit diagram of the shift register of the present invention.

FIG. 10 is a schematic diagram of a liquid crystal display of the present invention.

Description of reference symbols

LCD display 100 1000

Pixel circuit 110 1100

Shift register area 120 1120

Pixel 111

Shift register S1-Sn 400 700

Voltage level signal VSS

Clock signal XCK CK

start signal ST

Gate drive signal G1-Gn

Next level gate drive signal Gn+1

The gate drive signal Gn-1 of the previous stage

Switches Q1-Q23

Control circuit 410 420 430 710 720 730 910 920 930

Output stage circuit 440 600 740 810 940

Parasitic capacitance C1 C2

Glass substrate 1100 1300

Liquid crystal layer 1200

Node A B C D E F G H I J K L M

Detailed ways

Please refer to Figure 6. FIG. 6 is an output stage circuit 600 of the present invention. The output stage circuit 600 includes two switches Q9 and Q10. The control terminals of the switches Q9 and Q10 are coupled to the node F for receiving the control signal of the node F and transmitting the signal of the node E to the node G according to the control signal. In the actual situation, due to the existence of the parasitic capacitance C2 between the node E and the node F, the switching of the signal in the switch Q9 is not good. Therefore, in the present invention, a switch Q10 is coupled to the output terminal of the switch Q9. When the switches Q9 and Q10 are both in the off state, although the parasitic capacitance C2 will couple the signal of the node E to the node F and affect the action of the switch Q9, but because the switch Q10 is still in the off state, therefore, the switch Q9 is in the off state. Noise output due to coupling is not output to node G. Therefore, the present invention achieves the purpose of reducing the coupling effect and affecting the output performance by means of such circuit coupling.

Please refer to Figure 7. FIG. 7 is a block diagram of a shift register 700 of the present invention. The shift register 700 includes switches Q11 - Q19 , control circuits 710 - 730 , and an output stage circuit 740 . The output stage circuit 740 includes two switches Q18 and Q19. The control circuit 710 controls the potentials of the nodes I and J respectively through the switches Q12 and Q13 according to the clock signal CK. When the control circuit 710 turns on the switches Q12 and Q13 according to the clock signal CK, the potentials of the nodes I and J are pulled to the voltage level VSS. The control circuit 720 controls the potentials of the nodes I and J respectively through the switches Q14 and Q15 according to the clock signal XCK. When the control circuit 720 turns on the switches Q14 and Q15 according to the clock signal XCK, the potentials of the nodes I and J are pulled to the voltage level VSS. The control circuit 730 controls the potentials of the nodes I and J respectively through the switches Q16 and Q17 according to the gate driving signal Gn+1 of the next stage. When the control circuit 730 turns on the switches Q16 and Q17 according to the gate driving signal Gn+1 of the next stage, the potentials of the nodes I and J will be pulled to the voltage level VSS. The output circuit 740 transmits the clock signal CK to the node J according to the potentials of the nodes I and J as the gate driving signal Gn. In this way, when the gate driving signal Gn-1 of the previous stage is input into the shift register 700, the shift register 700 can output the gate driving signal Gn after a delay for a period of time according to the operation mode shown in FIG. 3 .

Please refer to Figure 8. FIG. 8 is a schematic diagram of another embodiment 810 of the output stage circuit 740 . As shown in the figure, the output stage circuit 740 can be changed to the output stage circuit 810 and used in the shift register 700 of the present invention. The output stage circuit 810 includes four switches Q20-Q23, and the switches Q20-Q23 are all coupled to the node I for receiving a control signal on the node I to control the switching action. One ends of the switches Q20 and Q22 are commonly coupled to the node H for receiving signals on the node H, and the other ends are respectively coupled to the switches Q21 and Q23 . One ends of the switches Q21 and Q23 are respectively coupled to the switches Q20 and Q22 , and the other ends are commonly coupled to the node J for transmitting signals to the node J. With the above circuit, the function of the output stage circuit 740 is completed.

Please refer to Figure 9. FIG. 9 is a schematic circuit diagram of a shift register 900 of the present invention, which is a detailed illustration of FIG. 7 . The control circuits 910 , 920 , 930 can all be compared to the control circuits 710 , 720 , 730 . The output stage circuit 940 can be compared to the output stage circuit 740 . The rest of the functions are as mentioned above, and will not be repeated here.

Please refer to Figure 10. FIG. 10 is a schematic diagram of a liquid crystal display 1000 of the present invention. As shown in the figure, the liquid crystal display 1000 includes a first glass substrate 1100 , a liquid crystal layer 1200 , and a second glass substrate 1300 . The first glass substrate 1100 includes a pixel circuit 1110 and a shift register area 1120 . The shift register 1120 includes a plurality of cascaded shift registers 900 . The shift register area 1120 can receive an external start signal ST to sequentially send gate driving signals to the pixel circuit 1110 to drive the pixels to display images. Through the improved shift register 900 of the present invention, the noise of the gate driving signal can be reduced, thereby improving the quality of the image display.

In addition, the switches Q9-Q23 described in the present invention can all be realized by thin film transistors.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (18)

1. A shift register that reduces coupling effects, comprising: a first node; a first switch, comprising: a first end, coupled to the output end of a previous stage shift register; a second terminal coupled to the first node; and a control terminal coupled to the output terminal of the previous stage shift register; an output terminal; A first control circuit, comprising: a first input terminal for receiving a first clock signal; a second input terminal for receiving a second clock signal; a third input end coupled to the output end of the previous stage shift register; a first output terminal coupled to the first node; and a second output end coupled to the output end of the shift register; A second control circuit, comprising: a first input terminal for receiving the second clock signal; a second input terminal coupled to the output terminal of the previous stage shift register; a first output terminal coupled to the first node; and a second output end coupled to the output end of the shift register; A third control circuit, comprising: an input terminal coupled to the output terminal of the next stage shift register; a first output terminal coupled to the first node; and a second output end coupled to the output end of the shift register; a second switch, comprising: a first terminal for receiving the first clock signal; a second end; and a control terminal coupled to the first node; and a third switch, comprising: a first terminal coupled to the second terminal of the second switch; a second terminal coupled to the output terminal of the shift register; and A control terminal is coupled to the first node. 2. The shift register according to claim 1, wherein the first, second, and third switches are respectively a thin film transistor, and the control terminals of the first, second, and third switches are respectively a thin film The gate of the transistor. 3. The shift register as claimed in claim 1, wherein the phase difference between the first clock signal and the second clock signal is 180 degrees. 4. The shift register as claimed in claim 1, wherein the first control circuit further comprises: a first switch, comprising: a first terminal coupled to a first node; a second terminal coupled to a common terminal; and a control terminal coupled to the third input terminal of the first control circuit; a second switch, comprising: a first terminal coupled to the first node; a second terminal coupled to the common terminal; and a control terminal coupled to the second input terminal of the first control circuit; a third switch, comprising: a first terminal coupled to the first input terminal of the first control circuit; a second terminal coupled to the first node; and a control terminal coupled to the first input terminal of the first control circuit; a fourth switch, comprising: a first terminal coupled to the first output terminal of the first control circuit; a second terminal coupled to the common terminal; and a control terminal coupled to the first node; a fifth switch, comprising: a first terminal coupled to the second output terminal of the first control circuit; a second terminal coupled to the common terminal; and a control terminal coupled to the first node; and a sixth switch, comprising: a first terminal coupled to the first node; a second terminal coupled to the common terminal; and A control terminal is coupled to the second output terminal of the first control circuit. 5. The shift register as claimed in claim 4, wherein the first, second, third, fourth, fifth and sixth switches are thin film transistors, and the first, second, third, fourth, fifth and sixth switches The control terminal is the gate of a thin film transistor. 6. The shift register as claimed in claim 1, wherein the second control circuit further comprises: a first switch, comprising: a first terminal coupled to the first output terminal of the second control circuit; a second terminal coupled to the second input terminal of the second control circuit; and a control terminal coupled to the first input terminal of the second control circuit; and a second switch, comprising: a first terminal coupled to the second output terminal of the second control circuit; a second terminal coupled to a common terminal; and A control terminal is coupled to the first input terminal of the second control circuit. 7. The shift register as claimed in claim 6, wherein the first and second switches are a thin film transistor, and the control terminals of the first and second switches are gates of a thin film transistor. 8. The shift register as claimed in claim 1, wherein the third control circuit further comprises: a first switch, comprising: a first terminal coupled to the first output terminal of the third control circuit; a second terminal coupled to a common terminal; and a control terminal coupled to the input terminal of the third control circuit; and a second switch, comprising: a first terminal, the second output terminal of the third control circuit; a second terminal coupled to the common terminal; and A control terminal is coupled to the input terminal of the third control circuit. 9. The shift register as claimed in claim 8, wherein the first and second switches are a thin film transistor, and the control terminals of the first and second switches are gates of a thin film transistor. 10. A liquid crystal display that reduces coupling effects, comprising: A first glass substrate, comprising: A plurality of stack-coupled shift registers, each shift register comprising: a first node; a first switch, comprising: a first end, coupled to the output end of a previous stage shift register; a second terminal coupled to the first node; and a control terminal coupled to the output terminal of the previous stage shift register; an output terminal; A first control circuit, comprising: a first input terminal for receiving a first clock signal; a second input terminal for receiving a second clock signal; a third input end coupled to the output end of the previous stage shift register; a first output terminal coupled to the first node; and a second output end coupled to the output end of the shift register; A second control circuit, comprising: a first input terminal for receiving the second clock signal; a second input terminal coupled to the output terminal of the previous stage shift register; a first output terminal coupled to the first node; and a second output end coupled to the output end of the shift register; A third control circuit, comprising: an input terminal coupled to the output terminal of the next stage shift register; a first output terminal coupled to the first node; and a second output end coupled to the output end of the shift register; a second switch, comprising: a first terminal for receiving the first clock signal; a second end; and a control terminal coupled to the first node; and a third switch, comprising: a first terminal coupled to the second terminal of the second switch; a second terminal coupled to the output terminal of the shift register; and a control terminal coupled to the first node; and a pixel circuit, coupled to the output end of at least one shift register among the plurality of stack-coupled shift registers; a second glass substrate; and A liquid crystal layer, the liquid crystal layer is between the first glass substrate and the second glass substrate. 11. The liquid crystal display as claimed in claim 10, wherein the first, second, and third switches are respectively a thin film transistor, and the control terminals of the first, second, and third switches are respectively a thin film transistor. Crystal grid. 12. The liquid crystal display as claimed in claim 10, wherein the phase difference between the first clock signal and the second clock signal is 180 degrees. 13. The liquid crystal display as claimed in claim 10, wherein the first control circuit further comprises: a first switch, comprising: a first terminal coupled to a first node; a second terminal coupled to a common terminal; and a control terminal coupled to the third input terminal of the first control circuit; a second switch, comprising: a first terminal coupled to the first node; a second terminal coupled to the common terminal; and a control terminal coupled to the second input terminal of the first control circuit; a third switch, comprising: a first terminal coupled to the first input terminal of the first control circuit; a second terminal coupled to the first node; and a control terminal coupled to the first input terminal of the first control circuit; a fourth switch, comprising: a first terminal coupled to the first output terminal of the first control circuit; a second terminal coupled to the common terminal; and a control terminal coupled to the first node; a fifth switch, comprising: a first terminal coupled to the second output terminal of the first control circuit; a second terminal coupled to the common terminal; and a control terminal coupled to the first node; and a sixth switch, comprising: a first terminal coupled to the first node; a second terminal coupled to the common terminal; and A control terminal is coupled to the second output terminal of the first control circuit. 14. The liquid crystal display as claimed in claim 13, wherein the first, second, third, fourth, fifth, and sixth switches are thin film transistors, and the first, second, third, fourth, fifth, and sixth switches are The control terminal is a gate of a thin film transistor. 15. The liquid crystal display as claimed in claim 10, wherein the second control circuit further comprises: a first switch, comprising: a first terminal coupled to the first output terminal of the second control circuit; a second terminal coupled to the second input terminal of the second control circuit; and a control terminal coupled to the first input terminal of the second control circuit; and a second switch, comprising: a first terminal coupled to the second output terminal of the second control circuit; a second terminal coupled to a common terminal; and A control terminal is coupled to the first input terminal of the second control circuit. 16. The liquid crystal display as claimed in claim 15, wherein the first and second switches are a thin film transistor, and the control terminals of the first and second switches are gates of a thin film transistor. 17. The liquid crystal display as claimed in claim 10, wherein the third control circuit further comprises: a first switch, comprising: a first terminal coupled to the first output terminal of the third control circuit; a second terminal coupled to a common terminal; and a control terminal coupled to the input terminal of the third control circuit; and a second switch, comprising: a first terminal, the second output terminal of the third control circuit; a second terminal coupled to the common terminal; and A control terminal is coupled to the input terminal of the third control circuit. 18. The liquid crystal display as claimed in claim 17, wherein the first and second switches are a thin film transistor, and the control terminals of the first and second switches are gates of a thin film transistor.

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