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CN1917198A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1917198A
CN1917198A CNA2006101085017A CN200610108501A CN1917198A CN 1917198 A CN1917198 A CN 1917198A CN A2006101085017 A CNA2006101085017 A CN A2006101085017A CN 200610108501 A CN200610108501 A CN 200610108501A CN 1917198 A CN1917198 A CN 1917198A
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CN
China
Prior art keywords
semiconductor device
power transistor
region
bonding pad
bonding
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Pending
Application number
CNA2006101085017A
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English (en)
Inventor
小池信也
松下司
佐藤仁久
大川启一
锦泽笃志
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Renesas Technology Corp
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Renesas Technology Corp
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Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Publication of CN1917198A publication Critical patent/CN1917198A/zh
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Abstract

需要提供一种能够降低半导体器件中的功率晶体管的导通电阻的技术，该半导体器件将功率晶体管和控制集成电路集成到单一半导体芯片中。另外需要提供一种能够减小半导体器件的芯片尺寸的技术。一种半导体芯片包括用于形成功率晶体管的功率晶体管形成区域、用于形成逻辑电路的逻辑电路形成区域和用于形成模拟电路的模拟电路形成区域。在功率晶体管形成区域中形成焊盘。该焊盘和引线通过接线柱来连接，该接线柱的横截面大于导线的横截面。另一方面，通过导线29连接键合焊盘。

Description

半导体器件及其制造方法
相关申请的交叉引用
本申请要求于2005年8月16日提交的日本专利申请No.2005-235778的优先权，据此将其内容通过参考引入本申请。
技术领域
本发明涉及半导体器件及其制造技术。更具体地，本发明涉及一种在单一半导体芯片上形成功率晶体管和控制集成电路的半导体器件，以及一种可有效应用于半导体器件的制造技术的技术。
背景技术
所谓的分立功率晶体管由独立的功率晶体管组成并且使用厚膜布线，因为不需要形成复杂的布线。厚膜布线的使用增加布线的横截面，使得可以降低导通电阻。此外，厚膜布线的使用可以减小当把金导线键合到键合焊盘时可能造成的键合损伤。这使得可以在键合焊盘下方布置功率晶体管。
例如，日本未审专利公开No.2000-49184(专利文献1)公开了用于分立功率晶体管的技术。该技术使连接到功率晶体管的源电极的键合导线变粗并使连接到栅电极的键合导线变细。
在日本未审专利公开No.2004-153234(专利文献2)中公开的技术使用厚金属带来在功率晶体管的源电极和外部端子之间进行连接，并且使用薄金属带来在栅电极和外部端子之间进行连接。
可获得一种单独封装的半导体器件，它密封其上形成有功率晶体管的半导体芯片和其上形成有逻辑电路的半导体芯片。这种半导体器件涉及在日本未审专利公开No.Hei 11(1999)-204724(专利文献3)中描述的技术。该技术使用粗键合导线来连接用于形成功率晶体管的半导体芯片，并使用细键合导线来连接用于形成逻辑电路的半导体芯片。
此外，有一种在单一半导体芯片上形成功率晶体管和控制集成电路的技术。这种技术使用键合导线来将半导体芯片与外部端子(引线)连接。该技术不在键合焊盘下方形成器件，使得防止键合期间的损伤。
[专利文献1]日本未审专利公开No.2000-049184
[专利文献2]日本未审专利公开No.2004-153234
[专利文献3]日本未审专利公开No.Hei11(1999)-204724
发明内容
近年来，存在对减小用于安装半导体器件的面积的需求或者对简化装配的用户需求。为了这个目的，一种解决方案是将功率晶体管和控制集成电路(诸如逻辑电路和模拟电路)形成在单一半导体芯片上。
当把功率晶体管和控制集成电路形成在一个半导体芯片中时，使用精细布线来进行控制集成电路的高集成化。为了形成该精细布线，半导体制造工艺使用利用铝膜的薄膜布线技术。
但是，由于将功率晶体管和控制集成电路安装在一个半导体芯片上，所以将精细布线用于控制集成电路比将精细布线用于功率晶体管更为重要。期望功率晶体管使用厚膜布线，因为可以增加布线横截面并且可以降低导通电阻。但是，对于控制集成电路的高集成化，使用薄膜布线可以减小布线横截面并且增加导通电阻。也就是，将功率晶体管和控制集成电路集成到单一芯片中会增加功率晶体管的导通电阻和功率消耗。
由于分立功率晶体管可以使用厚膜布线，所以通过厚膜布线可以缓和来自键合焊盘的键合损伤。因此，即使当功率晶体管布置在键合焊盘下方时也不会发生问题。但是，当把功率晶体管和控制集成电路集成到单一芯片中时，功率晶体管需要用薄膜布线而不是厚膜布线。薄膜布线减小了对键合焊盘的键合损伤的抵抗力。作为结果，不能将功率晶体管布置在键合焊盘下方，增加了半导体芯片面积，导致问题的发生。
本发明的目的在于，提供一种能够降低半导体器件中的功率晶体管的导通电阻的技术，该半导体器件将功率晶体管和控制集成电路集成到单一半导体芯片中。
本发明的另一个目的在于，提供一种能够降低半导体器件的芯片尺寸的技术，该半导体器件将功率晶体管和控制集成电路集成到单一半导体芯片中。
通过参照以下描述和附图，可以容易地确定本发明的这些以及其它目的和新颖特征。
以下概述在本申请中公开的发明的代表性实施例。
一种根据本发明的半导体器件包括：(a)半导体芯片；(b)形成在该半导体芯片上方的第一区域和第二区域；(c)形成在该第一区域中的多个第一键合焊盘；以及(d)形成在该第二区域中的多个第二键合焊盘。该半导体器件进一步包括：(e)多个第一引线和多个第二引线；(f)第一导体，电连接第一键合焊盘与第一引线；以及(g)第二导体，电连接第二键合焊盘与第二引线。第一导体的横截面大于第二导体的横截面。
根据本发明的半导体器件制造方法，包括以下步骤：(a)在具有多个第一引线和多个第二引线的引线框架上方，安装具有第一区域和第二区域的半导体芯片；以及(b)在形成在第一区域中的第一键合焊盘和第一引线上方形成连接材料。该方法进一步包括以下步骤：(c)经由接线柱(clip)电连接第一键合焊盘与第一引线；以及(d)对半导体芯片应用热处理。此外，该方法包括步骤(e)在步骤(d)之后，经由导线电连接形成在第二区域中的第二键合焊盘和第二引线。
以下概述由在本申请中公开的发明的代表性方面所提供的效果。
在将功率晶体管和控制集成电路集成到单一半导体芯片中的半导体器件中，代替导线而使用接线柱来电连接在功率晶体管形成区域中的键合焊盘与外部端子(引线)。该接线柱具有比导线大的横截面。使用该接线柱可以降低功率晶体管的导通电阻并因此减小其功率消耗。由于在功率晶体管形成区域中，代替导线而使用接线柱来连接键合焊盘与引线，所以可减小用于该芯片的布线电阻并抑制键合损伤。因此，可以将诸如功率晶体管的器件布置在键合焊盘之下，使得可以将半导体芯片小型化。
附图说明
图1表示硬盘设备的电路块；
图2是表示根据本发明实施例的半导体芯片的布局例子的平面图；
图3是表示半导体芯片的另一布局例子的平面图；
图4是表示半导体芯片的又一布局例子的平面图；
图5是表示将半导体芯片安装在引线框架上的例子的平面图；
图6是表示将半导体芯片安装在引线框架上的另一例子的平面图；
图7是沿图5的A-A线所取的横截面图；
图8说明导线键合；
图9说明接线柱键合；
图10是表示根据本发明实施例的半导体器件的制造工艺的流程图；
图11是示意性地表示根据本发明实施例的半导体器件的制造工艺的平面图；
图12是继图11之后的示意性地表示该半导体器件的制造工艺的平面图；
图13是继图12之后的示意性地表示该半导体器件的制造工艺的平面图；
图14是表示与图10不同的制造工艺的流程图；
图15是示意性地表示根据该实施例的半导体器件的制造工艺的平面图；
图16是继图15之后的示意性地表示该半导体器件的制造工艺的平面图；以及
图17是继图16之后的示意性地表示该半导体器件的制造工艺的平面图。
具体实施方式
以下描述根据需要而分成多个部分或进一步实施例的实施例。除非具体指明，否则它们彼此相关并且一个是另一个的部分或全部的修改、细节、补充等。
以下实施例可以提及元件数目等(包括项数、数值、数量和范围)。这些实施例不限于特定值并且可以大于或等于或者小于或等于该特定值，除非例如当明确指定为特定值时以及当原则上该实施例显然限于特定值时。
此外，在以下实施例中，显然的是，构成元件(包括要素步骤等)不一定是必需的，除非当明确指定它们时以及当原则上明显需要它们时。
类似地，以下实施例可以提及构成元件等的形状、位置关系等。在这样的情况下，假定该描述实际上包含接近于或类似于该形状等的那些形状等，除非例如当明确指定该形状、位置关系等时以及当原则上应明显避免它们时。这也适用于上述数值和范围。
参照附图将进一步详细地描述本发明的实施例。贯穿用于描述实施例的所有附图，相同的部件用相同的参考标号来表示并且为了简便起见省略重复描述。
本实施例将根据实施例的半导体器件应用于硬盘设备。图1表示该硬盘设备的电路块。在图1中，该硬盘设备包括MCU(微控制器单元)1、HDD马达驱动器IC 2、主轴马达3、Rsns 4和VCM(音圈马达)5。
MCU 1是控制整个硬盘设备的微型计算机。MCU 1构造为执行数字信号处理。HDD马达驱动器IC 2构造为能够控制主轴马达3的旋转，控制连接到VCM 5的磁头臂(head arm)的定位，监视电源电压，以及产生特定电压。HDD马达驱动器IC 2由一个半导体芯片组成，其中形成功率晶体管、逻辑电路(数字电路)和模拟电路。在本说明书中，将逻辑电路和模拟电路共同称作控制集成电路。也就是，控制集成电路表示形成在HDD马达驱动器IC 2中的逻辑电路和模拟电路。根据本实施例的半导体器件被应用于该HDD马达驱动器IC 2。
主轴马达3是用于使构成硬盘的盘旋转的马达。Rsns 4检测流经主轴马达3的电流。VCM 5连接到用于向硬盘读或写的磁头臂，并且定位该磁头臂。
如上所述构造硬盘设备。以下更详细地描述HDD马达驱动器IC2的构造。HDD马达驱动器IC 2包括功率晶体管单元、逻辑电路单元和模拟电路单元。功率晶体管单元包含形成在其中的功率晶体管6和功率晶体管7两者。功率晶体管6连接到主轴马达3并且用作驱动电路来向主轴马达3供给电流。另一方面，功率晶体管7连接到VCM 5并且用作驱动电路来向VCM 5供给电流。
逻辑电路(数字电路)单元包括数字PWM系统8、串行I/O 9和控制逻辑单元10。数字PWM系统8控制主轴马达3以防止突然的电流变化，使得主轴马达3可以平稳地操作。数字PWM系统8可以消除主轴马达3的不规则旋转，并且抑制主轴马达3在旋转时的噪声。数字PWM系统8基于来自Rsns 4的结果来控制主轴马达3，该Rsns 4检测供给到主轴马达3的电流。也就是，将Rsns 4的检测结果反馈到数字PWM系统8，然后该数字PWM系统8控制主轴马达3。
串行I/O 9用来在MCU 1与HDD马达驱动器IC 2之间输入或输出数字信号。例如，将从MCU 1输出的数字信号输入到串行I/O 9。该数字信号从串行I/O 9输出并且经由D/A转换器转换成模拟信号。通过控制逻辑电路10的切换操作，将转换的模拟信号传送到功率晶体管7，以向VCM 5供给电流。以此方式，VCM 5操作以将磁头臂移动到硬盘的特定位置。在数字信号从串行I/O 9输出并且转换成模拟信号的同时，控制逻辑单元10构造为执行切换操作，将该模拟信号传送到功率晶体管7。在诸如电源的突然故障的异常情况下，控制逻辑单元10断开与串行I/O 9的连接，使得不将信号从串行I/O 9传送到功率晶体管7。控制逻辑单元10执行切换操作，以将来自作为模拟电路的收回(retract)控制单元11的信号传送到功率晶体管7。以此方式，连接到功率晶体管7的VCM 5操作以将磁头臂收回到安全位置。控制逻辑单元10由数字电路组成并且用作将功率晶体管7与来自串行I/O 9或来自收回控制单元11的信号连接的开关。也就是，控制逻辑单元10具有用来控制供给到VCM 5的电流并操作磁头臂的功能。
除了上述收回控制单元11之外，模拟电路单元包括磁头速度检测单元12、冲击检测单元13、3.3V串行调节器14、切换调节器15、负电压产生调节器16、功率监视器17、通电复位单元18以及升压器19。
磁头速度检测单元12构造为检测VCM 5所连接到的磁头臂的速度。基于由磁头臂检测单元12检测的速度来控制VCM 5。以此方式，可以精确地控制磁头臂。冲击检测单元13检测施加到硬盘设备的冲击使得当出现施加到硬盘设备的冲击时立即停止该系统。
3.3V串行调节器14从5V或12V的电源电压产生3.3V的电压。切换调节器15从电源电压产生1.1V至2.5V的电压。负电压产生调节器16从电源电压产生负电压。例如将从这些调节器产生的电压供给到MCU 1。在许多情况下，用于调节器的系统和电压取决于根据客户规范的IC。
功率监视器17具有监视电源电压中是否出现错误的功能。例如，当电源电压经受小于或等于容许范围的变化时，通电复位单元18使HDD马达驱动器IC 2向MCU 1输出复位信号。升压器19是电荷泵电路，其产生大于或等于电源电压的电压。例如，将在升压器19中产生的电压供给到功率晶体管6和7的栅电极。将在升压器19中产生的电压用于HDD马达驱动器IC 2中的电路。
在HDD马达驱动器IC 2中，形成有功率晶体管和由逻辑电路和模拟电路组成的控制集成电路。这些电路形成在一个半导体芯片中。以下描述其中形成HDD马达驱动器IC 2的半导体芯片的布局。
图2示出其中形成HDD马达驱动器IC 2的半导体芯片20的布局例子。如图2所示，半导体芯片20设置有功率晶体管形成区域(第一区域)21、逻辑电路形成区域(第二区域)22以及模拟电路形成区域(第二区域)23。在功率晶体管形成区域21中形成功率晶体管。在逻辑电路形成区域22中形成数字电路。在模拟电路形成区域23中形成模拟电路。
沿半导体芯片20的外围形成键合焊盘(第二键合焊盘)24。该键合焊盘24连接到逻辑电路或模拟电路，但不形成在逻辑电路形成区域22和模拟电路形成区域23上。原因如下。诸如金导线的导线(第二导体)键合到键合焊盘24。当在键合焊盘24下方形成构成逻辑电路或模拟电路的器件时，键合期间的冲击可能会损伤器件。为了避免这种情况，在逻辑电路形成区域22和模拟电路形成区域23的外部形成键合焊盘24。
在功率晶体管形成区域21中，形成有连接到功率晶体管的焊盘(第一键合焊盘)25。当使用已知技术在如图2所示的功率晶体管形成区域21中形成焊盘25时，在焊盘25下方不布置器件。形成对比，本实施例在焊盘25下方布置器件。这是根据本实施例的半导体器件的特征之一。在功率晶体管形成区域21中形成焊盘25。在该焊盘25下方形成器件。这可以减小半导体芯片20的面积。也就是，可以减小半导体芯片20的尺寸。可以增加从一个半导体晶片制造的半导体芯片20的数目并降低半导体芯片20的成本。当在功率晶体管形成区域21中形成焊盘25时，经由金导线等键合焊盘25可能会损伤焊盘25下方的功率晶体管。但是，本实施例避免了经由金导线等对形成在功率晶体管形成区域21中的焊盘25进行导线键合。也就是，经由具有比导线大的横截面的接线柱(第一导体)连接形成在功率晶体管形成区域21中的焊盘25，使得降低功率晶体管的导通电阻，稍后将进行描述。经由接线柱的连接不向焊盘25施加冲击并因此可以抑制对形成在焊盘25下方的功率晶体管的损伤。为此，在功率晶体管形成区域21中形成焊盘25，以防止焊盘所占的面积增加。
形成在功率晶体管形成区域21中的焊盘25具有比沿半导体芯片20的外围形成的键合焊盘24大的面积。这是因为增加焊盘25与接线柱之间的连接面积可以使功率晶体管的导通电阻减小。焊盘25的最小间距比键合焊盘24的最小间距大。这是因为连接到焊盘25的接线柱的横截面大于连接到键合焊盘24的金导线(键合导线)的横截面，并且需要保护相邻焊盘25以免发生短路。为此，焊盘25的最小间距大于键合焊盘24的最小间距。从另一个观点出发，连接到键合焊盘24的控制集成电路的器件具有比连接到焊盘25的功率晶体管的器件更高的集成度。键合焊盘24的最小间距小于焊盘25的最小间距。
功率晶体管对于功率消耗具有大的影响，并因此需要降低半导体芯片20的导通电阻。从而，本实施例增加待连接到功率晶体管的焊盘25的面积，并使用具有大横截面的接线柱进行连接。另一方面，需要增加由逻辑电路和模拟电路组成的控制集成电路的集成度。为此，本实施例减小待连接到控制集成电路的键合焊盘24的尺寸，并减小最小间距。由于将待连接到控制集成电路的键合焊盘24形成得较小，所以使用具有较小横截面的金导线(键合导线)进行连接来防止在相邻键合焊盘24之间的短路。
图3示出了半导体芯片20的另一种布局例子。同样在图3中，在半导体芯片20上形成有功率晶体管形成区域21、逻辑电路形成区域22和模拟电路形成区域23。在对应的形成区域中形成功率晶体管、逻辑电路和模拟电路。类似于图2，沿半导体芯片20的外围形成键合焊盘24，并在功率晶体管形成区域21中形成焊盘25。键合焊盘24连接到由逻辑电路和模拟电路组成的控制集成电路。焊盘25连接到功率晶体管。
同样根据图3中的布局，在功率晶体管形成区域21中形成焊盘25使得减小半导体芯片20的尺寸。将焊盘25的面积制成大于键合焊盘24的面积。另外，使用接线柱来连接焊盘25。以此方式，可以降低功率晶体管的导通电阻。
图4是示出了半导体芯片20的又一布局例子的平面图。将图4中的半导体芯片20与图2和图3所示的半导体芯片类似地构造，但在构成元件的布置上与图2和图3中的不同。同样在图4中，在功率晶体管形成区域21中形成焊盘25，使得减小半导体芯片20的尺寸。将焊盘25的面积制成大于键合焊盘24的面积。另外，使用接线柱来连接焊盘25。以此方式，可以降低功率晶体管的导通电阻。
如图2至图4所示，对于半导体芯片20可根据适用产品而利用各种布局。在任何情况下，该布局能够减小半导体芯片20的尺寸并且降低功率晶体管的导通电阻。
图5示出了将图2所示的半导体芯片20安装在引线框架26上的例子。如图5所示，在半导体芯片20的功率晶体管形成区域21中形成焊盘25。使用接线柱28将焊盘25与形成在引线框架26中的引线(第一引线)27a连接。另外，沿半导体芯片20的外围形成键合焊盘24。使用导线29将键合焊盘24与形成在引线框架26中的引线(第二引线)27b连接。
由于使用接线柱28将焊盘25与引线27a连接，所以可降低连接到焊盘25的功率晶体管的导通电阻。也就是，将焊盘25的面积形成得大于键合焊盘24的面积。经由接线柱28将焊盘25和引线27a彼此连接，该接线柱28的横截面大于导线29的横截面。这使得可以降低焊盘25与引线27a之间的连接电阻。因此，可以降低连接到焊盘25的功率晶体管的导通电阻。
常规地，使用导线将键合焊盘连接到功率晶体管。但是，由于导线具有小的横截面，所以键合焊盘与引线之间的连接电阻增加功率晶体管的导通电阻。功率晶体管的大导通电阻增加整个半导体器件的功率消耗。
为了解决这个问题，本实施例使用接线柱28代替导线来将焊盘25与待连接到功率晶体管的引线27a连接。接线柱28具有比导线大的横截面。电阻与横截面尺寸成反比。使用具有大横截面的接线柱28可以降低功率晶体管的导通电阻。用于接线柱28的材料可以包括例如铜和铝，其电阻率相对较小。
本实施例使用接线柱28将焊盘25连接到引线27a。经由接线柱28的连接可以防止由经由导线的连接而产生的键合损伤。即使当把焊盘25形成在其中形成功率晶体管的功率晶体管形成区域的正上方时，经由接线柱28的连接也不给功率晶体管带来任何损伤。从而，可以将焊盘25布置在功率晶体管形成区域中。为此，与将焊盘25布置在功率晶体管形成区域的外部的情况相比，可以减小半导体芯片20的尺寸。由于本实施例使用接线柱28将焊盘25连接到待连接到功率晶体管的引线27a，所以不仅可以降低功率晶体管的导通电阻，而且可以减小半导体芯片的尺寸。
本实施例可以减小焊盘25与引线27a之间的连接的电阻率。因此，当把整个功率晶体管电路的导通电阻保持为特定值时，还可以提高功率晶体管本身的集成度。也就是，由于可以减小在焊盘25与引线27a之间的连接的电阻率，因此即使当增加功率晶体管本身(包括布线)的集成度时导通电阻也不超过特定值。一般来说，减小器件常数，即，功率晶体管本身的面积，可以增加导通电阻。但是，本实施例可以减小焊盘25与引线27a之间的连接的电阻率。功率晶体管面积可以随着电阻率的降低而减小。以此方式，可以提高功率晶体管集成度并且可以减小半导体芯片20，而不使导通电阻从特定值增加。当导通电阻不需要过多地减小时，本实施例可以进一步减小半导体芯片20以降低成本。
导线29由例如金导线制成，用来连接键合焊盘24与沿半导体芯片20的外围形成的引线27b。键合焊盘24连接到逻辑电路和模拟电路(控制集成电路)。当连接导线29时可能会使键合焊盘24经受键合损伤。为此，在由逻辑电路形成区域22和模拟电路形成区域23组成的控制集成电路形成区域的外部形成键合焊盘24。
控制集成电路需要许多I/O管脚，即键合焊盘，以便响应于市场对多样化功能的需求。为此，必需提高键合焊盘间隔之间的集成度。因此，使用具有小横截面的导线29将键合焊盘24与引线27b连接。当使用接线柱将键合焊盘24与引线27b连接时，接线柱具有大横截面，使得必需扩大相邻键合焊盘24之间的间隔。从而，半导体芯片20的尺寸增加，使得难以提高集成度。作为对此的解决方案，使用具有小横截面的导线29将键合焊盘24与引线27b连接以保持集成度。
功率晶体管需要降低其导通电阻。控制集成电路需要提高其集成度。当需要将功率晶体管和控制集成电路形成到一个半导体芯片中时，本实施例使用具有大横截面的接线柱连接功率晶体管并且使用导线连接控制集成电路。以此方式，可以降低功率晶体管的导通电阻并且可以减小半导体芯片的尺寸。从减小半导体芯片的尺寸的角度出发，必需提高功率晶体管和控制集成电路的集成度。但是，从降低功率晶体管的导通电阻的角度出发，期望不增加功率晶体管的集成度。如上所述，通过将接线柱用于功率晶体管连接并将导线用于控制集成电路连接，可以解决该相互矛盾的要求。因此，根据本实施例的半导体器件可以同时满足该相互矛盾的要求，并且是高度可行和有用的。
图6示出了将半导体芯片20安装在引线框架26上的另一个例子。图6与图5的不同之处如下。在图5中，使用一个接线柱28将多个焊盘25(图5中为三个焊盘)连接到一条引线27a。在图6中，形成一个焊盘30而不是多个焊盘25。焊盘30具有比多个焊盘35大的面积。使用接线柱28将焊盘30与引线27a连接。根据本构造，焊盘30的面积大于多个焊盘25的总面积，进一步降低了焊盘30与引线27a之间的连接电阻。另外，可以改善降低芯片上的布线电阻的效果，进一步降低功率晶体管的导通电阻。
图7是沿图5的A-A线所取的横截面图。如图7所示，在半导体衬底31的功率晶体管形成区域中形成功率晶体管32。经由层间绝缘膜在功率晶体管32上形成第一布线33。经由在层间绝缘膜中形成的栓塞(plug)电连接功率晶体管32和该第一布线。经由层间绝缘膜在第一布线33上方形成第二布线34。经由层间绝缘膜在第二布线34上方形成第三布线35(键合焊盘)。使用栓塞将第一布线33与第二布线34连接并且将第二布线34与第三布线35连接。在布线35之上形成钝化膜36，并且该钝化膜36用作表面保护膜。钝化膜36设置有使第三布线35露出的孔37。在从孔37露出的第三布线35之上形成表面处理膜38。该表面处理膜38是由镍、金和钯膜组成的多层膜。在表面处理膜38之上形成连接材料39。形成表面处理膜38以改善连接材料39与第三布线35之间的连接性。连接材料39由焊料或导电树脂浆料(paste)制成。将接线柱40连接到连接材料39。也就是，经由连接材料39将作为键合焊盘的第三布线35电连接到接线柱40。根据本实施例，在功率晶体管32正上方形成接线柱40。与在功率晶体管形成区域外部的区域中形成接线柱40的情况相比，本实施例可以减小半导体芯片尺寸。
在导线键合区域中形成第三布线(键合焊盘)35。在第三布线35之下不形成器件或布线。在第三布线35之上形成钝化膜36，其中形成孔41以对其开口。在孔41的底部处露出第三布线35。将由例如金导线制成的导线42连接到从孔41露出的第三布线35。由于在导线键合期间损伤导线键合区域，所以不在导线键合区域中形成器件或布线。
参照图8和图9，以下描述为什么不在导线键合区域中形成器件或布线以及在接线柱40的形成区域之下形成功率晶体管。
图8示出了使用金导线43导线键合到键合焊盘44。当在图8中将导线43连接到键合焊盘44时，例如施加200℃至250℃的热负荷，以及施加1W或更少的超声。使用键合工具施加20g至50g的负荷进行键合。此时，键合工具施加的负荷可能会损伤其中形成键合焊盘44的半导体衬底。当在导线键合区域之下形成器件时，导线键合可能会损伤和破坏器件。与分立晶体管不同，即使将功率晶体管形成区域扩大到一定程度，IC技术也注重提高整个芯片集成度。为此，采用薄膜Al工艺来实现精细布线，并提高控制集成电路的集成度。布线和器件被进行精细的处理并且容易被损伤。因此，不在导线键合区域之下形成器件。在其它区域中形成控制集成电路。
图9示出了使用接线柱45连接到焊盘46。在图9中，接线柱45和焊盘46经由连接材料47而彼此连接。作为连接材料，可以使用焊料来施加300℃至350℃的热负荷。可选地，可以使用导电树脂浆料来施加150℃至200℃的热负荷。与导线键合不同，不施加负荷来将接线柱45安装在连接材料47上。由于不向接线柱45施加负荷，所以不会对其中形成焊盘46的半导体衬底造成损伤。当在接线柱45之下形成功率晶体管时，不会对功率晶体管造成损伤。
为此，不在导线键合区域中形成器件或布线，并且在接线柱45的形成区域之下形成功率晶体管。通过形成多个栓塞用于与作为用于导线键合区域的键合焊盘的第三布线35(下层布线)进行连接，可以提供抵抗损伤的加强作用。在导线键合区域之下可以形成控制集成电路。在该情况下，可以使半导体芯片进一步小型化。
图7说明功率晶体管形成区域和导线键合形成区域。设置有HDD马达驱动器IC的半导体芯片还包括控制集成电路形成区域。在控制集成电路形成区域中形成控制集成电路。具体来说，在控制集成电路中形成有由MOSFET(MISFET)、电阻器和双极晶体管组成的晶体管和由金属膜组成的布线。下面将在功率晶体管形成区域中形成的功率晶体管与在控制集成电路形成区域中形成的晶体管进行比较。在功率晶体管形成区域中形成的功率晶体管具有大于或等于在控制集成电路形成区域中形成的晶体管的最小栅极长度。功率晶体管形成区域具有大于控制集成电路形成区域的最小栅极宽度。这是因为控制集成电路的集成度高于功率晶体管。由于相同的原因，在功率晶体管形成区域中形成的布线具有大于在控制集成电路形成区域中形成的布线的宽度和最小间隔。
参照附图，以下描述根据本实施例的半导体器件的制造方法。图10是表示根据本实施例的半导体器件的制造工艺的流程图。
如图11所示，在其中形成多个引线27a和27b的引线框架26上安装半导体芯片20(图10中的步骤S101)。此时，在半导体芯片20中形成控制集成电路形成区域并且包括功率晶体管形成区域21、逻辑电路形成区域22和模拟电路形成区域23。在相应区域中形成功率晶体管、逻辑电路和模拟电路。沿着半导体芯片20的外围形成有待连接到逻辑电路或模拟电路的键合焊盘24。在功率晶体管形成区域中形成焊盘25并且将该焊盘25连接到功率晶体管。也就是，在焊盘25下方紧接着形成诸如功率晶体管的器件。焊盘25具有大于键合焊盘24的面积。
将连接材料涂覆到形成在功率晶体管形成区域中的焊盘25并且涂覆到连接到焊盘25的引线27a(图10中的步骤S102)。该连接材料例如由焊料或导电树脂浆料制成。在形成连接材料之前，可以形成表面处理膜，以改进连接材料、焊盘25和引线27a之间的粘附性。表面处理膜例如是由镍、金和钯膜组成的多层膜。
如图12所示，将接线柱28安装在涂覆有连接材料的焊盘25上和涂覆有连接材料的引线27a上(图10中的步骤S103)。以此方式，接线柱28将焊盘25与引线27a电连接。接线柱28具有大于导线的横截面并且可以降低焊盘25与引线27a之间的连接的电阻率。这使得可以降低连接到焊盘25的功率晶体管的导通电阻。接线柱28由具有低电阻率的成分诸如铜和铝制成。
然后将回流工艺应用于安装在引线框架26上的半导体芯片20，以将连接材料、焊盘25和引线27a进行连接(图10中的步骤S104)。当连接材料是焊料时执行回流工艺。热处理温度范围例如从300℃至350℃。当连接材料是导电浆料时，执行烘烤工艺而不是回流工艺。热处理温度范围例如从150℃至200℃。
如图13所示，使用导线29连接键合焊盘24和沿半导体芯片20的外围形成的引线27b(图10中的步骤S105)。将树脂施加到半导体芯片20以密封该半导体芯片(图10中的步骤S106)。根据本实施例，一些部分使用刚性大于导线29的刚性的接线柱28进行连接。当将树脂施加到半导体芯片20时，可以保护接线柱28免于因在通过接线柱28连接的功率晶体管形成区域中施加树脂而引起变形。可以防止由于接线柱28的变形而引起的在相邻接线柱之间的短路。之后，通过从树脂密封部分露出的引线27a和27b形成端子(图10中的步骤S107)。
以此方式，可以形成根据本实施例的半导体器件。当通过导线键合工艺形成的金导线不对接线柱连接期间的热负荷或传输造成妨碍时，优选地使用以下过程来制造根据本实施例的半导体器件。尽管根据上述实施例连接接线柱然后执行导线键合，但可以执行导线键合然后连接接线柱。图14是示出与图10中的制造工艺不同的制造工艺的流程图。
如图15所示，在其中形成多个引线27a和27b的引线框架26上安装半导体芯片20(图14中的步骤S201)。如图16所示，使用导线29连接键合焊盘24和沿半导体芯片20的外围形成的引线27b(图14中的步骤S202)。将连接材料涂覆到形成在功率晶体管形成区域中的焊盘25并且涂覆到连接到焊盘25的引线27a(图14中的步骤S203)。如图17所示，将接线柱28安装在涂覆有连接材料的焊盘25上和涂覆有连接材料的引线27a上(图14中的步骤S204)。以此方式，接线柱28将焊盘25与引线27a电连接。然后将回流工艺应用于在引线框架26上安装的半导体芯片20，以将连接材料、焊盘25和引线27a进行连接(图14中的步骤S205)。利用树脂密封半导体芯片20(图14中的步骤S206)，并且然后形成端子(图14中的步骤S207)。该方法也可以制造根据本实施例的半导体器件。
尽管已经描述了由本发明人做出的本发明的特定优选实施例，但应清楚地理解到，本发明并不限于此，而是可以在本发明的精神和范围内进行另外的各种实施。
使用硬盘设备作为例子描述了本实施例，但并不限于此。例如，可以将本实施例应用于用于车辆引擎控制和ABS系统的ASIC产品。
本发明可以被广泛地用于制造半导体器件的制造工业。
附图参考标记注释
图1
3——主轴马达
8——数字PWM系统
9——串行I/O
10——控制逻辑电路
11——收回控制电路
12——磁头速度检测单元
13——冲击检测单元
14——3.3V串行调节器
15——切换调节器
16——负电压产生调节器
17——功率监视器
18——通电复位单元
19——升压器
图5
20——半导体芯片
21——功率晶体管形成区域
22——逻辑电路形成区域
23——模拟电路形成区域
24——键合焊盘
25——焊盘
26——引线框架
27a、27b——引线
28——芯片
29——导线
图7
功率晶体管形成区域
导线键合区域
图10
开始
S101——管芯键合
S102——涂覆连接材料
S103——安装接线柱
S104——回流
S105——导线键合
S106——密封
S107——形成端子
结束
图14
开始
S201——管芯键合
S202——导线键合
S203——涂覆连接材料
S204——安装接线柱
S205——回流
S206——密封
S207——形成端子
结束

Claims (21)

1.一种半导体器件，包括：
(a)半导体芯片；
(b)第一区域和第二区域，形成在所述半导体芯片上方；
(c)多个第一键合焊盘，形成在所述第一区域上方；
(d)多个第二键合焊盘，形成在所述第二区域上方；
(e)多个第一引线和多个第二引线；
(f)第一导体，电连接所述第一键合焊盘与所述第一引线；以及
(g)第二导体，电连接所述第二键合焊盘与所述第二引线，
其中所述第一导体的横截面大于所述第二导体的横截面。
2.根据权利要求1所述的半导体器件，
其中所述第一导体是接线柱，以及所述第二导体是导线。
3.根据权利要求1所述的半导体器件，
其中所述第一导体由铜或铝制成，以及所述第二导体由金制成。
4.根据权利要求1所述的半导体器件，
其中在所述第一区域上方形成MISFET。
5.根据权利要求4所述的半导体器件，
其中形成在所述第一区域上方的MISFET的最小栅极长度大于或等于形成在所述第二区域上方的MISFET的最小栅极长度。
6.根据权利要求1所述的半导体器件，
其中在所述第一区域上方形成多个第一布线，以及在所述第二区域上方形成多个第二布线，以及
其中在所述第一布线之间的最小间隔大于或等于在所述第二布线之间的最小间隔。
7.根据权利要求1所述的半导体器件，
其中所述第一区域是功率晶体管形成区域，以及所述第二区域是控制集成电路形成区域。
8.根据权利要求1所述的半导体器件，
其中在所述第一键合焊盘下方紧接着形成功率晶体管。
9.根据权利要求1所述的半导体器件，
其中所述第一键合焊盘的面积大于所述第二键合焊盘的面积。
10.根据权利要求1所述的半导体器件，
其中在所述第一键合焊盘之间的最小间距大于在所述第二键合焊盘之间的最小间距。
11.一种半导体器件，包括：
(a)半导体芯片；
(b)功率晶体管形成区域和控制集成电路形成区域，形成在所述半导体芯片上方；
(c)多个第一键合焊盘，形成在所述功率晶体管形成区域上方；
(d)多个第二键合焊盘，形成在所述控制集成电路形成区域上方；
(e)多个第一引线和多个第二引线；
(f)接线柱，电连接所述第一键合焊盘与所述第一引线；以及
(g)导线，电连接所述第二键合焊盘与所述第二引线。
12.根据权利要求11所述的半导体器件，
其中所述接线柱的横截面大于所述导线的横截面。
13.根据权利要求11所述的半导体器件，
其中所述第一键合焊盘的面积大于所述第二键合焊盘的面积。
14.根据权利要求11所述的半导体器件，
其中在所述第一键合焊盘下方紧接着形成功率晶体管。
15.一种半导体器件制造方法，包括以下步骤：
(a)在具有多个第一引线和多个第二引线的引线框架上方，安装具有第一区域和第二区域的半导体芯片；
(b)在形成于所述第一区域中的第一键合焊盘和所述第一引线上方，形成连接材料；
(c)经由接线柱，将所述第一键合焊盘与所述第一引线电连接；
(d)对所述半导体芯片应用热处理；以及
(e)在所述步骤(d)之后，经由导线将形成于所述第二区域中的第二键合焊盘与所述第二引线电连接。
16.根据权利要求15所述的半导体器件制造方法，
其中所述接线柱的横截面大于所述导线的横截面。
17.根据权利要求15所述的半导体器件制造方法，
其中所述第一键合焊盘的面积大于所述第二键合焊盘的面积。
18.根据权利要求15所述的半导体器件制造方法，
其中在所述第一键合焊盘下方紧接着形成功率晶体管。
19.根据权利要求15所述的半导体器件制造方法，
其中所述连接材料可从焊料和树脂浆料中选择。
20.根据权利要求15所述的半导体器件制造方法，
其中所述第一区域是功率晶体管形成区域，以及所述第二区域是控制集成电路形成区域。
21.一种半导体器件制造方法，包括以下步骤：
(a)在具有多个第一引线和多个第二引线的引线框架上方，安装具有第一区域和第二区域的半导体芯片；
(b)经由导线，将形成于所述第二区域中的第二键合焊盘与所述第二引线电连接；
(c)在所述步骤(b)之后，在形成于所述第一区域上方的所述第一键合焊盘和所述第一引线上方，形成连接材料；
(d)经由导线，电连接所述第一键合焊盘和所述第一引线；以及
(e)对所述半导体芯片应用热处理。
CNA2006101085017A 2005-08-16 2006-08-03 半导体器件及其制造方法 Pending CN1917198A (zh)

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