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CN1913140A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN1913140A
CN1913140A CNA2006100956468A CN200610095646A CN1913140A CN 1913140 A CN1913140 A CN 1913140A CN A2006100956468 A CNA2006100956468 A CN A2006100956468A CN 200610095646 A CN200610095646 A CN 200610095646A CN 1913140 A CN1913140 A CN 1913140A
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Prior art keywords
semiconductor device
pad
electrode pad
metal
probe
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CN100517672C (zh
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永井纪行
阪下俊彦
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Nuvoton Technology Corp Japan
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Matsushita Electric Industrial Co Ltd
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Abstract

本发明揭示一种半导体器件，用沿着探针的前进方向平行并排的多个细金属层，形成焊盘金属(22)的至少探针区域(23)的正下方部分，从而不会导致工艺和芯片尺寸增大，能够提高焊盘金属(22)的表面平整度，防止半导体器件的特性恶化。

Description

半导体器件
技术领域
本发明涉及具有作为外部端子功能的I/O单元的半导体器件。
背景技术
一般，半导体器件具有I/O单元作为将内部电路与外部设备等连接的输入输出器件，对I/O单元的电极焊盘连接键合引线、或者形成凸点，通过这样与外部设备等进行电连接。另外，在半导体器件的检查中，也使探针与该电极焊盘接触，通过这样将半导体器件与测试设备电连接，进行检查。
下面，用图9、图10及图11的例子说明以往的半导体器件的I/O单元结构。
图9A为以往的半导体器件的平面图，图9B为以往的半导体器件中的I/O单元区域的主要部分放大图，是图9A的平面图中的I/O区域的放大图。图10为以往的半导体器件中的I/O区域附近的剖视图，表示图9的A-A′剖视图，是表示探测时的电极焊盘状态的示意图。图11为表示以往的半导体器件中形成凸点的电极焊盘的剖视图。
半导体器件划分为形成内部电路的工作区域10、以及形成与内部电路连接的作为输入输出器件的I/O单元11的I/O区域。
如图9及图10所示，以往的I/O单元将工作区域10中形成的内部电路的信号及电源等，使用多层的Cu布线，引到I/O区域的用最上层Cu布线形成的焊盘金属12(未图示)，通过通路15与从半导体器件表面的SiN膜13(平面图中省略)露出的Al电极焊盘14连接。这里，焊盘金属12与电极焊盘14形成为实质上相同形状。许多结构的焊盘金属及电极焊盘为50μm×80μm～70μm×100μm左右，Al电极焊盘膜厚具有450μm～2μm左右。
另外如图11所示，在半导体器件利用QFP及BGA等的封装形成时，在电极焊盘14的探针区域16以外的区域形成凸点18或焊球等。
检查时，使得与测试设备连接的探针17与电极焊盘14的探针区域16接触，进行检查。在探针17接触时，沿着探针17的前进方向削去电极焊盘14。这时，也可以削去电极焊盘14，一直到焊盘金属12露出为止，探针17与电极焊盘14直接连接。
但是，由于工艺精度的问题，在形成大面积图形时，存在表面平整度下降的倾向，在以往的I/O单元结构中，由于电极焊盘14为了进行探测，需要有最低限度的面积，与电极焊盘14形成实质上相同形状的焊盘金属12的表面形成凹凸，平整度降低。所以存在的问题是，在探针17接触时，往往由于在焊盘金属12的表面的凹凸处产生应力集中，焊盘金属12产生裂纹，有的情况下在层间膜产生裂纹，因此下层Cu布线与焊盘金属12产生短路或者下层Cu布线或电路等损坏，从而半导体器件的特性恶化。
作为它的解决措施，如特开2004-235416号公报所示，提出了一种结构，它是在焊盘金属的正下方设置空置布线，以缓和裂纹产生的影响，但存在的问题是，由于要形成多余的层，因此工艺复杂，另外在利用已有的布线层形成空置布线时，I/O单元区域的面积增大，芯片尺寸增大。
为了解决以上的问题，本发明的半导体器件的目的在于不导致工艺复杂及芯片尺寸增大，提高焊盘金属的表面平整度，防止半导体器件的特性恶化。
发明内容
为了达到上述目的，本发明的半导体器件，具有配置外部端子即电极焊盘的电极焊盘区域、以及配置内部电路的工作区域，其中具有：将前述电极焊盘与前述焊盘金属电连接的通路，在前述焊盘金属的至少一部分设置缝隙。
本发明的另一半导体器件，具有配置外部端子即电极焊盘的电极焊盘区域、以及配置内部电路的工作区域，其中具有：与来自前述内部电路的布线连接并通过层间膜配置在前述电极焊盘的下层的焊盘金属、以及贯通前述层间膜而将前述电极焊盘与前述焊盘金属电连接的通路，在前述焊盘金属的至少一部分设置缝隙。
再有，前述通路配置在除了前述探针区域以外的区域。
另外，超出到前述工作区域，形成前述电极焊盘。
再有，在前述工作区域的前述电极焊盘下部，形成屏蔽布线。
另外，前述层间膜是SiN层。
另外，在前述焊盘金属的至少一部分设置缝隙的位置是前述电极焊盘中包含检查时检查探针移动的探针区域的正下方的位置，设置前述缝隙的方向是前述检查探针的前述方向。
再有，仅在前述焊盘金属的前述探针区域正下方，设置前述缝隙，
另外，前述缝隙的至少一端具有开放端。
另外，具有多条前述缝隙。
再有，用多条前述缝隙夹住的前述焊盘金属的各金属层的宽度为小于等于20μm。
另外，形成前述焊盘金属的金属层由Cu构成，前述电极焊盘由Al构成。
附图说明
图1为本发明实施形态1的I/O单元区域的平面图。
图2为本发明实施形态1的I/O单元区域的剖视图。
图3所示为I/O单元的电极焊盘中的探针区域图。
图4为本发明实施形态1的仅在探针区域设置缝隙的I/O单元区域的平面图。
图5为本发明实施形态2的I/O单元区域的平面图。
图6为本发明实施形态2的I/O单元区域的剖视图。
图7为本发明实施形态2的I/O单元区域的平面图。
图8所示为本发明实施形态3的形成凸点的I/O单元结构的剖视图。
图9A为以往的半导体器件的平面图。
图9B为以往的半导体器件的I/O单元区域的主要部分放大图。
图10为以往的半导体器件的I/O区域附近的剖视图。
图11所示为以往的半导体器件中形成凸点的电极焊盘的剖视图。
具体实施方式
本发明的半导体器件的I/O单元，采用的结构是在工作区域形成的内部电路使用多层布线引到I/O单元区域的用最上层布线形成的焊盘金属，并通过通路与从半导体器件表面的层间膜露出的电极焊盘连接。在本发明的半导体器件的I/O单元中，至少在探针区域正下方部分用平行于探针前进方向并排的宽度细的多个金属层，形成焊盘金属。另外，在焊盘金属与电极焊盘之间形成层间膜时，在I/O单元的半导体器件端面部分形成将焊盘金属与电极焊盘连接的通路，对于通路在工作区域一侧设置与探针接触的探针区域。
这样，探针接触的探针区域正下方的焊盘金属，沿探针前进方向集中形成多条细长形状的焊盘金属，从而与以往的和电极焊盘实质上相同形状的焊盘金属相比，由于一个一个焊盘金属的面积减小，因此工艺上能够形成很好的表面平整度，能够缓和探针接触时的应力集中，缓和对I/O单元下部区域的影响，防止半导体器件的特性恶化。另外，由于在探针区域中因探针接触而产生的对焊盘金属的应力仅作用于细分的一个一个焊盘金属，应力对于整个电极焊盘下部不产生影响，因此能够缓和对I/O单元下部区域的影响，防止半导体器件的特性恶化。
下面，以Cu布线及Al电极焊盘的半导体器件为例，用附图说明本发明的实施形态。
实施形态1
首先，用图1、图2、图3及图4说明实施形态1的半导体器件。
图1为本发明实施形态1的I/O单元区域的平面图，图2为本发明实施形态1的I/O单元区域的剖视图，是图1的A-A′剖视图。图3所示为I/O单元的电极焊盘中的探针区域图，图4为本发明实施形态1的仅在探针区域设置缝隙的I/O单元区域的平面图。
如图1及图2所示，本实施形态的I/O单元与以往的半导体器件相同，将工作区域10中形成的内部电路的信号及电源等使用多层的Cu布线，引到I/O区域21的用最上层Cu布线形成的焊盘金属22(未图示)，通过通路15与从半导体器件表面的SiN膜13(在平面图中未图示)露出的Al电极焊盘14连接。电极焊盘也具有与以往的I/O单元同样的形状。这里，在以往的I/O单元中，是在电极焊盘14的形成区域整个表面形成成为焊盘金属的金属层，但本实施形态的焊盘金属22通过设置缝隙，则为图1那样的由沿着探针前进方向的多个细长的Cu层形成的结构。
这样，由于利用多个长方形的Cu层形成焊盘金属22，从而能够减小一个一个的Cu层的面积，能够形成Cu层表面的很好的平整度，因此能够缓和探针接触时的应力集中，缓和对I/O单元下部区域的影响，防止半导体器件的特性恶化。另外，由于在探针区域23中因探针接触而产生的对焊盘金属22的应力仅用途于细分的一个一个焊盘金属22，应力对于整个电极焊盘下部不产生影响，因此能够缓和对I/O单元下部区域的影响，防止半导体器件的特性恶化。
这里，用图3说明焊盘金属22的探针区域23。
如图3所示，设定探针17与电极焊盘14的探针区域23接触，探针17从半导体器件外侧向工作区域前进，刮削电极焊盘14，与电极焊盘14接触。
在上述说明中，是在焊盘金属整个面上设置探针前进方向的缝隙，将电极焊盘进行细分，但也可以如图4所示，仅在焊盘金属的探针区域正下方设置缝隙，将焊盘金属进行细分。
在图4中，焊盘金属22的探针区域23的正下方的探针前进方向前后的区域虽与以往相同，用单一平面形成，但在探针区域23的正下方设置缝隙24，形成焊盘金属22的接触部分，使得沿着探针前进方向用细长的Cu层进行接触。
另外，上述那样的细长的Cu层，只要至少在探针区域23的正下方形成即可，而在图4的说明中，将探针区域23的正下方的探针前进方向前后的两个区域形成为单一平面形状，但也可以一直到焊盘金属的探针前进方向前后的某一区域为止都进行细分，作为形放端，而剩下的一个区域形成为单一平面形状。
实施形态2
下面，用图5及图6说明实施形态2的半导体器件。
图5为本发明实施形态2的I/O单元区域的平面图，图6为本发明实施形态2的I/O单元区域的剖视图，是图5的A-A′剖视图。
如图5及图6所示，本实施形态的I/O单元与以往的半导体器件相同，将工作区域10中形成的内部电路的信号及电源等使用多层的Cu布线引到I/O区域21的用最上层Cu布线形成的焊盘14连接。这里，在实施形态2的I/O单元中，在焊盘金属32上，除了通路35区域以外，还形成SiN膜33(在平面图中未图示)，并在SiN膜33上形成电极焊盘14。电极焊盘14与焊盘金属32通过通路35电连接，通路35形成在探针区域23之外，最好形成在I/O单元的半导体器件端部区域。这是由于在通路35上的电极焊盘14的表面产生凹凸，而在探针接触时以避免受到该凹凸的影响。
这时，本实施形态的焊盘金属32，采用的结构是通过设置缝隙34，由图5那样的沿探针前进方向的多个细长的Cu层形成。但是，如上所述，在I/O单元的半导体器件端部区域由于形成通路35，而不形成缝隙34。
这样，由于利用多个长方形的Cu层形成包含探针区域23正下方的区域的焊盘金属32，从而能够减小一个一个的Cu层的面积，能够形成Cu层表面的很好的平整度，因此能够缓和探针接触时的应力集中，缓和对I/O单元下部区域的影响，防止半导体器件的特性恶化。另外，由于在探针区域23中因探针接触而产生的对焊盘金属32的应力仅作用于细分的一个一个焊盘金属32，应力对于整个电极焊盘14的下部不产生影响，因此能够缓和对I/O单元下部区域的影响，防止半导体器件的特性恶化。
另外，也可以与实施形态1相同，焊盘金属32的探针区域23正下方的探针前进方向前后的区域与以往相同，用单一平面形成，而仅在探针区域23的正下方设置缝隙34，使得焊盘金属32的接触部分沿着探针的前进方向细长的Cu层进行接触。
实施形态3
下面，用图7及图8说明实施形态3的半导体器件。
图7为本发明实施形态3的I/O单元区域的平面图，图8所示为本发明实施形态3的形成凸点的I/O单元结构的剖视图。
在本实施形态中与实施例2相同，在具有缝隙44的焊盘金属42上除了通路35区域以外，形成SiN膜33(在平面图中未图示)，在SiN膜33上形成电极焊盘14。
这里，以超出到工作区域10的形态形成电极焊盘14，从而能够缩小被电极焊盘14的最小面积所限制的I/O单元，能够减小芯片尺寸。另外，通常屏蔽布线36在工作区域10的I/O单元附近走线，屏蔽布线36能够在电极焊盘14的下部进行布线。
另外，在探针接触时，虽然探针有时贯通电极焊盘14，但在电极焊盘14的探针区域23的正下方形成200～650nm左右的SiN膜，不会与屏蔽布线等的布线接触。
这样，由于利用多个长方形的Cu层形成包含探针区域23正下方的区域的焊盘金属42，从而能够减小一个一个的Cu层的面积，能够形成Cu层表面的很好的平整度，因此能够缓和探针接触时的应力集中，缓和对I/O单元下部区域的影响，防止半导体器件的特性恶化。另外，由于在探针区域23中因探针接触而产生的对焊盘金属42的应力仅作用于细分的一个一个焊盘金属42，应力对于整个电极焊盘14的下部不产生影响，因此能够缓和I/O单元下部区域的影响，防止半导体器件的特性恶化。
另外，也可以与实施形态2相同，焊盘金属42的探针区域23正下方的探针前进方向前后的区域与以往相同，用单一平面形成，而仅在探针区域23的正下方设置缝隙44，使得焊盘金属32的接触部分沿着探针的前进方向用细长的Cu层进行接触。
对于本实施形态的I/O单元，在形成堆积凸点37时，如图8所示能够在工作区域10上的电极焊盘形成。
在以上的各实施形态中，是以用Cu布线形成内部布线、用Al层形成电极焊盘的情况为例进行说明的，但即使将其它的金属层任意组合使用，也具有同样的结果。另外，作为层间膜是采用SiN层进行说明的，但即使采用其它的层间膜材料，也具有同样的结果。
另外，关于利用缝隙来细分的细长金属层的宽度，越细则表面的平整度越高，工艺最小线宽为0.2μm左右为最佳，但这里设为小于等于20μm，若考虑到设计布图，则最好为9μm左右。

Claims (18)

1.一种半导体器件，具有
配置作为外部端子的电极焊盘的电极焊盘区域、以及
配置内部电路的工作区域，
其特征在于，具有
与来自所述内部电路的布线连接并配置在所述电极焊盘的下层的焊盘金属、以及
将所述电极焊盘与所述焊盘金属电连接的通路，
在所述焊盘金属的至少一部分设置缝隙。
2.一种半导体器件，具有
配置作为外部端子的电极焊盘的电极焊盘区域、以及
配置内部电路的工作区域的半导体器件中，
其特征在于，具有
与来自所述内部电路的布线连接并通过层间膜配置在所述电极焊盘的下层的焊盘金属、以及
贯通所述层间膜将所述电极焊盘与所述焊盘金属电连接的通路，
在所述焊盘金属的至少一部分设置缝隙。
3.如权利要求2所述的半导体器件，其特征在于，
所述通路配置在除了所述探针区域以外的区域。
4.如权利要求2所述的半导体器件，其特征在于，
超出到所述工作区域，形成所述电极焊盘。
5.如权利要求4所述的半导体器件，其特征在于，
在所述工作区域的所述电极焊盘下部，形成屏蔽布线。
6.如权利要求2所述的半导体器件，其特征在于，
所述层间膜是SiN层。
7.如权利要求1所述的半导体器件，其特征在于，
在所述焊盘金属的至少一部分设置所述缝隙的位置是所述电极焊盘中包含检查时检查探针移动的探针区域的正下方的位置，设置所述缝隙的方向是所述检查探针的前进方向。
8.如权利要求2所述的半导体器件，其特征在于，
在所述焊盘金属的至少一部分设置所述缝隙的位置是所述电极焊盘中包含检查时检查探针移动的探针区域的正下方的位置，设置所述缝隙的方向是所述检查探针的前进方向。
9.如权利要求7所述的半导体器件，其特征在于，
仅在所述焊盘金属的所述探针区域正下方，设置所述缝隙。
10.如权利要求8所述的半导体器件，其特征在于，
仅在所述焊盘金属的所述探针区域正下方，设置所述缝隙。
11.如权利要求1所述的半导体器件，其特征在于，
所述缝隙的至少一端具有开放端。
12.如权利要求2所述的半导体器件，其特征在于，
所述缝隙的至少一端具有开放端。
13.如权利要求1所述的半导体器件，其特征在于，
具有多条所述缝隙。
14.如权利要求2所述的半导体器件，其特征在于，
具有多条所述缝隙。
15.如权利要求13所述的半导体器件，其特征在于，
用多条所述缝隙夹住的所述焊盘金属的各金属层的宽度为小于等于20μm。
16.如权利要求14所述的半导体器件，其特征在于，
用多条所述缝隙夹住的所述焊盘金属的各金属层的宽度为小于等于20μm。
17.如权利要求1所述的半导体器件，其特征在于，
形成所述焊盘金属的金属层由Cu构成，所述电极焊盘由Al构成。
18.如权利要求2所述的半导体器件，其特征在于，
形成所述焊盘金属的金属层由Cu构成，所述电极焊盘由Al构成。
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JP2007048853A (ja) 2007-02-22
CN100517672C (zh) 2009-07-22
US7944059B2 (en) 2011-05-17
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US20110215481A1 (en) 2011-09-08
US20070052085A1 (en) 2007-03-08

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