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CN1815710A - 具有低介电常数介电层的半导体元件的制造方法 - Google Patents

具有低介电常数介电层的半导体元件的制造方法 Download PDF

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CN1815710A
CN1815710A CNA200510088983XA CN200510088983A CN1815710A CN 1815710 A CN1815710 A CN 1815710A CN A200510088983X A CNA200510088983X A CN A200510088983XA CN 200510088983 A CN200510088983 A CN 200510088983A CN 1815710 A CN1815710 A CN 1815710A
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carbon
layer
essence
low
dielectric
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CN100369233C (zh
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郑双铭
叶明灵
包天一
林耕竹
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种具有低介电常数介电层的半导体元件的制造方法。此方法包括沉积通式为CxHy的碳氢化合物层于低介电常数介电层的表面上。其中，沉积此碳氢化合物层时利用等离子体增强化学气相沉积(PECVD)工艺，并使用乙烯(C2H4)或经取代的己烷衍生物α－松油烯(CH3) 2CHC6H6CH3作为前驱材料。根据本发明的实施例，碳扩散进入低介电常数介电层中，因此可降低等离子体处理或蚀刻对低介电常数介电层所造成的伤害。在其它实施例中，则至少包括一种具有低介电常数介电层的半导体元件，其中此低介电常数介电层具有经碳调节的介电区邻近于沟渠侧壁、以及主介电区(Bulk Dielectric Region)。在较佳实施例中，经碳调节的介电区的碳浓度低于主介电区的碳浓度不超过约 5％。

Description

具有低介电常数介电层的半导体元件的制造方法
交互参照的相关申请案
本申请案有关于公元2005年2月1日申请的同申请人、同样申请中且与本案一起申请的专利申请案编号第11/048,518(TSM04-0816)号“以CxHy封住低介电常数介电质的孔洞的方法(Sealing Pores of Low-KDielectrics Using CxHy)”。本申请案亦有关于公元2004年11月10日申请的同申请人、同样申请中的专利申请案编号第10/985,149(TSM04-0369)“镶嵌结构的扩散阻挡层(Diffusion Barrier for DamasceneStructures)”。在此将这些同申请人且同样申请中的申请案一并列入参考。
技术领域
本发明涉及一种半导体制造，且特别是涉及一种制造具低介电常数介电层的元件的改良方法。
背景技术
随着半导体元件的密度的增加，以及电路构件的尺寸的缩减，电阻电容(RC)延迟时间对电路性能的影响日益提高。为了降低电阻电容延迟，需将传统介电质转换成低介电常数介电质。以这些低介电常数介电材料作为内金属介电质(IMD)以及内层介电质(ILD)，特别有其效用。然而，低介电常数介电质在制造工艺期间，特别在制造内连线的导电材料的工艺期间，会引发一些问题。
一般利用高能量的等离子体蚀刻工艺图案化并蚀刻导电材料。在其它工艺系统中，图案化低介电常数材料时，是通过光刻胶的应用与图案化。通过光刻胶掩膜来蚀刻低介电常数材料，接着利用高能量的等离子体蚀刻工艺移除光刻胶。由于低介电常数材料较软、化学稳定性较低、更具多孔性或上述因素的任意组合，因此低介电常数材料较易遭受等离子体蚀刻损害。等离子体损害本身可产生较高的漏电流、较低的崩溃电压、并造成低介电常数介电材料的介电常数的改变。
图1为镶嵌结构的剖面示意图。介电层12已设置在导线层11上。介层窗孔14自沟渠15向下延伸。当铜填入后，介层窗孔14连接两导线层。由于铜的高扩散性与在硅中扮演在结合中心的趋势，进行步骤时必须确保所有的铜限制在镶嵌结构中。传统上，大都借助于阻挡层18的导入，此阻挡层18衬在沟渠15与介层窗孔14的侧壁上，如图2所示。
在制造工艺期间，低介电常数介电质的表面易受损害。多孔性低介电常数介电质，例如多孔性硅土，特别容易受损。当表面孔洞受损时，工艺化学物质可能会穿透而进入介电质中，进而导致其介电常数提高。低介电常数介电质的损伤会造成沟渠地面21与沟渠侧壁23的表面粗化，如图1与图2所示。如此一来，意味着阻挡层18的厚度需比正常厚度大，如图2所示，以确保无薄贴片让铜移动穿过。无前述粗化问题下，阻挡层的厚度约300即足以遏制铜，反之，于粗糙沟渠表面存在下，则必须将阻挡层的厚度增加到至少500。
如同上述，介电质损伤会造成较高的漏电流、较低的崩溃电压、以及低介电常数介电材料的介电常数的改变。有鉴于这些与其它问题，因此亟需可改善低介电常数介电质制造的方法。
发明内容
本发明的目的就是提供一种制造具有低介电常数介电质的半导体元件的改良方法，其中本发明的较佳实施例可解决或防止上述或其它问题，并具有技术优势。
本发明的一较佳实施例中，提供了一种制造具有低介电常数介电层的半导体元件的方法。沉积碳氢化合物层于低介电常数介电层上。在较佳实施例中，沉积此碳氢化合物层时利用等离子体增强化学气相沉积(PECVD)工艺，并使用乙烯(C2H4)或己烷衍生物α-松油烯[(CH3)2CHC6H6CH3]作为前驱材料。在实施例中，还至少包括利用等离子体蚀刻在碳氢化合物层与低介电常数介电层中形成凹陷特征。根据本发明的实施例，碳会扩散至低介电常数介电层，因此可降低等离子体处理对低介电常数介电层所造成的伤害。
在本发明的另一实施例中，提供了一种修补半导体制造工艺中所造成的低介电常数介电质的碳耗损伤害。此方法至少包括利用等离子体增强化学气相沉积反应工艺来反应前驱材料，以沉积碳氢化合物层于低介电常数介电层上。在较佳实施例中，碳氢化合物层至少包括：介于约20至约95原子百分比的碳；介于约5至约80原子百分比的氢；以及介于约0至约5原子百分比的氧。
还有一些实施例至少包括一种具有低介电常数介电层的半导体元件，其中此低介电常数介电层具有经碳调节区邻近于沟渠侧壁。在较佳实施例中，经碳调节区的碳浓度低于主介电区的碳浓度不超过约5％。
以下将描述本发明的实施例的附加特征与优点，这些附加特征与优点形成本发明的权利要求的课题。所属技术领域的技术人员应可了解到其可轻易地以所披露的特定实施例为基础，来修正或设计其它结构或工艺，以实现本发明的目的。所属技术领域的技术人员亦应可了解到，所描述的示范实施例上中这类的等效架构与变化并不脱离权利要求中所提出的本发明的精神与范围。
附图说明
为了更完整了解本发明及其优点，请参照上述辅以所附附图所作的说明。其中，所附的附图包括：
图1与图2为在半导体元件在传统镶嵌工艺中的中间步骤的剖面图，其中表示出低介电常数介电质表面的粗化损伤。
图3为依照本发明一较佳实施例的一种在半导体元件在示范镶嵌工艺中的中间步骤的剖面图，其中进一步表示出CxHy层。
图4为依照本发明一较佳实施例的一种在半导体元件在示范镶嵌工艺中的中间步骤的剖面图，其中进一步表示出经碳调节的区域邻近于沟渠侧壁。
图5为依照本发明一较佳实施例的一种在半导体元件在示范镶嵌工艺中的中间步骤的剖面图，其中进一步表示出化学机械研磨前的结构。
图6为依照本发明一较佳实施例的一种在半导体元件在示范镶嵌工艺中的中间步骤的剖面图，其中进一步表示出化学机械研磨平坦化的结构。
在不同附图中的相对应图号与符号一般表示相对应的部分，除非另有指定。附图表示成可清楚显示较佳实施例的相关方面，而无需依比例表示。主要元件标记说明
11：导线层                     12：介电层
14：介层窗孔                   15：沟渠
18：阻挡层                     21：沟渠地面
23：沟渠侧壁                   85：双重金属镶嵌结构
86：沟渠                       104：介层窗
106：沟渠                      116：阻挡层
300：镶嵌结构                  301：基材
303：第一蚀刻终止层            305：低介电常数介电层
307：碳氢化合物层              308：碳覆膜
309：经碳调节的区域            310：导体层
具体实施方式
以下将详细讨论本较佳实施例的操作与制造。然而，在此所述实施例与例子并非本发明仅有的应用或运用。在此所讨论的特定实施例仅为制造或使用本发明的特定方式的举例说明，并非用以限制本发明或权利要求的范围。
本发明有关于半导体元件的制造，且特别是有关于多孔洞的低介电常数介电层的制造与处理。此低介电常数介电层可包括许多薄膜或许多层，但实施例并不限于这些型态。以下将以特定内容，即在镶嵌工艺中铜导线与介层窗的制造，来描述本发明的较佳实施例。可相信的一点是，当本发明的实施例应用在此工艺中时，将具有明显优势。更可相信的一点是，当本发明的实施例运用在其它关注低介电常数介电层的性能的半导体制造应用上，亦具有其优势。更可相信的一点是，在此所描述的实施例将有利于其它未特别提及的集成电路内连线的应用。因此，在此所讨论的特定实施例仅用以说明制造与应用本发明的特定方法，并非用以限制本发明的范围。
现请参照图3，其为欲依照本发明的较佳实施例与示范镶嵌工艺来进行处理的一种中间代表性的镶嵌结构300的剖面图。图3所示为半导体的基材301，此基材301可例如至少包括硅、绝缘层上有硅(SOI)、功能性与逻辑元件、其它内连线层或其组合。以下为描述本发明的实施例的目的，基材301至少包括内层介电层(ILD)以及导电内连线。镶嵌工艺的详细说明，Bao等人已在美国专利案编号第6,248,665号以及美国专利申请案公开编号第2004/0121583号中加以描述，在此一并列入参考。
请再次参照图3，第一蚀刻终止层303位于基材301上。低介电常数介电层305位于第一蚀刻终止层303上，其中此低介电常数介电层305亦称为内金属介电层(IMD)、内层介电层(ILD)或介电层。
根据较佳实施例，虽然其它的等离子体工艺或薄膜沉积方法也适用，但较佳为利用等离子体增强化学气相沉积方式沉积碳氢化合物层307，其中此碳氢化合物层307至少包括CxHy。碳氢化合物层307由有机分子前驱物所构成，且形成于等离子体增强化学气相沉积反应器中。合适的前驱物包括具有充分的挥发性的碳氢化合物，如此一来，这些碳氢化合物可在反应容器中形成蒸气。较佳的前驱物为经取代的己烷衍生物α-松油烯(Substituted Hexane Derivativeα-terpinene；ATRP)[(CH3)2CHC6H6CH3]或乙烯(C2H4)。替代的前驱物包括任何其它碳氢化合物，较佳是具有碳-碳双键的碳氢化合物。通过控制等离子体增强化学气相沉积工艺的参数，例如温度、压力、射频电力、以及气体流率，可适当地沉积碳氢化合物的前驱物。在沟渠深度约2000时，碳氢化合物层307的厚度通常约介于40至50之间。
等离子体增强化学气相沉积工艺较佳包括惰性载气，例如氦气。氦气的流量可介于约25sccm至约10000sccm之间，较佳介于约50sccm至约5000sccm之间。基材的温度介于约25℃至约400℃，且较佳介于约125℃至约350℃之间。射频功率密度介于约50W至约2500W，且较佳介于约50W至约1500W。在沉积工艺中，反应器温度介于约100mTorr至约10000mTorr之间，较佳介于约500mTorr至约8000mTorr之间。较合适的碳氢化合物层307的沉积时间约在10秒内。
碳氢化合物层307较佳至少包括：介于约20至约95原子百分比的碳；介于约0至约5原子百分比的氧；以及介于约5至约80原子百分比的氢。在薄膜的沉积工艺期间，受控制的主要工艺变量为射频功率、前驱物流率、反应器压力以及基材温度。
请参照图4，其为图3的中间半导体元件经进一步形成各向异性蚀刻的中间双重金属镶嵌结构85后的侧视剖面图。在此中间的双重金属镶嵌结构85中，由介层窗104与上方的沟渠106所构成的凹陷特征。
制造第一双重金属镶嵌结构85时，先利用光刻图案化以及各向异性蚀刻，来形成介层窗104穿过低介电常数介电层305、以及至少一部分第一蚀刻终止层303。接下来，利用相似的工艺来光刻图案化与各向异性蚀刻，以形成沟渠106穿过第一蚀刻终止层303、以及部分低介电常数介电层305。这些步骤形成沟渠106位于且围绕在介层窗104的上方。可了解的一点是，沟渠106可包围一或多个介层窗104，沟渠106与介层窗104可形成于不同的堆栈内金属介电层中，其中这些不同的堆栈内金属介电层之间形成有另一个蚀刻终止层。还可了解到低介电常数介电层305的表面可包括其它凹陷的特征，例如沟渠86，以容纳更多内层导电层。
如同先前所提及的传统低介电常数介电层工艺，沟渠蚀刻工艺会伤及沟渠侧壁。然而，本发明的实施例可避免此问题。此乃由于在沟渠蚀刻期间，碳从碳氢化合物层307移转至沟渠86、沟渠106以及介层窗104的侧壁，而形成碳覆膜308。如同在本发明中所采用的碳氢化合物层307的材料一样，碳覆膜308包括多种材料，不仅仅是纯碳而已。
碳覆膜308可至少包括碳氢化合物、含碳有机材料、至少包括碳、氢与氧的材料或多种碳材料的混合。申请人假设碳转移的工艺通过聚合反应工艺而发生。因此，申请人建议碳覆膜308在某种程度上可至少包括高分子聚合物层。在本发明的实施例中，碳覆膜308通常至少包括碳源，而从碳源处，碳可扩散至邻近的介电区。
在碳覆膜308沉积于沟渠侧壁上之后，碳自碳覆膜308扩散至低介电常数介电层305中。此扩散过程形成经碳调节的区域309邻近于低介电常数介电层305的沟渠侧壁，其中经碳调节的区域309的厚度为x。x较佳介于约300至500之间。根据本发明的较佳实施例，经碳调节的区域309可部分修补由传统沟渠蚀刻或等离子体处理所造成的碳消耗的损伤。
传统上，在含碳的低介电常数介电质中形成沟渠时，邻近于沟渠侧壁的区域通常会产生碳的消耗。这样的消耗通常相当严重。一般而言，邻近于沟渠侧壁的碳浓度相对于主介电区的碳的浓度下降至少5％至10％。
用以修补碳消耗的实施例并不限于上述至少包括沟渠侧壁的实施例。一般而言，等离子体处理会消耗介电质表面区的碳。较佳实施例将表面碳的浓度复原至原来浓度的至少95％。
在另一些实施例中，经碳调节的区域309亦可称为富含碳的区域，其中邻近于沟渠侧壁的碳浓度可提高至高于主介电质的碳浓度。然而，申请人发现较佳实施例并未要求将介电质的碳的增加量作为碳的消耗量不超过5％的限制，其中碳的消耗在不超过5％的情况下，相信即可获得适当的介电质性能。
如同以上所述，在传统工艺中，一种低介电常数介电质的损害使低介电常数介电层表面粗化。申请人发现传统上经处理过的介电质层具有平均表面粗化值34.7，表面粗化值的均方根为44.16，且最大表面粗化值为447.88。然而，根据较佳实施例，申请人发现介电层具有平均表面粗化值11.1，表面粗化值的均方根为14.2，且最大表面粗化值为314.8。经降低表面损伤的结果，申请人发现测试元件的电阻电容(RC)值降低10％。
在修补形成沟渠时所造成的碳消耗后，利用温度介于约300℃至约400℃的热处理，来移除残余的碳氢化合物层307、碳覆膜308或任何碳的残余。一般而言，这样的热处理可轻易地整合至另一工艺中。
接下来请参照图4，低介电常数介电层305包括介电常数小于约4的介电质。这样的介电质包括例如掺杂碳的二氧化硅，亦称为有机硅玻璃(Organo-silicate Glass；OSG)以及碳氧化物。在替代实施例中，低介电常数材料可包括沉积于半导体结构的表面上的硼磷硅玻璃(BorophosphosilicateGlass；BPSG)、硼硅玻璃(Borosilicate Glass；BSG)、以及磷硅玻璃(Phosphosilicate；PSG)，这些材料层的厚度介于约5000至约9000之间，且较佳经平坦化。示范的有机低介电常数材料包括聚芳基酯(polyaryleneether)、氢硅酸盐(hydrogen silsesquioxane；HSQ)、含甲基的硅酸盐(methylsilsesquioxane；MSQ)、聚硅酸盐(polysilsesquioxane)、聚亚胺(polyimide)、苯环丁烯(benzocyclobutene；BCB)、以及非晶系聚四氟乙烯(amorphouspolytetrafluoroethylene；PTFE)(通常又称特氟龙，Teflon)。适合本发明的方法的其它类型的低介电常数材料包括氟硅玻璃(Fluorinated SilicateGlass；FSG)，例如掺杂氟的二甲基硅酸盐[fluorine-doped-(O-Si(CH3)2-O)-]。
低介电常数介电层305亦可包括一种低介电常数介电质，此种低介电常数介电质通常称为超低介电常数(Extreme Low-k；ELK)介电质。超低介电常数介电质一般具有低于约2的介电常数，且这些超低介电常数介电质包括多孔洞的介电质。合适的超低介电常数介电材料可包括氮化硅、氧化硅、旋涂玻璃(SOG)、等离子体增强(PE)的四乙氧基硅甲烷(Tetraethoxysilane；TEOS)、卤化的氧化硅以及氟硅玻璃。
其它较佳的超低介电常数介电质包括含有未反应且孔洞生成的材料或致孔剂(porogen)。将致孔剂加热至高于其分解温度，而在介电质中形成孔洞。举例而言，陶氏化学(Dow Chemical)的多孔性SILK产品与日本合成橡胶股份有限公司(JSR Corporation)的商品JSR 5109为合适的商用低介电常数前驱物，其中这些低介电常数前驱物利用有机母体材料(OrganicHost Material)。在较佳实施例中，低介电常数介电质至少包括希普励(Shipley)公司所提供的商用ZIRKONTM低介电常数内层介电质。ZIRKONTM低介电常数内层介电质是一种以含甲基的硅酸盐(MSQ)为基础材料与散布在溶剂丙二醇单甲基醚酯(PGMEA)中的丙烯酸(acrylic)、高分子聚合物系统的纳米微粒致孔剂的混合。另一种替代的较佳超低介电常数包括等离子体增强化学气相沉积的SiwOxCyHz，因为不论其有或没有致孔剂，均具有达成k＜2的可能性。
较佳是利用传统的旋转涂布机来沉积ZIRKONTM低介电常数内层介电质。待沉积后，较佳在垂直炉管中进行部分修复以交互连结母体，其中温度介于约250℃至300℃之间。ZIRKONTM低介电常数内层介电质的致孔剂的衰减开始于约275℃，且完全衰减发生在约450℃。
已知多孔性低介电常数材料的开放性孔洞会使性能下降。因此，实施例可选择性地包括孔洞密封方法，例如利用氩与氨的等离子体孔洞密封法、有机金属孔洞密封法、气相孔洞密封法或者较佳的电子束孔洞密封法。电子束孔洞密封法运用典型状况下的电子束，此典型状况为2000～5000keV、1～6mA以及75～100μC/cm2。
根据传统处理且请参照图5，全面性沉积阻挡层116，以至少衬在双重金属镶嵌结构85上。阻挡层116的厚度较佳约为10至100之间，且此阻挡层116可阻挡铜的扩散。阻挡层116可包括金属氮化物，例如氮化钽(TaN)、氮化钛(TiN)、氮化钨(WN)、氮化铽(TbN)、氮化钒(VN)、氮化锆(ZrN)、氮化铬(CrN)、碳化钨(WC)、碳氮化钨(WCN)、氮化铌(NbN)、氮化铝(AlN)及上述材料的组合。在其它实施例中，阻挡层116包括钽/氮化钽双层结构。
可利用物理气相沉积(PVD)、化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)或等离子体增强原子层沉积(PEALD)等技术来形成阻挡层116。在较佳实施例中，阻挡层116包括氮化钽，且利用原子层沉积(ALD)方式来沉积阻挡层116。
替代的实施例可进一步包括粘着层(未表示)介于阻挡层116与其上方的导体层310之间。粘着层有助于相邻各层之间的附着。此粘着层较佳包含可与铜及/或下方的阻挡层结合的材料。且粘着层的厚度约为10至500之间，较佳少于约150。粘着层可包括至少一层材料层，此层材料包含由钌(Ru)、钽、钛、钨、钴(Co)、镍(Ni)、铝(Al)、铌、铝铜合金、上述材料的氮化物及上述材料的组合。
沉积导体层之前，先利用例如物理气相沉积及/或化学气相沉积方式选择性地沉积晶种层(Seed Layer)(未表示)于粘着层上。物理气相沉积晶种层，其材质较佳为铜，以形成厚度约为400至700的连续层于晶片的处理表面上，以提供连续的导电表面，以利在电化学沉积工艺中沉积铜主体。
请再次参照图5，待阻挡层116沉积后，利用传统电化学沉积工艺电镀导体层310，以填满沟渠86、沟渠106、与介层窗104，并形成位于沟渠平面上的上方部分(亦即过度填充)，其中导体层310的材质较佳为铜。虽然可使用其它的铜填充方法，例如物理气相沉积法与化学气相沉积法，但由于电镀(电沉积)具有优异的填隙与阶梯覆盖能力，因此较佳利用电镀来沉积铜。在替代实施例中，导体层310实质上可由铜、铝、金、银、上述材料的混合物及上述材料的合金化合物。
化学机械研磨(CMP)平坦化导体层310至图6所示的程度。在另一替代实施例中，电研磨可用来取代化学机械研磨或与化学机械研磨接续使用。在此替代实施例中，可同时进行化学机械研磨与电镀工艺。
低介电常数介电层305包括经碳调节的区域309邻近于沟渠106，如图6所示。依照本发明的实施例，经碳调节的区域309部分地修补了传统沟渠蚀刻所造成的碳耗损伤害。经碳调节的区域309的厚度约为300至500之间。经碳调节的区域309的碳浓度低于低介电常数介电层305的主体区的碳浓度不超过约5％。
上述本发明的实施例仅为示范例并非用以限制本发明的范围，且对于所属技术领域的技术人员而言，各种变型为显而易见，而包括本发明的特征的这些变型落在本发明的范围与权利要求中。虽然本发明的实施例及其优点已详细描述如上，然应该了解到的一点是，在不偏离权利要求所定义的本发明的精神与范围下，当可在此进行各种改变、取代以及修正。
举例而言，所属技术领域的技术人员将可轻易地了解到在此所描述的许多特征、功能、工艺及材料可在本发明的范围内变化。此外，本申请案的范围并非用以将本发明的范围限制在说明书所描述的工艺、机械、制造、物质成分、手段、方法以及步骤的特定实施例中。任何所属技术领域的技术人员，将可轻易从本发明的披露中了解到，现存或日后所发展出的可与上述对应实施例执行实质相同的功能或达到实质相同的结果的工艺、机械、制造、物质成分、手段、方法或步骤，可依据本发明来加以应用。因此，权利要求用以将这类工艺、机械、制造、物质成分、手段、方法或步骤涵括在其范围内。

Claims (12)

1.一种半导体元件的制造方法，其特征是至少包括：
形成碳氢化合物层于低介电常数介电层上；
形成开口于该碳氢化合物层以及该低介电常数介电层中；以及
形成导电层位于该开口中。
2.根据权利要求1所述的半导体元件的制造方法，其特征是还至少包括：
形成碳层位于该开口中；
将碳从该碳层扩散至邻近于该开口的低介电常数介电区中；以及
利用加热该半导体元件，来移除碳残余。
3.根据权利要求1所述的半导体元件的制造方法，其特征是形成该碳氢化合物层于该低介电常数介电层上的步骤包括等离子体增强化学气相沉积工艺。
4.根据权利要求3所述的半导体元件的制造方法，其特征是该等离子体增强化学气相沉积工艺包括：
将基材温度设定在介于实质125℃至实质350℃之间；
将等离子体增强化学气相沉积反应器的压力设定在介于实质500mTorr至实质8000mTorr之间；以及
将等离子体增强化学气相沉积反应器的功率水准设定在介于实质50W至实质1500W之间。
5.根据权利要求1所述的半导体元件的制造方法，其特征是该低介电常数介电层至少包括一种材料，且该材料选自于实质上由有机硅玻璃、硼磷硅玻璃、硼硅玻璃、磷硅玻璃、聚芳基酯(polyarylene ether)、氢硅酸盐(hydrogen silsesquioxane；HSQ)、含甲基的硅酸盐(methyl silsesquioxane；MSQ)、聚硅酸盐(polysilsesquioxane)、聚亚胺(polyimide)、苯环丁烯(benzocyclobutene；BCB)、非晶系聚四氟乙烯(amorphouspolytetrafluoroethylene；PTFE)、氟硅玻璃(Fluorinated Silicate Glass；FSG)、多孔性氧化物、多孔性氮化物、致孔剂(porogen)及其组合所组成的族群。
6.根据权利要求1所述的半导体元件的制造方法，其特征是该碳氢化合物层至少包括：
介于实质20至实质95原子百分比的碳；
介于实质5至实质80原子百分比的氢；以及
介于实质0至实质5原子百分比的氧。
7.一种利用权利要求1所述方法制造的半导体元件，其特征是该低介电常数介电层至少包括：
主介电区，具有主碳浓度；以及
表面介电区邻近于该开口，其中该表面介电区的碳浓度为该主碳浓度的至少95％。
8.一种修补半导体元件工艺中所造成的低介电常数介电层的损伤的方法，其特征是至少包括：
形成碳氢化合物层位于该低介电常数介电层上；
利用等离子体工艺蚀刻该低介电常数介电层；以及
利用加热该低介电常数介电层达实质上至少300℃，来移除碳残余。
9.根据权利要求8所述的修补半导体元件工艺中所造成的低介电常数介电层的损伤的方法，其特征是该碳氢化合物层至少包括：
介于实质20至实质95原子百分比的碳；
介于实质5至实质80原子百分比的氢；以及
介于实质0至实质5原子百分比的氧。
10.根据权利要求8所述的修补半导体元件工艺中所造成的低介电常数介电层的损伤的方法，其特征是形成该碳氢化合物层的步骤还至少包括反应一种材料，且该材料选自于主要由C2H4、(CH3)2CHC6H6CH3、具有碳-碳双键的碳氢化合物及其组合所组成的族群。
11.一种半导体元件，其特征是至少包括：
基材；以及
低介电常数介电层位于该基材上，其中该低介电常数介电层具有开口，且该低介电常数介电层至少包括：
主介电区，具有主碳浓度；以及
表面介电区邻近于该开口，其中该表面介电区的碳浓度为该主碳浓度的至少95％。
12.根据权利要求11所述的半导体元件，其特征是该低介电常数介电层至少包括一种材料，且该材料选自于实质上由有机硅玻璃、硼磷硅玻璃、硼硅玻璃、磷硅玻璃、聚芳基酯(polyarylene ether)、氢硅酸盐(hydrogensilsesquioxane；HSQ)、含甲基的硅酸盐(methyl silsesquioxane；MSQ)、聚硅酸盐(polysilsesquioxane)、聚亚胺(polyimide)、苯环丁烯(benzocyclobutene；BCB)、非晶系聚四氟乙烯(amorphouspolytetrafluoroethylene；PTFE)、氟硅玻璃(Fluorinated Silicate Glass；FSG)、多孔性氧化物、多孔性氮化物、致孔剂(porogen)及其组合所组成的族群。
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