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CN1779934A - 用于使用重新分配基板制造晶片层芯片尺寸封装的方法 - Google Patents

用于使用重新分配基板制造晶片层芯片尺寸封装的方法 Download PDF

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Publication number
CN1779934A
CN1779934A CNA2005101059910A CN200510105991A CN1779934A CN 1779934 A CN1779934 A CN 1779934A CN A2005101059910 A CNA2005101059910 A CN A2005101059910A CN 200510105991 A CN200510105991 A CN 200510105991A CN 1779934 A CN1779934 A CN 1779934A
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wafer
substrate
call wire
redistribution
line
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CN100416785C (zh
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金在俊
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Epworks Co Ltd
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Easetech Korea Co Ltd
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Abstract

本发明涉及一种用以使用一重新分配基板制造一晶片层芯片尺寸封装的方法，其具有由重新分配线所连接且形成于一透明绝缘基板上的图案化凸块对。该重新分配基板与一晶片分离生产，且接着结合至该基板。各凸块对的一部分接触该晶片的激活表面上的一芯片垫，且另一部分与形成于该晶片中的孔其中的一相一致。传导线形成于该孔中及于该晶片的非激活表面上。外部连接终端于该非激活表面处形成于该传导在线。

Description

用于使用重新分配基板制造晶片层芯片尺寸封装的方法
技术领域
本发明涉及一种半导体封装技术，尤指一种用以晶片层芯片尺寸封装『water level chip scale package(W1-CSP)』的方法。
背景技术
如业界中已知的，大量集成电路(IC)装置制造于一半导体晶片中，且被划分成分开的芯片。该芯片接着自该晶片分离，且以欲用于电子系统或产品的封装形式组合。所述封装，一般是提供机械支撑该芯片的结构，是保护该芯片不受环境损害的有形壳体，自与该芯片的电气连接，并移除由该芯片产生的热。
最近，多媒体、信息、通讯、及数字相关产业的快速成长需要具有小型因素、高整合性、及高效能的更新与更进阶的IC产品。此市场潮流反应于减小的芯片大小、增加的电气终端等等中，其导致对该封装的结构与电气设计而非对该芯片许多的新挑战。今日的封装技术对于影响电子端应用的价格、效能、及可靠度愈形重要。
一广泛已知初始形式的封装已经使用具有周围环绕该芯片边缘的铅终端的一铅框。之后，已经研发透过一印刷电路板使用锡球区域分配的一球栅数组(BGA)封装，以给予更大量终端，且又已经研发一芯片尺寸封装(CSP)，以满足业界对最小(即芯片大小)形状因素的成长需求。此外，已经引入一晶片层封装(WLP)技术，以实现于芯片分离前该晶片上有成本效益的封包制造。
一传统WLP与其制造显示于图1A至图1K中。该示范传统WLP已熟知为由以色列Shellcase有限公司所研发的“ShellBGA”。
图1A显示一硅晶片1，其中形成一些IC芯片10a与10b。一划线区域13区分该相邻芯片10a与10b。各芯片10a与10b具有复数个芯片垫12于其激活表面11上。除了该芯片垫12之外，该激活表面11覆盖有一被动层16。一垫延伸层14连接且延伸自该芯片垫12。
图1B显示附加一第一玻璃基板20至该硅晶片1的一步骤。对于其间的附加来说，涂覆一环氧化物18于该被动层16与该垫延伸层14上。
图1C显示形成球垫22于该第一玻璃基板20上的一步骤。该球垫22是锡球将形成为该封装之外不连接终端之处。
图1D显示藉由沿着该划线区域13自该第一玻璃基板20部分移除该晶片1至该芯片10a与10b的上部分形成一刻痕24的一部分。结果，暴露该垫延伸层14的一侧端至该刻痕24。
图1E显示形成一图案化铅层26的一步骤，其配置自该刻痕24的一表面至该球垫22。该铅层26因此连接至暴露至该刻痕24的垫延伸层14。
图1F显示形成一焊料罩层30的一步骤，除了该球垫22上的部分外，其覆盖大部分该铅层26。
图1G显示形成锡球32于该个别球垫22上的一步骤。该球垫22上的铅层26因此电气耦合至该锡球32。
图1H显示一晶片背磨步骤。于此步骤中，机械研磨该晶片1的下部分，因此各芯片10a与10b减少厚度。
图1T显示自该晶片1的背表面沿着该刻划区域13蚀刻该晶片1的一步骤。
图1J显示透过一环氧化物36附加一第二玻璃基板34至该晶片1的背表面的一步骤。
图1K显示一晶片菱形化步骤。于此步骤中，沿着该刻划区域13中的一菱形区域38切割该晶片1，因此获得制造于该个别芯片10a与10b上的WLP。如于上文中所讨论般，该传统WLP实施沿着该刻划区域形成的刻痕，以允许透过该刻痕形成该图案划铅层。相应地，为了形成该刻痕，该传统WLP需要增加该刻划区域的宽度，而非该菱形区域。很不幸地，此可能导致单一晶片中的芯片数减少。
此外，由于该图案划铅层形成于该芯片的外部上，该传统WLP可能到达封装大小中减小的一限制。并且，直接执行于该芯片边缘上的图案化铅层仅可限制该图案设计弹性。
发明内容
本发明的目的是提供一种用以使用重新分配基板制造晶片层芯片尺寸封装的方法。
本发明的范例非限制实施例提供一种用以制造一晶片层芯片尺度封装，而不增加一晶片中一刻划区域的宽度的方法。本发明的范例非限制实施例另提供一种用以制造一晶片层芯片尺度封装，不仅有利减少封装大小，亦具有绝佳图案设计弹性的方法。
根据本发明的一范例实施例，该方法包含(a)生产具有一透明绝缘基板与形成于该透明绝缘基板上的重新分配线的一重新分配基板；(b)提供具有含一激活表面与至少一非激活表面的一半导体基板的一晶片，该晶片另具有形成于该激活表面上的芯片垫；(c)结合该重新分配基板至该晶片，使得该重新分配线的第一部分连接该芯片垫；(d)于该晶片中形成自该激活表面延伸至该非激活表面的孔，使得该重新分配线的第二部分暴露至该孔；(e)形成传导线于该孔中与该非激活表面上；(f)形成外部连接终端于形成于该非激活表面上的传导在线；及(g)沿着一刻划线区分该重新分配基板与该晶片。于本发明的方法中，该步骤(a)包含(a-1)提供该透明绝缘基板；(a-2)提供一绝缘层于该透明绝缘基板上；(a-3)藉由图案化该绝缘层形成凸块；及(a-4)形成该重新分配线于该凸块上。
该透明绝缘基板可由玻璃、石英、或丙烯酸树脂制成。该步骤(a-3)可另具有藉由图案化该绝圆层形成屏障。亦，该步骤(a-3)可形成凸块对，各对具有连接该芯片垫的一第一凸块与暴露至该孔的一第二凸块。该绝缘层可由聚合物制成。
该重新分配线可由铜(Cu)、镍(Ni)、钛(Ti)、铬(Cr)、钨(W)、或其合成物制成。该步骤(a-4)可使用溅镀、电镀、沉积、无电电镀、丝网印刷、或喷墨加以实施。
该晶片可另具有形成于该激活表面上的一影像感应区域。另外，该晶片可另具有形成于该芯片垫上的至少一垫金属层。该垫金属层可由金(Au)、镍(Ni)、铝(Al)、铜(Cu)、锡(Sn)、或其合成物制成。
该步骤(c)中的重新分配基板与晶片间的结合是使用一光敏性胶黏剂加以建立。该步骤(c)中的重新分配线与芯片垫间的连接是使用一铟(In)型胶黏剂加以作成。或者，该步骤(c)中的重新分配基板与晶片间的结合是使用异向性传导材料或纳米互连糊状物加以作成。
本发明的方法可另包含于步骤(c)之后，机械研磨该晶片的一底表面，以减小该晶片的厚度。该晶片可藉由该研磨步骤变细至约50～150μm的厚度。该步骤(d)可使用雷射钻孔、机械钻孔、等离子体乾蚀刻、或反应离子蚀刻加以实施。
该步骤(e)可包含形成至少一传导层于该孔中及于该非激活表面上，及选择性移除该传导层，以产生该传导线。或者，该步骤(e)可包含形成对应至该非激活表面上的传导线的一光阻图案，及透过该光阻图案执行一选择电镀，以产生该传导线。
该传导线可具有第一传导线与形成于该第一传导在线的第二传导线。该第一传导线可由钨(W)、钛(Ti)、铝(Al)、锆(Zr)、铬(Cr)、铜(Cu)、金(Au)、银(Ag)、铅(Pb)、镍(Ni)、氧化铟锡(ITO)、或其合成物加以形成。该第二传导线可由选自铬(Cr)、钛(Ti)、钨(W)、铜(Cu)、镍(Ni)、金(Au)、及钨化钛(TiW)中的一合成物加以形成。
本发明的方法可另包含于该步骤(e)之后，形成一介电保护层于该传导在线，以保护该传导线及定义终端位置。
该步骤(f)中之外部连接终端可形成于该半导体基板的一底表面上，或者于该半导体基板的至少一横向侧表面上。
附图说明
图1A至图1K是显示用以制造一传统晶片层封装的一方法的剖面图；
图2A至图2D是显示根据本发明的一范例实施例用以生产一重新分配基板的一方法的剖面图；
图3是显示根据本发明的一范例实施例的一晶片的一剖面图；
图4A至图4I是显示根据本发明的一范例实施例用以制造一晶片层芯片尺度封装的一方法的剖面图；
图5A至图5E是显示根据本发明的另一范例实施例用以制造一晶片层芯片尺度封装的一方法的剖面图。
附图标号说明：1-硅晶片；10a-IC芯片；10b-IC芯片；11-激活表面；12-芯片垫；13-划线区域；14-垫延伸层；16-被动层；18-环氧化物；20-第一玻璃基板；22-球垫；24-刻痕；26-图案化铅层；32-锡球；34-第二玻璃基板；36-环氧化物；38-菱形区域；100-重新分配基板；110-透明基板；112-绝缘层；114-周围屏障；116-图案化凸块；118-重新分配线；120-光敏性胶黏剂；122-铟(In)型胶黏剂；200-晶片；201-半导体基板；202-激活表面；204-非激活表面；212-影像感应区域；214-芯片垫；216-被动层；218-垫金属层；220-孔；222-第一传导层；223-第一传导线；224-第二传导层；225-第二传导线；226-光阻罩；228-介电保护层；230-外部连接终端；232-划线区域；240-光阻层；242-热固树脂。
具体实施方式
现在开始将参照附图更完整说明本发明的范例非限制实施例。然而，本发明可实施于许多不同形式中，且不应解释为限制于在此提出的范例实施例。而是提供该公开实施例，使得此公开将彻底且完整，且将完全传达本发明的范畴至熟悉该领域的普通一般技术人员。本发明的原则与特征可于不超出本发明的权利要求保护范畴外实施于各种各样与许多实施例中。
应注意不详细描述或示范已知结构与制程，以避免混淆本发明的本质。亦应注意附图并非依比例尺绘制。而是为了示范的简化与澄清的目的，相对其他组件夸张某些组件的尺寸。类似组件符号用于不同附图的类似与对应部分。
于剖面图中，第2A至图2D显示根据本发明的一范例实施例用以生产一重新分配基板的一方法。
图2A显示提供一透明绝缘基板110做为该重新分配基板100的基底的一步骤。该透明基板110具有约300～500μm的一厚度，且如由玻璃制成。该透明基板110可由其它材料制成，例如石英、丙烯酸树脂、及具有良好光透射率的许多其它适当材料。此外，若有需要，该透明基板110可涂上氧化铟锡(ITO)。
图2B显示提供一绝缘层112于该透明基板110的一表面上的一步骤。该绝缘层112具有约10～100μm的一厚度，且将于一后续步骤中制造至图案化凸块及周围屏障中。该绝缘层112是由聚合物制成，例如聚亚酰胺。然而，该绝缘层112的材料仅为示范，且其它适当材料或可使用为该绝缘层112。
图2C显示形成该图案化凸块116与该周围屏障114的一步骤。该绝缘层112使用业界中已知的光蚀刻技术图案化，因此获得该凸块116与该屏障114。如稍后所述般，当该重新分配基板100结合至一晶片时，该凸块116将同时接触该晶片的一芯片垫与一传导线。因此可能想要该凸块16成对。
本发明的晶片层芯片尺度封装可有利应用至一光电子装置，例如一影像传感器芯片，其具有由配置于一芯片激活表面上的一像素数组与一微米透镜所组成的一影像感应区域。该屏障114将环绕该影像感应区域，以避免不想要的微粒污染该影像感应区域。
图2D显示形成重新分配线118的一步骤，其各连接一对凸块116。若有必要，该重新分配线118可形成于该屏障114上。该重新分配线118可由铜(Cu)、镍(Ni)、钛(Ti)、铬(Cr)、钨(W)、及其合成物所制成，包含铬/铜/钛(Cr/Cu/Ti)、钛/铜/镍(Ti/Cu/Ni)、铬/铜/镍(Cr/Cu/Ni)、及钛/钨/镍(Ti/W/Ni)。然而，应了解上列金属仅经由示范加以呈现，且并非作为本发明之一限制。各金属层可具有范围自约50至约25μm的一厚度。
溅镀或电镀可用以形成该重新分配线118，且一足够光阻罩可另用以图案化该重新分配线118。应了解该公开技术仅为范例，且并非视为本发明之一限制。业界中已知的许多其它适当技术或者可用以形成该重新分配线118，例如沉积、无电电镀、丝网印刷、及喷墨。
上文中所讨论的重新分配基板100将结合至该晶片，且用于该晶片层芯片尺度封装的制造。
于一剖面图中，图3显示根据本发明的一范例实施例的一晶片200。
该晶片是由半导体材料制成，例如单晶硅，且基于具有约700～800μm的一厚度的一薄碟型基板201。该半导体基板201可具有一激活表面202与一非激活表面204。于下方该非激活表面204将指该激活表面的相对表面或侧表面其中之一。
该半导体基板201的激活表面202具有复数个芯片垫214使用为芯片内部电路(未显示)的电气连接终端。除了该芯片垫214之外，该激活表面202覆盖着一被动层216。该芯片垫214主要由铝(Al)形成。然而，该芯片垫214可由其它适当材料形成，例如铝(Al)与铜(Cu)的合金。该钝化层216可由氧化硅或氮化硅形成。
可想要该芯片垫214以致少一金属层涂覆，其于下方将称为一垫金属层218。该垫金属层218可由与用于上述重新分配层的相同金属或其它金属形成。最好，金(Au)、镍(Ni)、铝(Al)、或铜(Cu)可用于该垫金属层218，且沉积约1～3μm的一厚度。另外，防氧化金属，例如金(Au)，或传导氧化金属，例如锡(Sn)，可另沉积介于约100与约5μm间的一厚度。该垫金属层218可使用已知技术加以形成，包含例如(但非限制于)蒸发或溅镀脱除(sputterlift-off)。
如上所讨论般，于具有光电子装置的晶片的情况中，该半导体基板201的激活表面202亦可具有该影像感应区域212。
上文中所述的晶片200结合至该重新分配基板，于图2D中为100，且该晶片层芯片尺度封装制造自此。
于剖面图中，图4A至图4I显示根据本发明的一范例实施例用以制造一晶片层芯片尺度封装的一方法。
图4A显示结合该重新分配基板100至该晶片200的一步骤。举例来说，该结合是使用一光敏性胶黏剂120加以建立，例如环氧化物。该光敏性胶黏剂120选择性涂覆于该晶片200或该重新分配基板100上，不覆盖该晶片200的影像感应区域212。再者，举例来说，一铟(In)型胶黏剂122使用雷射焊接连接该晶片200的芯片垫214与该重新分配基板100的凸块116的对应者。
于其它实施例中，该重新分配基板100与该晶片200间的结合可使用异向性传导材料、纳米互连糊状物、或业界中已知的任何其它材料加以作成。
图4B显示一晶片背磨步骤。于该晶片200结合至该重新分配基板100的后，若有需要，可机械研磨该半导体基板201，以减小该晶片200的厚度。该晶片200可由该研磨步骤变细至约50～150μm的厚度。
图4C显示形成孔220于该晶片200中的一步骤。如上所讨论般，该重新分配基板100的图案化凸块116成对。另外，各凸块对同晶片200的芯片垫214相接触。各孔220与各凸块的另一个相应和一致。该孔220可藉由钻孔，例如雷射钻孔或机械钻孔、蚀刻，例如等粒子体乾蚀刻或反应离子蚀刻、或业界中已知的其它传统孔形成技术加以形成。
蚀刻孔的一范例情况示范于图5A至图5E中。参照图5A至图5E，一开始，该半导体基板201的底表面204涂上一光阻层240(图5A)。接着，实施暴露与显影，以产生一光阻图案241(图5B)。然后，使用该光阻图案241实施一工序，以选择性蚀刻该半导体基板201(图5C)。举例来说，该工序可使用一六氟化硫(SF6)气体作为一蚀刻剂气体。其后，移除该光阻图案，且该半导体基板201的底表面204涂上一热固树脂242，例如环氧化物(图5D)。组合或喷洒技术可用以涂覆该热固树脂242。然后，藉由选择性蚀刻该热固树脂242，该孔形成于该树脂242中，而非该半导体基板201中(图5E)。
于该孔220形成于该晶片200中之后，形成一传导层222。图4D显示形成该传导层222于该孔220中及于该半导体基板201的底表面204上的一步骤。该传导层222可由具有高传导性的金属或瑕疵金属形成。举例来说，该传导层222可实施钨(W)、钛(Ti)、铝(Al)、锆(Zr)、铬(Cr)、铜(Cu)、金(Au)、银(Ag)、铅(Pb)、镍(Ni)、氧化铟锡(ITO)、或其合成物。最好，铬(Cr)、铜(Cu)及镍(Ni)可一个接着一个电镀，以形成该传导层222。
于该传导层222(于下方称为该第一传导层)形成之后，若有需要，可另形成一第二传导层。第4E图显示作为一黏着层、一种子层、一扩散阻挡层、及一焊料淋湿层的第二传导层224的一步骤。该第二传导层224可由选自铬(Cr)、钛(Ti)、钨(W)、铜(Cu)、镍(Ni)、金(Au)、及钨化钛(TiW)中的合成物加以形成。举例来说，可能使用钛/铜/镍/金(Ti/Cu/Ni/Au)、铬/铜/镍/金(Cr/Cu/Ni/Au)、或钨化钛/镍(TiW/Ni)。然而，应了解为该第一与第二传导层222与224的上列材料仅经由示范加以呈现，且并非作为本发明之一限制。
图4F显示形成第一传导线223与第二传导线225的一步骤，两着皆可藉由透过一光阻罩226选择性移除该第一与第二传导层222与224加以产生。该传导层222与224的选择性移除可使用业界中已知的蚀刻或雷射整修。
代替选择性移除该传导层，传统图案镀敷可用以形成该传导线223与225。该图案镀敷包含事先形成对应至该传导线的一光阻图案，及接着透过该光阻图案执行一选择性电镀。
图4G显示形成一介电保护层228的一步骤，举例来说，其可由传动光焊阻(PSR)材料制成。该介电保护层228不只保护该传导线223与225的大部分，但亦暴露该传导线223与225的一些部分，以定义终端位置。
图4H显示形成外部连接终端230的一步骤。不同种类的焊料、金(Au)、或其它替代材料可形成塑形为凸块或球的外部连接终端230。该外部连接终端230配置于该半导体基板201的非激活表面上。也就是该终端230可如所述般形成于该半导体基板201的底表面204上，或者于该半导体基板201的至少一横向侧表面上。
最后，图4I显示一晶片菱形化步骤。该晶片200与该重新分配基板100沿着一划线区域232分割，因此获得制造于该个别芯片上的WLP。此步骤可使用一钻石轮或一雷射切割工具。
如上文中所完整讨论般，根据本发明的方法使用该重新分配基板以电气连接该激活表面上的芯片垫与该非激活表面上的封装终端。该重新分配基板可与该晶片分离生产，且接着结合至该晶片，因此整个制程变得较简单且改进该生产力。
本发明的方法不但用该重新分配基板而且用该孔实施电气连接，其两者皆位于该芯片区域中，而非于该划线区域中。因此不需要增加该晶片的一划线区域，亦不需使用具有减少芯片数的一不利晶片。
再者，使用位于该芯片区域中而非该划线区域中的孔的电气连接对于减少封装大小较有利。
此外，使用该凸块对上的重新分配线的电气连接提供绝佳图案设计弹性，而不考虑该芯片垫与该孔的位置。
虽然本发明已经参照其范例实施例特别显示与描述，熟悉该项技术的普通一般技术人员应了解于不超出所附权利要求所定义的本发明精神与范畴外于其中可做不同形式与细节的变更。

Claims (24)

1.一种用以制造一晶片层芯片尺寸封装的方法，其特征在于，该方法包含：
(a)生产具有一透明绝缘基板与形成于该透明绝缘基板上的重新分配线的一重新分配基板；
(b)提供具有含一激活与至少一未激活表面的一半导体基板的一晶片，该晶片另具有形成于该激活表面上的芯片垫；
(c)结合该重新分配基板至该晶片，使得该重新分配线的第一部分连接该芯片垫；
(d)于该晶片中形成自该激活表面延伸至该非激活表面的孔，使得该重新分配线的第二部分暴露至该孔；
(e)形成传导线于该孔中与该非激活表面上；
(f)形成外部连接终端于形成于该非激活表面上的传导在线；及
(g)沿着一刻划线划分该重新分配基板与该晶片。
2.如权利要求1所述的方法，其特征在于，该步骤(a)包含：
(a-1)提供该透明绝缘基板；
(a-2)提供一绝缘层于该透明绝缘基板上；
(a-3)藉由图案化该绝缘层形成凸块；及
(a-4)形成该重新分配线于该凸块上。
3.如权利要求1所述的方法，其特征在于，该透明绝缘基板是由玻璃、石英、或丙烯酸树脂制成。
4.如权利要求2所述的方法，其特征在于，该步骤(a-3)另具有藉由图案化该绝缘层形成屏障。
5.如权利要求2所述的方法，其特征在于，该步骤(a-3)形成凸块对，各对具有连接该芯片垫的一第一凸块与暴露至该孔的一第二凸块。
6.如权利要求2所述的方法，其特征在于，该绝缘层是由聚合物制成。
7.如权利要求1所述的方法，其特征在于，该重新分配线是由铜(Cu)、镍(Ni)、钛(Ti)、铬(Cr)、钨(W)、或其合成物制成。
8.如权利要求2所述的方法，其特征在于，该步骤(a-4)使用溅镀、电镀、沉积、无电电镀、丝网印刷、或喷墨加以实施。
9.如权利要求1所述的方法，其特征在于，该晶片另具有形成于该激活表面上的一影像感应区域。
10.如权利要求1所述的方法，其特征在于，该晶片另具有形成于该芯片垫上的至少一垫金属层。
11.如权利要求10所述的方法，其特征在于，该垫金属层是由金(Au)、镍(Ni)、铝(Al)、铜(Cu)、锡(Sn)、或其合成物制成。
12.如权利要求1所述的方法，其特征在于，该步骤(c)中的重新分配基板与晶片间的结合是使用一光敏性胶黏剂加以建立。
13.如权利要求1所述的方法，其特征在于，该步骤(c)中的重新分配线与芯片垫间的连接是使用一铟(In)型胶黏剂加以作成。
14.如权利要求1所述的方法，其特征在于，该步骤(c)中的重新分配基板与晶片间的结合是使用异向性传导材料或纳米互连糊状物加以作成。
15.如权利要求1所述的方法，其特征在于，其另包含：
于步骤(c)之后，机械研磨该晶片的一底表面，以减小该晶片的厚度。
16.如权利要求15所述的方法，其特征在于，该晶片藉由该研磨步骤变细至约50～150μm的厚度。
17.如权利要求1所述的方法，其特征在于，该步骤(d)使用雷射钻孔、机械钻孔、等离子体乾蚀刻、或反应离子蚀刻加以实施。
18.如权利要求1所述的方法，其特征在于，该步骤(e)包含形成至少一传导层于该孔中及于该非激活表面上，及选择性移除该传导层，以产生该传导线。
19.如权利要求1所述的方法，其特征在于，该步骤(e)包含形成对应至该非激活表面上的传导线的一光阻图案，及透过该光阻图案执行一选择电镀，以产生该传导线。
20.如权利要求1所述的方法，其特征在于，该传导线具有第一传导线与形成于该第一传导在线的第二传导线。
21.如权利要求20所述的方法，其特征在于，该第一传导线是由钨(W)、钛(Ti)、铝(Al)、锆(Zr)、铬(Cr)、铜(Cu)、金(Au)、银(Ag)、铅(Pb)、镍(Ni)、氧化铟锡(ITO)、或其合成物加以形成。
22.如权利要求20所述的方法，其特征在于，该第二传导线是由选自铬(Cr)、钛(Ti)、钨(W)、铜(Cu)、镍(Ni)、金(Au)、及钨化钛(TiW)中的一合成物加以形成。
23.如权利要求1所述的方法，其特征在于，其另包含：
于该步骤(e)之后，形成一介电保护层于该传导在线，以保护该传导线及确定终端位置。
24.如权利要求1所述的方法，其特征在于，该步骤(f)中的外部连接终端形成于该半导体基板的一底表面上，或者于该半导体基板的至少一横向侧表面上。
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