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CN1773694A - Encapsulation structure with high adhesion between substrate and encapsulant - Google Patents

Encapsulation structure with high adhesion between substrate and encapsulant Download PDF

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Publication number
CN1773694A
CN1773694A CN 200410090685 CN200410090685A CN1773694A CN 1773694 A CN1773694 A CN 1773694A CN 200410090685 CN200410090685 CN 200410090685 CN 200410090685 A CN200410090685 A CN 200410090685A CN 1773694 A CN1773694 A CN 1773694A
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CN
China
Prior art keywords
conductive
substrate
core layer
wire
semiconductor chip
Prior art date
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Granted
Application number
CN 200410090685
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Chinese (zh)
Other versions
CN100392845C (en
Inventor
罗光淋
方仁广
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CNB200410090685XA priority Critical patent/CN100392845C/en
Publication of CN1773694A publication Critical patent/CN1773694A/en
Application granted granted Critical
Publication of CN100392845C publication Critical patent/CN100392845C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention relates to a packaging structure with high adhesiveness between a substrate and a packaging colloid. The packaging structure comprises a substrate, a semiconductor chip, a plurality of bonding wires and a packaging colloid. The substrate has a core layer, a plurality of conductive traces and a solder mask layer. The conductive traces are located on the upper surface of the core layer, each of the conductive traces has a conductive finger and a connecting line, wherein the conductive finger is used for wire bonding, and the connecting line is used for electrically connecting the conductive finger to a preset position. The connecting wire has an inner portion and an outer portion. The solder mask layer is positioned on the upper surface of the core layer and covers the outer part of the connecting wire. The packaging colloid coats the upper surface of the core layer, the semiconductor chip and the solder mask layer, and contacts the inner part of the connecting wire. Therefore, the adhesive force between the encapsulant and the substrate can be increased, so that the encapsulant is not peeled off from the substrate.

Description

The encapsulating structure that between substrate and packing colloid, has high adhesion
Technical field
The present invention relates to a kind of encapsulating structure, in detail, the present invention relates to a kind of adhesive encapsulating structure between substrate and packing colloid that increases.
Background technology
With reference to figure 1 and Fig. 2, its shown respectively conventional encapsulating structure on look and cross-sectional schematic, wherein Fig. 1 does not show packing colloid, Fig. 2 is the cutaway view of 2-2 direction among Fig. 1.This routine encapsulating structure 1 comprises a substrate 11, semiconductor chip 12, many closing lines 13, a packing colloid 14 and a plurality of soldered balls 15.
This substrate 11 comprises a sandwich layer (core layer) 111, a plurality of conductive trace (trace) 112 and a solder mask (solder mask) 113.This sandwich layer 111 is made by conventional materials such as epoxy resin, pi resin, BT resin or FR4 resins usually, and it has a upper surface and a lower surface, and this upper surface has a chip disposal area.These conductive traces 112 are positioned at the upper surface of this sandwich layer 111, and each these conductive traces 112 comprise a conductive finger (finger) 1121, a connecting line 1122 and a via (via) 114.This conductive finger 1121 engages in order to line, and this connecting line 1122 is in order to be electrically connected this conductive finger 1121 to this via 114.This solder mask 113 is positioned at this sandwich layer 111 upper surfaces, and covers these connecting lines 1122 and via 114 fully, only exposes these conductive fingers 1121.Therefore in Fig. 1, these connecting lines 1122 and via 114 all are represented by dotted lines.
This semiconductor chip 12 is attached at this chip disposal area by an adhesion coating (not shown), and this semiconductor chip 12 has a plurality of joint sheets (bonding pad) 121.These closing lines 13 are in order to be electrically connected these joint sheet 121 and these conductive fingers 1121.This packing colloid 14 coats these substrate 11 upper surfaces, this semiconductor chip 12, these closing lines 13 and this solder mask 113 of part.
These soldered balls 15 are positioned at the lower surface of this sandwich layer 111 and are exposed to outside this packing colloid 14, in order to be electrically connected this semiconductor chip 12 to external device.
With reference to figure 3, the cross-sectional schematic of 3-3 direction in its displayed map 1.By finding out among the figure, because this solder mask 113 covers this connecting line 1122, therefore after the sealing operation was finished, this packing colloid 14 contacted these solder masks 113.Because the bond strength between 113 two kinds of materials of this packing colloid 14 and this solder mask is not high, it is more smooth to add that this solder mask 113 covers this formed plane, connecting line 1122 backs, so this packing colloid 14 is peeled off from this substrate 11 easily, thereby cause the encapsulation failure.
Therefore, be necessary to provide the encapsulating structure of the high adhesion of a kind of innovation and tool progressive to solve the problems referred to above.
Summary of the invention
The object of the present invention is to provide a kind of encapsulating structure of high adhesion, the conductive trace on the substrate is wherein not exclusively covered by solder mask, that is to say that this conductive trace exposes a part and contacts with packing colloid after the sealing operation.Therefore, can increase the adhesion strength of packing colloid and substrate, make this packing colloid be difficult for from this strippable substrate.
For achieving the above object, the invention provides a kind of encapsulating structure of high adhesion, it comprises: a substrate, semiconductor chip, many closing lines and a packing colloid.
This substrate comprises a sandwich layer, a plurality of conductive trace and a solder mask.This sandwich layer has a upper surface, and this upper surface has a chip disposal area.These conductive traces are positioned at the upper surface of this sandwich layer, each these conductive traces comprise a conductive finger and a connecting line, this conductive finger engages in order to line, and this connecting line is in order to be electrically connected this conductive finger to one precalculated position, and this connecting line comprises an inside part and an Outboard Sections.This solder mask is positioned at around the outer rim of this sandwich layer upper surface, and covers the Outboard Sections of this connecting line.
This semiconductor chip is attached at this chip disposal area by an adhesion coating, and this semiconductor chip has a plurality of joint sheets.These closing lines are in order to be electrically connected these joint sheets and these conductive fingers.This packing colloid coats this upper surface of base plate, this semiconductor chip, these closing lines and this solder mask of part, and this packing colloid directly contacts the inside part of this connecting line.
Description of drawings
Fig. 1 show conventional encapsulating structure on look schematic diagram, wherein do not show packing colloid;
The cross-sectional schematic of 2-2 direction in Fig. 2 displayed map 1;
The cross-sectional schematic of 3-3 direction in Fig. 3 displayed map 1;
Fig. 4 show encapsulating structure according to the preferred embodiment of the invention on look schematic diagram, wherein do not show packing colloid;
The cross-sectional schematic of 5-5 direction in Fig. 5 displayed map 4; With
The cross-sectional schematic of 6-6 direction in Fig. 6 displayed map 4.
Embodiment
With reference to figure 4 and Fig. 5, its show respectively encapsulating structure according to the preferred embodiment of the invention on look and cross-sectional schematic, wherein Fig. 4 does not show packing colloid.This encapsulating structure 2 comprises a substrate 21, semiconductor chip 22, many closing lines 23, a packing colloid 24 and a plurality of soldered balls 25.
This substrate 21 comprises a sandwich layer 211, a plurality of conductive trace 212 and a solder mask 213.This sandwich layer 211 is made by conventional materials such as epoxy resin, pi resin, BT resin or FR4 resins usually, and it has a upper surface and a lower surface, and this upper surface has a chip disposal area.These conductive traces 212 are positioned at the upper surface of this sandwich layer 211, each these conductive traces 212 comprise a conductive finger 2121 and a connecting line 2122, this conductive finger 2121 engages in order to line, this connecting line 2122 is in order to be electrically connected this conductive finger 2121 to one precalculated positions, and this precalculated position is the position of a via 214 normally.This connecting line 2122 can be divided into an inside part 2122a and an Outboard Sections 2122b, and this inside part 2122a is connected to this conductive finger 2121, and this Outboard Sections 2122b is connected to this via 214.This solder mask 213 is positioned at around the outer rim of these sandwich layer 211 upper surfaces, and cover the Outboard Sections 2122b of this connecting line 2122, the inside part 2122a that is to say this connecting line 2122 is not covered by this solder mask 213, and the inside part 2122a of this connecting line 2122 is exposed to outside this solder mask 213.Therefore, the inside part 2122a of this connecting line 2122 represents that with solid line the Outboard Sections 2122b of this connecting line 2122 is represented by dotted lines.
This semiconductor chip 22 is to be attached at this chip disposal area by an adhesion coating, and this semiconductor chip 22 has a plurality of joint sheets 221.These closing lines 23 are in order to be electrically connected these joint sheet 221 and these conductive fingers 2121.This packing colloid 24 coats these substrate 21 upper surfaces, this semiconductor chip 22, these closing lines 23 and this solder mask 213 of part, and this packing colloid 24 directly contacts the inside part 2122a of this connecting line 2122.These soldered balls 25 are positioned at the lower surface of this sandwich layer 211 and are exposed to outside this packing colloid 24, in order to be electrically connected this semiconductor chip 22 to external device.
With reference to figure 6, the cross-sectional schematic of 6-6 direction in its displayed map 4.By finding out among the figure, because this solder mask 213 does not cover the inside part 2122a of this connecting line 2122, therefore after the sealing operation was finished, this packing colloid 24 directly contacted the inside part 2122a of this connecting line 2122 and the upper surface of this sandwich layer 211.Because the bond strength that this packing colloid 24 and this sandwich layer are 211 is better than the bond strength of 213 of this packing colloid 24 and this solder masks, the formed concavo-convex profile of inside part 2122a that adds this connecting line 2122 can increase surface roughness, so this packing colloid 24 is difficult for peeling off from this substrate 21.
The foregoing description only is explanation principle of the present invention and its effect, but not in order to restriction the present invention.Therefore, one of ordinary skill in the art can make amendment to the foregoing description under the situation of spirit of the present invention and change.Interest field of the present invention claim as described later is listed.

Claims (6)

1.一种高粘着性的封装结构，其包括：1. A highly adhesive packaging structure, comprising: 一基板，其包括：A substrate comprising: 一芯层，其具有一上表面和一下表面，该上表面具有一芯片容置区；a core layer, which has an upper surface and a lower surface, and the upper surface has a chip accommodation area; 多个导电迹线，其位于该芯层的上表面，各个该等导电迹线包含一导电指和一连接线，该导电指用以线接合，该连接线用以电气连接该导电指至一预定位置，该连接线包括一内侧部分和一外侧部分；和a plurality of conductive traces, which are located on the upper surface of the core layer, each of the conductive traces includes a conductive finger and a connecting wire, the conductive finger is used for wire bonding, and the connecting wire is used to electrically connect the conductive finger to a at a predetermined location, the connecting line includes an inner portion and an outer portion; and 一阻焊层，其覆盖该芯层上表面的外缘周围，且覆盖该连接线的外侧部分；a solder resist layer covering around the outer edge of the upper surface of the core layer and covering the outer portion of the connecting wire; 一半导体芯片，其通过一粘着层而贴附于该芯片容置区，该半导体芯片具有多个接合垫；A semiconductor chip, which is attached to the chip accommodation area through an adhesive layer, the semiconductor chip has a plurality of bonding pads; 多条接合线，其用以电气连接该等接合垫和该等导电指；和a plurality of bonding wires for electrically connecting the bonding pads and the conductive fingers; and 一封装胶体，其包覆该芯层上表面、该半导体芯片、该等接合线和部分该阻焊层，该封装胶体直接接触该连接线的内侧部分。An encapsulant encapsulating the upper surface of the core layer, the semiconductor chip, the bonding wires and part of the solder resist layer, the encapsulating encapsulant directly contacts the inner part of the connecting wire. 2.根据权利要求1所述的封装结构，其中该基板更包括多个导通孔，该连接线用以电气连接该导电指至该导通孔。2. The package structure according to claim 1, wherein the substrate further comprises a plurality of via holes, and the connection lines are used to electrically connect the conductive fingers to the via holes. 3.根据权利要求1所述的封装结构，其更包括多个焊球，位于该芯层的下表面且暴露于该封装胶体之外，用以电气连接该半导体芯片至外界装置。3 . The package structure according to claim 1 , further comprising a plurality of solder balls located on the lower surface of the core layer and exposed to the encapsulant, for electrically connecting the semiconductor chip to external devices. 4 . 4.一种用以封装结构的基板，其包括：4. A substrate for packaging structures, comprising: 一芯层，其具有一上表面，该上表面具有一芯片容置区；a core layer, which has an upper surface, and the upper surface has a chip accommodation area; 多个导电迹线，其位于该芯层的上表面，各个该等导电迹线包含一导电指和一连接线，该导电指用以线接合，该连接线用以电气连接该导电指至一预定位置，该连接线包括一内侧部分和一外侧部分；和a plurality of conductive traces, which are located on the upper surface of the core layer, each of the conductive traces includes a conductive finger and a connecting wire, the conductive finger is used for wire bonding, and the connecting wire is used to electrically connect the conductive finger to a at a predetermined location, the connecting line includes an inner portion and an outer portion; and 一阻焊层，其覆盖该芯层上表面的外缘周围，且覆盖该连接线的外侧部分，该连接线的内侧部分暴露于该阻焊层之外。A solder resist layer covers the periphery of the upper surface of the core layer and covers the outer portion of the connection line, and the inner portion of the connection line is exposed outside the solder resist layer. 5.根据权利要求4所述的基板，其更包括多个导通孔，该连接线用以电气连接该导电指至该导通孔。5 . The substrate according to claim 4 , further comprising a plurality of via holes, and the connecting wire is used to electrically connect the conductive fingers to the via holes. 6.一种高粘着性的封装结构，其包括一基板、一半导体芯片和一封装胶体，该基板的一表面上具有多个导电迹线，各个该等导电迹线包含一导电指和一连接线，该导电指用以线接合，该连接线用以电气连接该导电指至一预定位置，其特征在于：6. A package structure with high adhesiveness, which comprises a substrate, a semiconductor chip and an encapsulant, a plurality of conductive traces are arranged on a surface of the substrate, and each of these conductive traces includes a conductive finger and a connection Wire, the conductive finger is used for wire bonding, and the connection wire is used to electrically connect the conductive finger to a predetermined position, characterized in that: 该封装胶体直接接触该连接线。The encapsulant directly contacts the connecting wire.
CNB200410090685XA 2004-11-12 2004-11-12 Packaging structure with high adhesiveness between substrate and packaging colloid Expired - Lifetime CN100392845C (en)

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CN100392845C CN100392845C (en) 2008-06-04

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101882607B (en) * 2009-05-08 2012-06-13 日月光半导体制造股份有限公司 Packaging structure of chip with conductor layer
CN103178034A (en) * 2011-12-21 2013-06-26 矽品精密工业股份有限公司 Package structure, package substrate structure and manufacturing method thereof
CN105261572A (en) * 2011-12-21 2016-01-20 联发科技股份有限公司 Semiconductor package
TWI822230B (en) * 2022-08-05 2023-11-11 友達光電股份有限公司 Luminous panel

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1157790C (en) * 2000-11-27 2004-07-14 矽品精密工业股份有限公司 Chip stacking and packaging structure
TW533518B (en) * 2002-05-21 2003-05-21 Siliconware Precision Industries Co Ltd Substrate for carrying chip and semiconductor package having the same
TW564534B (en) * 2002-10-14 2003-12-01 Siliconware Precision Industries Co Ltd Chip carrier
TWI229574B (en) * 2002-11-05 2005-03-11 Siliconware Precision Industries Co Ltd Warpage-preventing circuit board and method for fabricating the same
DE10255844B3 (en) * 2002-11-29 2004-07-15 Infineon Technologies Ag Integrated circuit manufacturing method of chip scale package, involves attaching solder balls in area that is uncovered by resist element, of patterned rewriting element, in patterned form
KR100584965B1 (en) * 2003-02-24 2006-05-29 삼성전기주식회사 Package Substrate and Manufacturing Method Thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101882607B (en) * 2009-05-08 2012-06-13 日月光半导体制造股份有限公司 Packaging structure of chip with conductor layer
CN103178034A (en) * 2011-12-21 2013-06-26 矽品精密工业股份有限公司 Package structure, package substrate structure and manufacturing method thereof
CN103178034B (en) * 2011-12-21 2015-09-16 矽品精密工业股份有限公司 Package structure, package substrate structure and manufacturing method thereof
CN105261572A (en) * 2011-12-21 2016-01-20 联发科技股份有限公司 Semiconductor package
CN105261572B (en) * 2011-12-21 2018-11-02 联发科技股份有限公司 Semiconductor package
TWI822230B (en) * 2022-08-05 2023-11-11 友達光電股份有限公司 Luminous panel

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Granted publication date: 20080604