CN100392845C - Packaging structure with high adhesiveness between substrate and packaging colloid - Google Patents

Abstract

The invention relates to a packaging structure with high adhesiveness between a substrate and a packaging colloid. The packaging structure comprises a substrate, a semiconductor chip, a plurality of bonding wires and a packaging colloid. The substrate has a core layer, a plurality of conductive traces and a solder mask layer. The conductive traces are located on the upper surface of the core layer, each of the conductive traces has a conductive finger and a connecting line, wherein the conductive finger is used for wire bonding, and the connecting line is used for electrically connecting the conductive finger to a preset position. The connecting wire has an inner portion and an outer portion. The solder mask layer is positioned on the upper surface of the core layer and covers the outer part of the connecting wire. The packaging colloid coats the upper surface of the core layer, the semiconductor chip and the solder mask layer, and contacts the inner part of the connecting wire. Therefore, the adhesive force between the encapsulant and the substrate can be increased, so that the encapsulant is not peeled off from the substrate.

Description

Encapsulation structure with high adhesion between substrate and encapsulant

technical field

The invention relates to a packaging structure, in particular, the invention relates to a packaging structure which can increase the adhesion between the substrate and the packaging colloid.

Background technique

Referring to FIG. 1 and FIG. 2 , they respectively show a top view and a schematic cross-sectional view of a conventional packaging structure, wherein FIG. 1 does not show the encapsulant, and FIG. 2 is a cross-sectional view along the direction 2-2 in FIG. 1 . The conventional package structure 1 includes a substrate 11 , a semiconductor chip 12 , a plurality of bonding wires 13 , an encapsulant 14 and a plurality of solder balls 15 .

The substrate 11 includes a core layer 111 , a plurality of conductive traces 112 and a solder mask 113 . The core layer 111 is generally made of conventional materials such as epoxy resin, polyimide resin, BT resin or FR4 resin, and has an upper surface and a lower surface, and the upper surface has a chip receiving area. The conductive traces 112 are located on the upper surface of the core layer 111 , and each of the conductive traces 112 includes a conductive finger 1121 , a connection line 1122 and a via 114 . The conductive finger 1121 is used for wire bonding, and the connecting wire 1122 is used for electrically connecting the conductive finger 1121 to the via hole 114 . The solder resist layer 113 is located on the upper surface of the core layer 111 and completely covers the connection lines 1122 and the via holes 114 , only exposing the conductive fingers 1121 . Therefore, in FIG. 1 , the connection lines 1122 and the via holes 114 are represented by dotted lines.

The semiconductor chip 12 is attached to the chip accommodation area through an adhesive layer (not shown in the figure), and the semiconductor chip 12 has a plurality of bonding pads (bonding pads) 121 . The bonding wires 13 are used to electrically connect the bonding pads 121 and the conductive fingers 1121 . The encapsulant 14 covers the upper surface of the substrate 11 , the semiconductor chip 12 , the bonding wires 13 and part of the solder resist layer 113 .

The solder balls 15 are located on the lower surface of the core layer 111 and exposed to the encapsulant 14 for electrically connecting the semiconductor chip 12 to external devices.

Referring to FIG. 3 , it shows a schematic cross-sectional view along direction 3-3 in FIG. 1 . It can be seen from the figure that since the solder resist layer 113 covers the connecting wire 1122 , the encapsulant 14 contacts the solder resist layer 113 after the sealing process is completed. Because the bonding strength between the two materials of the encapsulant 14 and the solder resist layer 113 is not high, and the plane formed by the solder resist layer 113 covering the connecting wire 1122 is relatively flat, the encapsulant 14 is easy to remove from the substrate. 11 peeled off, resulting in package failure.

Therefore, it is necessary to provide an innovative and progressive packaging structure with high adhesiveness to solve the above problems.

Contents of the invention

The object of the present invention is to provide a highly adhesive packaging structure, wherein the conductive traces on the substrate are not completely covered by the solder mask, that is to say, the conductive traces are partially exposed and will be separated from the package after the sealing operation. colloidal contact. Therefore, the adhesive force between the encapsulant and the substrate can be increased, so that the encapsulant is not easily peeled off from the substrate.

To achieve the above object, the present invention provides a highly adhesive packaging structure, which includes: a substrate, a semiconductor chip, a plurality of bonding wires and an encapsulating compound.

The substrate includes a core layer, a plurality of conductive traces and a solder resist layer. The core layer has an upper surface, and the upper surface has a chip accommodation area. The conductive traces are located on the upper surface of the core layer, each of the conductive traces includes a conductive finger and a connecting wire, the conductive finger is used for wire bonding, and the connecting wire is used to electrically connect the conductive finger to a predetermined position , the connection line includes an inner portion and an outer portion. The solder resist layer is located around the outer edge of the upper surface of the core layer and covers the outer portion of the connecting wire.

The semiconductor chip is attached to the chip accommodation area through an adhesive layer, and the semiconductor chip has a plurality of bonding pads. The bonding wires are used to electrically connect the bonding pads and the conductive fingers. The packaging colloid covers the upper surface of the substrate, the semiconductor chip, the bonding wires and part of the solder resist layer, and the packaging colloid directly contacts the inner part of the connecting wires.

Description of drawings

Figure 1 shows a schematic top view of a conventional packaging structure, where the packaging colloid is not shown;

Fig. 2 shows a schematic cross-sectional view of direction 2-2 in Fig. 1;

Figure 3 shows a schematic cross-sectional view of the direction 3-3 in Figure 1;

Fig. 4 shows a schematic top view of a packaging structure according to a preferred embodiment of the present invention, wherein the packaging colloid is not shown;

Figure 5 shows a schematic cross-sectional view of the direction 5-5 in Figure 4; and

FIG. 6 shows a schematic cross-sectional view along the direction 6-6 in FIG. 4 .

Detailed ways

Referring to FIG. 4 and FIG. 5 , they respectively show a top view and a schematic cross-sectional view of a package structure according to a preferred embodiment of the present invention, wherein FIG. 4 does not show the encapsulant. The package structure 2 includes a substrate 21 , a semiconductor chip 22 , a plurality of bonding wires 23 , an encapsulant 24 and a plurality of solder balls 25 .

The substrate 21 includes a core layer 211 , a plurality of conductive traces 212 and a solder resist layer 213 . The core layer 211 is generally made of conventional materials such as epoxy resin, polyimide resin, BT resin or FR4 resin, and has an upper surface and a lower surface, and the upper surface has a chip receiving area. The conductive traces 212 are located on the upper surface of the core layer 211. Each of the conductive traces 212 includes a conductive finger 2121 and a connecting wire 2122. The conductive finger 2121 is used for wire bonding, and the connecting wire 2122 is used for electrical connection. The conductive finger 2121 reaches a predetermined position, which is usually a position of a via hole 214 . The connection line 2122 can be divided into an inner portion 2122a and an outer portion 2122b , the inner portion 2122a is connected to the conductive finger 2121 , and the outer portion 2122b is connected to the via hole 214 . The solder resist layer 213 is located around the outer edge of the upper surface of the core layer 211 and covers the outer portion 2122b of the connection line 2122, that is to say the inner portion 2122a of the connection line 2122 is not covered by the solder resist layer 213, The inner portion 2122 a of the connection line 2122 is exposed outside the solder resist layer 213 . Therefore, the inner portion 2122a of the connection line 2122 is indicated by a solid line, and the outer portion 2122b of the connection line 2122 is indicated by a dotted line.

The semiconductor chip 22 is attached to the chip accommodating area through an adhesive layer, and the semiconductor chip 22 has a plurality of bonding pads 221 . The bonding wires 23 are used to electrically connect the bonding pads 221 and the conductive fingers 2121 . The encapsulant 24 covers the upper surface of the substrate 21 , the semiconductor chip 22 , the bonding wires 23 and part of the solder resist layer 213 , and the encapsulant 24 directly contacts the inner portion 2122 a of the connecting wire 2122 . The solder balls 25 are located on the lower surface of the core layer 211 and exposed to the encapsulant 24 for electrically connecting the semiconductor chip 22 to external devices.

Referring to FIG. 6 , it shows a schematic cross-sectional view along direction 6-6 in FIG. 4 . It can be seen from the figure that since the solder resist layer 213 does not cover the inner portion 2122a of the connecting wire 2122, the encapsulant 24 directly contacts the inner portion 2122a of the connecting wire 2122 and the core after the sealing operation is completed. The top surface of layer 211. Because the bonding strength between the encapsulant 24 and the core layer 211 is better than that between the encapsulant 24 and the solder resist layer 213, and the concave-convex shape formed by the inner portion 2122a of the connection line 2122 can increase the surface roughness. Therefore, the encapsulant 24 is not easily peeled off from the substrate 21 .

The above-mentioned embodiments are only for illustrating the principles and effects of the present invention, but not for limiting the present invention. Therefore, those skilled in the art can make modifications and changes to the above-described embodiments without departing from the spirit of the present invention. The scope of rights of the present invention should be listed in the following claims.

Claims (6)

1. A highly adhesive packaging structure, comprising: A substrate comprising: a core layer, which has an upper surface and a lower surface, and the upper surface has a chip accommodation area; a plurality of conductive traces, which are located on the upper surface of the core layer, each of the conductive traces includes a conductive finger and a connecting wire, the conductive finger is used for wire bonding, and the connecting wire is used to electrically connect the conductive finger to a at a predetermined location, the connecting line includes an inner portion and an outer portion; and a solder resist layer covering around the outer edge of the upper surface of the core layer and covering the outer portion of the connecting wire; A semiconductor chip, which is attached to the chip accommodation area through an adhesive layer, the semiconductor chip has a plurality of bonding pads; a plurality of bonding wires for electrically connecting the bonding pads and the conductive fingers; and An encapsulant encapsulating the upper surface of the core layer, the semiconductor chip, the bonding wires and part of the solder resist layer, the encapsulating encapsulant directly contacts the inner part of the connecting wire. 2. The package structure according to claim 1, wherein the substrate further comprises a plurality of via holes, and the connection lines are used to electrically connect the conductive fingers to the via holes. 3 . The package structure according to claim 1 , further comprising a plurality of solder balls located on the lower surface of the core layer and exposed to the encapsulant, for electrically connecting the semiconductor chip to external devices. 4 . 4. A substrate for packaging structures, comprising: a core layer, which has an upper surface, and the upper surface has a chip accommodation area; a plurality of conductive traces, which are located on the upper surface of the core layer, each of the conductive traces includes a conductive finger and a connecting wire, the conductive finger is used for wire bonding, and the connecting wire is used to electrically connect the conductive finger to a at a predetermined location, the connecting line includes an inner portion and an outer portion; and A solder resist layer covers the periphery of the upper surface of the core layer and covers the outer portion of the connection line, and the inner portion of the connection line is exposed outside the solder resist layer. 5 . The substrate according to claim 4 , further comprising a plurality of via holes, and the connecting wire is used to electrically connect the conductive fingers to the via holes. 6. A package structure with high adhesiveness, which comprises a substrate, a semiconductor chip and an encapsulant, a plurality of conductive traces are arranged on a surface of the substrate, and each of these conductive traces includes a conductive finger and a connection Wire, the conductive finger is used for wire bonding, and the connection wire is used to electrically connect the conductive finger to a predetermined position, characterized in that: The encapsulant directly contacts the connecting wire.

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