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CN1610075A - 半导体装置及其形成方法 - Google Patents

半导体装置及其形成方法 Download PDF

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CN1610075A
CN1610075A CNA200410046205XA CN200410046205A CN1610075A CN 1610075 A CN1610075 A CN 1610075A CN A200410046205X A CNA200410046205X A CN A200410046205XA CN 200410046205 A CN200410046205 A CN 200410046205A CN 1610075 A CN1610075 A CN 1610075A
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layer
semiconductor device
dielectric layer
dielectric constant
low dielectric
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CN1320609C (zh
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章勋明
柯忠祁
包天一
黎丽萍
刘埃森
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
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Abstract

本发明提供一种形成半导体装置的方法，首先，提供一半导体基底，于半导体基底上形成一化学气相沉积的低介电常数介电层；然后，以氢气对化学气相沉积的低介电常数介电层表面进行处理以形成一改质表层。

Description

半导体装置及其形成方法
技术领域
本发明是有关于一种半导体装置的制造方法，特别是有关于一种具有保护层，且由低介电常数材料所形成的金属层间介电层的方法。
背景技术
不论何种电子组件均少不了用来传输电讯的金属导线，半导体集成电路组件亦然，各个组件必藉由适当的内联机当作电性连接，方得以发挥所欲达成的功能。在今日多层内联机制程中，除了制作各层导线图案之外，更须藉助接触孔(contact via)构成，以作为组件接触区与导线之间或是多层导线之间的联系信道。再者，随着集成电路积集度不断地提升，电路设计尺寸逐渐缩小为0.18μm或以下，一种能够同时在介电材料蚀刻形成沟槽(trench)与接触孔，而后填入铜金属材料的镶嵌式铜导线制程(damascene Cu process)正是目前的主流。
其次，为了有效地降低导线间寄生电容(parasitic capacitance)和组件的RC延迟，内联机的制程逐渐使用具有低介电常数(例如k＝2.5～3.0)的介电材料，来取代传统的二氧化硅以及氮化硅等材料(k例如为4以上)，例如是以化学气相沉积(chemical vapor deposition，CVD)的方法所形成的掺碳的氧化硅等。
以下以图1a-图1d说明现有的在金属层间介电层形成铜内联机的流程示意图。
请参考图1a，首先，提供一半导体基底101，于半导体基底101上依序形成一停止层102及介电层103；其中，停止层102一般例如是氧化层；介电层103例如是金属层间介电层，材质一般例如是化学气相沉积形成的低介电常数材料，如掺碳的氧化硅或掺氟的氧化硅。
请参考图1b，接着，在介电层103上形成一具有开口的图案化光刻胶层(未显示)，开口会露出介电层103的表面。以图案化光刻胶层为罩幕蚀刻介电层103，以在介电层103形成一开口104，开口104会露出半导体基底101的表面。
请参考图1c，然后，在开口104的表面上顺应性一阻障层105，阻障层105可帮助后续金属的附着并防止其扩散至介电层103中。接下来，以化学气相沉积法(CVD)、物理气相沉积法(PVD)，或电镀沉积法(Electroplating)在阻障层105上形成一金属层106，并使其填满开口104。其中，阻障层105的材质例如是钽(Ta)，氮化钽(TaN)，氮化钨(WN)，或氮化钛(TiN)等；金属层106例如是铜金属层。
请参考图1d，对金属层106及阻障层105进行平坦化步骤，直至露出介电层103的表面为止，并且会留下开口104中的金属层106a，金属层106a即为导通半导体基底101及形成于介电层103上的组件的内联机。其中，平坦化步骤例如是化学机械研磨步骤。
因为金属层106及阻障层105是直接形成在介电层103上，所以在对金属层106及阻障层105进行平坦化步骤时，常会对介电层103的表面造成破坏而形成裂缝107。裂缝107的存在会使介电层103的结构不完整，而降底介电层103的机械强度与电性强度，进而影响介电层103的隔绝能力。并且，由于多重内联机的制程系由镶嵌铜导线的多层介电材料构成，此多层堆栈的结果亦容易导致低介电常数材料的龟裂。
发明内容
有鉴于此，本发明的目的在于提供一种具有保护层的由低介电常数材料所形成的金属层间介电层的方法，能够降低应力(stress)与耐冲击特性，进而防止多层介电材料堆栈产生的龟裂。
根据上述目的，本发明提供一种形成半导体装置的方法，包括下列步骤：提供一半导体基底；于所述半导体基底上形成有一低介电常数介电层；及以含氢元素气体对所述低介电常数介电层表面进行处理以形成一改质表层。
本发明的另一目的在于提供一种半导体装置，其具有利用上述方法所形成的金属层间介电层。
根据上述目的，本发明提供一种半导体装置，包括：一半导体基底，半导体基底上形成有一低介电常数介电层；及一经等离子体处理的改质表层，形成于低介电常数介电层表面上，用以降低低介电常数介电层表面的应力。
本发明再提供一种半导体装置，包含：一介电层于一半导体基底上；一含氢保护层于所述介电层上；以及一导线于所述保护层及所述介电层内。
附图说明
图1a-图1d是显示现有的在金属层间介电层形成铜内联机的流程示意图。
图2a-图2e是显示本发明的在金属层间介电层形成铜内联机的流程示意图的第一实施例。
图3a-图3g是显示本发明的在金属层间介电层形成铜内联机的流程示意图的第二实施例。
图4a-图4c是显示本发明的形成金属层间介电层的流程示意图的一实施例。
符号说明
101～半导体基底；         102～停止层；
103～介电层；104～开口；  105～阻障层；
106、106a～金属层；       107～裂缝；
201～半导体基底；         202～停止层；
203～介电层；             204～保护层；
205～开口；               206～阻障层；
207、207a～金属层；       301～半导体基底；
302～停止层；             303～第一介电层；
304～第一保护层；         305～第二介电层；
306～第二保护层；         307～第一图案化光刻胶层；
308～孔洞；               309～第二图案化光刻胶层；
310～双镶嵌沟槽；         311～阻障层；
312、312a～金属层；       401半导体基底；
402～停止层；             403～复合介电层；
403a～介电层；            403b～改质表层。
具体实施方式
为了让本发明的上述目的、特征、和优点能更明显易懂，下文特举一较佳实施例，并配合所附图式，作详细说明如下：
第一实施例：
请参考图2a，首先，提供一半导体基底201，于半导体基底201上依序形成一停止层202及介电层203。接着，在摄氏300-400度的温度及2-10Torr的压力下，以120-1500W的功率及以1000-3000cc流量的氢气(H2)对介电层203表面进行等离子体辅助化学气相沉积(Plasma enhance chemical vapordeposition，PECVD)处理，以在介电层203的表面上形成一保护层204，保护层204例如是掺甲烷氧化硅(SiOCH)层。以氢气进行处理的步骤，可在多腔处理室(cluster chamber)中进行，可不破真空，接续在先前的形成步骤后处理；但亦可在一般处理室中进行。其中，停止层202一般例如是氧化层；介电层203是作为金属层间介电层之用，材质例如是掺碳氧化硅(SiOC)所制成的低介电常数材料层，材料系数约在2.3-2.6之间。金属层间介电层的材料亦可以是其它利用化学气相沉积的方法所形成的低介电常数介电层，例如是掺碳氧化硅(SiOC)层或掺氟氧化硅(SiOF)层等。
请参考图2b，接着，在保护层204上形成一具有开口的图案化光刻胶层(未显示)，开口会露出保护层204的表面。以图案化光刻胶层为罩幕依序蚀刻保护层204及介电层203，以在介电层203形成一开口205，开口205会露出半导体基底201的表面。
请参考图2c，然后，在开口205的表面上顺应性一阻障层206，阻障层206可帮助后续金属的附着并防止其扩散至介电层203中。接下来，以化学气相沉积法(CVD)、物理气相沉积法(PVD)，或电镀沉积法(Electroplating)在阻障层206上形成一金属层207，并使其填满开口205。其中，阻障层205的材质例如是钽(Ta)，氮化钽(TaN)，氮化钨(WN)，或氮化钛(TiN)等；金属层207例如是铜金属层。
请参考图2d，对金属层207及阻障层206进行平坦化步骤，直至露出保护层204的表面为止，并且会留下开口204中的金属层207a，金属层207a即为导通半导体基底201及形成于介电层203上的组件的内联机。其中，平坦化步骤例如是化学机械研磨步骤。
因为介电层203上形成有保护层204，因此在对金属层207及阻障层206进行平坦化步骤时，不会对介电层203的表面造成破坏而形成裂缝，可提高介电层203的机械强度与电性强度，进而增加介电层203的隔绝能力。同时，亦可减少多重内联机的多层堆栈而容易导致低介电常数材料的龟裂的问题。
第二实施例：
请参考图3a，首先，提供一半导体基底301，于半导体基底301上依序形成一停止层302及第一介电层303。接着，在摄氏100-350度的温度及2-8Torr的压力下，以100-1500W的功率及以1000-3000cc流量的氢气(H2)对第一介电层303表面进行PECVD处理，以在第一介电层303的表面上形成一第一保护层304，其中，第一保护层304例如是掺甲烷氧化硅(SiOCH)层。以氢气进行处理的步骤，可在多腔处理室(cluster chamber)中进行，可不破真空，接续在先前的形成步骤后处理；但亦可在一般处理室中进行。其中，停止层302一般例如是氧化层；第一介电层303是作为金属层间介电层之用，材质例如是掺碳氧化硅(SiOC)所制成的低介电常数材料层，材料系数约在2.3-2.6之间。金属层间介电层的材料亦可以是其它利用化学气相沉积的方法所形成的低介电常数介电层，例如是掺碳氧化硅(SiOC)层或掺氟氧化硅(SiOF)层等。
请参考图3b，接着，在第一保护层304上形成一第二介电层305，并且同样在摄氏100-350度的温度及2-8Torr的压力下，以流量为1000-3000cc的氢气(H2)对第二介电层305表面进行PECVD处理，以在第二介电层305的表面上形成一第二保护层306，第二保护层306例如是掺甲烷氧化硅(SiOCH)层。以氢气进行处理的步骤，可在多腔处理室(cluster chamber)中进行，可不破真空，接续在先前的形成步骤后处理；但亦可在一般处理室中进行。第二介电层305同样是作为金属层间介电层之用，材质例如是低介电常数材料层，材料系数约在2.3-2.6之间。金属层间介电层的材料亦可以是氧化硅、氮化硅、氮氧化硅、硅玻璃等；形成的方法例如是化学气相沉积、高密度等离子体沉积或旋转涂布式等。
请参考图3c，在第二保护层306上形成一具有第一开口(未标示)的第一图案化光刻胶层307。第一开口会露出第二保护层306的表面。以第一图案化光刻胶层307为罩幕，依序蚀刻保护层第二保护层306、第二介电层305、第一保护层304及第一介电层303，以形成一会露出半导体基底301的表面的孔洞308。因为保护层与介电层的材质不同的缘故，所以两者被蚀刻速的速度不同相同。接着，去除第一图案化光刻胶层307后，继续在第二保护层306上形成一第二图案化光刻胶层309，第二图案化光刻胶层309亦具有一第二开口(未标示)，第二开口会露出第二保护层306的表面及孔洞308，如图3d所示。
请参考图3e，接着，以第二图案化光刻胶层309为罩幕，依序蚀刻第二保护层306及第二介电层305以形成一凹槽(未标示)，凹槽与孔洞308即共同形成一双镶嵌沟槽310；接下来，在第二保护层306表面及双镶嵌沟槽310的表面上顺应性形成一阻障层311，阻障层311可帮助后续金属的附着并防止其扩散至第二介电层305及第一介电层303中。当第二介电层305被蚀刻完毕而开始蚀刻第一保护层304时，因为蚀刻速度不同的缘故，所以可以在开始蚀刻第一保护层304时即被察觉而停止蚀刻，因此，第一保护层304亦具有作为蚀刻停止层的功用。其中，阻障层311的材质例如是钽(Ta)，氮化钽(TaN)，氮化钨(WN)，或氮化钛(TiN)等。
请参考图3f，以化学气相沉积法(CVD)、物理气相沉积法(PVD)，或电镀沉积法(Electroplating)在阻障层311上形成一金属层312，并使其填满双镶嵌沟槽310。其中，金属层312例如是铜金属层。
请参考图3g，对金属层312及阻障层311进行平坦化步骤，直至露出第二保护层306的表面为止，并且会留下双镶嵌沟槽310中的金属层312a，金属层312a即为导通半导体基底及形成于介电层上的组件的内联机。其中，平坦化步骤例如是化学机械研磨步骤。
因为第二介电层305上形成有第二保护层306，因此在对金属层312及阻障层311进行平坦化步骤时，不会对第二介电层305的表面造成破坏而形成裂缝，可提高第二介电层305的机械强度与电性强度，进而增加第二介电层305的隔绝能力。同时，亦可减少多重内联机的多层堆栈而容易导致低介电常数材料的龟裂的问题。
第三实施例：
请参考图4a，首先，提供一半导体基底401，于半导体基底401上依序形成一停止层402及介电层403a。接着，在摄氏100-400度的温度及2-10Torr的压力下，以流量为1000-3000cc的氢气(H2)对介电层403a表面进行PECVD处理，以在介电层403a的表面上形成一改质表层403b，如图4b所示。以氢气进行处理的步骤，可在多腔处理室(cluster chamber)中进行，可不破真空，接续在先前的形成步骤后处理；但亦可在一般处理室中进行。其中，停止层402一般例如是氧化层；介电层403a是作为金属层间介电层之用，材质例如是掺碳氧化硅(SiOC)所制成的低介电常数材料层，材料系数约在2.3-2.6之间。金属层间介电层的材料亦可以是其它利用化学气相沉积的方法所形成的低介电常数介电层，例如是掺碳氧化硅(SiOC)层或掺氟氧化硅(SiOF)层等。
请参考图4c，接着，重复进行形成介电层403a及改质表层403b的步骤，以形成具有多层介电层403a及改质表层403b的复合介电层403；其中，形成于最顶层的改质表层403b具有保护层的作用；并且这样在不同深度具有改质表层403b的复合介电层403具有良好的薄膜特性(film properties)。
利用本发明所提供的形成半导体装置的方法，具有下列优点：(一)有效使利用化学气相沉积方法形成的作为金属层间介电层的低介电常数介电层具有良好的机械特性，如硬度较高、杨氏系数(Young’s modulus)较高等；(二)具有良好的电性特性，如崩溃电压(breakdown)较大等；(三)可使抗反射层的厚度可以降低；(四)封装程序较容易进行；(五)可缩短整个制程所花费的时间。
虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明，任何熟习此技艺者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视所附的权利要求范围所界定者为准。

Claims (24)

1.一种形成半导体装置的方法，包括下列步骤：
提供一半导体基底；
于所述半导体基底上形成有一低介电常数介电层；及
以含氢元素气体对所述低介电常数介电层表面进行处理以形成一改质表层。
2.如权利要求1所述的形成半导体装置的方法，其中所述低介电常数介电层以化学气相沉积法形成。
3.如权利要求1所述的形成半导体装置的方法，其中所述低介电常数介电层为掺碳氧化硅层。
4.如权利要求1所述的形成半导体装置的方法，其中所述低介电常数介电层的介电常数为2.3-2.6之间。
5.如权利要求1所述的形成半导体装置的方法，其中所述含氢气体的流量为1000-3000cc。
6.如权利要求1所述的形成半导体装置的方法，其中所述含氢气体的条件为在摄氏100-400的温度、2-10Torr的压力下、功率为100-1500w下进行。
7.如权利要求1所述的形成半导体装置的方法，其中对所述低介电常数介电层表面进行的处理为等离子体处理。
8.如权利要求1所述的形成半导体装置的方法，其中所述改质表层为掺甲烷氧化硅层。
9.一种半导体装置，其特征在于，包括：
一半导体基底，所述半导体基底上形成有一低介电常数介电层；及
一经等离子体处理的改质表层，形成于所述低介电常数介电层表面上，用以降低所述低介电常数介电层表面的应力。
10.如权利要求9所述的半导体装置，其特征在于，所述低介电常数介电层以化学气相沉积法形成。
11.如权利要求9所述的半导体装置，其特征在于，所述低介电常数介电层为掺碳氧化硅层。
12.如权利要求9所述的半导体装置，其特征在于，所述低介电常数介电层的介电常数为2.3-2.6之间。
13.如权利要求9所述的半导体装置，其特征在于，所述经等离子体处理改质表层以含氢元素气体进行等离子体处理而得。
14.如权利要求13所述的半导体装置，其特征在于，所述含氢元素气体的流量为1000-3000cc。
15.如权利要求13所述的半导体装置，其特征在于，所述等离子体处理在摄氏100-400的温度、2-10Torr的压力、功率为100-1500w下进行。
16.如权利要求9所述的半导体装置，其特征在于，所述改质表层为含氢材料层。
17.如权利要求9所述的半导体装置，其特征在于，所述低介电常数介电层为掺碳氧化硅层或掺氟氧化硅层。
18.如权利要求9所述的半导体装置，其特征在于，所述改质表层为掺甲烷氧化硅层。
19.一种半导体装置，其特征在于，包括：
一介电层于一半导体基底上；
一含氢保护层于所述介电层上；以及
一导线于所述保护层及所述介电层内。
20.如权利要求19所述的半导体装置，其特征在于，又包括一蚀刻停止层于所述介电层下。
21.如权利要求19所述的半导体装置，其特征在于，所述导线为铜。
22.如权利要求19所述的半导体装置，其特征在于，所述介电层为低介电常数介电层。
23.如权利要求19所述的半导体装置，其特征在于，所述含氢保护层为掺甲烷氧化硅层。
24.如权利要求19所述的半导体装置，其特征在于，所述介电层的介电常数为2.3-2.6之间。
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