CN1604300A - Optimal Design Method of PN Junction Substrate Isolation Chip Inductor - Google Patents

Abstract

This invention relates to micro electronics technique field and in detail to a method to design the multiple PN joints underlay isolation pad inductance by use of standard CMOS process, which comprises the following steps: to inject impurity with reverse polarity to the trap ions in single trap process; to spread the impurity against top trap to form a PN joint and three serial PN joints vertical to the silicon pad; to control inductance register capacitor through adjusting the single or multiple PN joints isolation layer anti-bias voltage ; to adjust resonance frequency to make the inductance work in self-triggering oscillation frequency.

Description

Optimal Design Method of PN Junction Substrate Isolation Chip Inductor

technical field

The invention belongs to the technical field of microelectronics, and specifically relates to a method for designing a multi-PN junction substrate isolation layer laid under an on-chip inductor by using a standard CMOS process, and a corresponding method for optimizing the inductor.

Background technique

With the rapid development of semiconductor technology, monolithic integrated circuits have become possible. Due to the inherent low power consumption, high performance, low cost, and high yield of monolithic integrated circuits, the on-chip implementation of the original off-chip components, such as inductors, has become a research hotspot. Inductors are a key component of radio frequency communications and are widely used in circuits such as amplifiers, mixers, oscillators, and power amplifiers. The rapid development of mobile communication has also greatly promoted the research of on-chip inductors. The characteristics of low power consumption in mobile communication require tuning circuits of inductors to achieve low power supply voltage and low power consumption, making inductors play an irreplaceable role.

The low cost, high yield of silicon-based integrated circuits, and the potential monolithic integration of digital and analog circuits are favored by the consumer electronics market. However, due to the relatively low impedance of the semiconductor silicon substrate, the inductor generates mirror current and eddy current on the substrate through the electric field and magnetic field respectively, reducing the Q value of the inductor, and the current crowding effect of the metal lines that make the on-chip inductor (skin effect and proximity) Effect) will increase the ohmic loss of the inductor itself, making it difficult for the Q value of conventional inductors to be greater than 10 in the range of several GHz, which limits the on-chip application of integrated inductors.

Figure 1 shows the standard CMOS hierarchical relationship of metal interconnection wire inductors. Due to the limited number of layers of metal interconnection wires, the distance between the top layer metal and the bottom metal layer is relatively close, and the current crowding effect is obvious; the short distance between the reverse current inductor coils makes the lateral inductance The static mutual inductance is relatively small; there are more through holes, and the parasitic series DC resistance of the inductor is relatively large, so that the Q of the inductor will not be high, so the inductor is planar or vertically connected. But at this time, the electromagnetic field of the inductor passes through the semiconductor substrate longitudinally, and the alternating magnetic field will inevitably generate eddy currents in the semiconductor substrate. When the eddy currents flow in the conductor, the Lenz-Joule heat will be generated due to the resistance of the conductor. In the form of loss of part of the electromagnetic energy, the Q value is reduced.

To this end, design engineers have proposed solutions from the perspectives of reducing substrate loss and ohmic loss of resistors and reducing the parasitic capacitance of inductors to increase their self-excited oscillation frequency, such as: paralleling multi-layer metals to reduce ohmic losses of inductors; The increase of the inductance in the form of the inner stack series is greater than the increase of the resistance to reduce the parasitic capacitance of the inductance; the line width of the inner ring inductance is reduced, and the coupling coefficient is increased to reduce the influence of the proximity effect; grounding through various film layers and virtual grounding The method of isolating the loss of the image current generated by the electric field of the substrate; the substrate resistance is increased through the PN junction depletion layer, and the substrate loss is reduced; the self-excited oscillation frequency f _self and Q value of the circuit are improved by using a differential drive method; in addition , some methods of improving the Q value of inductors in non-standard processes (such as hollowing out the substrate under the inductor, etc.), are not advocated here because of increased costs.

Process manufacturers also adjusted the process accordingly in order to improve the Q value of the on-chip inductor. This is the so-called silicon-based RF process. The resistivity of the substrate has been improved to a certain extent (generally 10Ω cm) to reduce substrate loss. The thickness of the top layer metal is increased to reduce the ohmic loss of the inductor. General process libraries provide several values of inductance, but for circuit design, the inductance value and Q value are often not optimal. For circuit designers, it is necessary to design the inductance value required by the circuit and the inductance with the maximum Q value at the operating frequency without changing the process based on the technical means provided by the standard CMOS process.

To reduce the substrate loss and improve the Q value of the inductor, we can start from two perspectives: (1) reduce the substrate coupling capacitance of the inductor, thereby reducing the loss of the mirror current induced by the electric field of the inductor substrate, and at the same time increase the self-excited oscillation frequency of the inductor ; (2) Increase the impedance of the substrate and reduce the eddy current loss of the inductive magnetic field on the substrate.

The substrate capacitance of the inductor is equivalent to the series connection of the oxide layer capacitance C _ox between the inductor and the substrate and the equivalent substrate capacitance C _sub . Lay a PN junction under the inductor, such as forming an N well on a P substrate, which will form a PN junction capacitance C _pn and a high-resistance depletion layer. The equivalent capacitance of the inductor is the series connection of C _ox , C _pn and C _sub . This reduces the equivalent capacitance of the substrate. However, since the PN junction is formed below it is the active region, which means that the thickness of the oxide layer between the inductor and the substrate is thinner than when nothing is laid, which means that the capacitance C _ox after laying a single-layer PN junction will increase, thereby reducing The effect of single-layer PN junction substrate isolation on reducing the parasitic capacitance of the inductor. And the previous practice is that the single-layer PN junction is a whole or simple parallel lines. Since the eddy current direction of the substrate is along the line direction of the inductor, such a structure is not sufficient to prevent the eddy current of the substrate, and since the resistance of the N well is lower than the resistance of the inductor substrate, an effective eddy current will be formed in the N well , increasing the loss of the inductance.

Standard CMOS on-chip inductors are wound with multiple layers of metal interconnects. The research of the inductor mainly focuses on improving the quality factor (Q) and the self-excited oscillation frequency (f _SR ) of the inductor and the establishment of the model.

The basic definition of the quality factor of an inductor is the ratio of stored energy to lost energy in a cycle:

The broadest definition of Q is:

${\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&omega;</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; Im</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; y</span>}\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; Re</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; y</span>}\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&omega;</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; E.</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}^{\mathrm{<span\; class="notranslate">\; av</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; E.</span>}}_{\mathrm{<span\; class="notranslate">\; e</span>}}^{\mathrm{<span\; class="notranslate">\; av</span>}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; l</span>}}^{\mathrm{<span\; class="notranslate">\; av</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

Among them, E _m ^av , E _e ^av , P _l ^av respectively represent the average stored magnetic energy, electric energy and loss of the inductor in one cycle. The self-excited oscillation frequency (f _SR ) of an inductor is defined as the operating frequency of the inductor when Q is 0 in formula (2):

${\mathrm{<span\; class="notranslate">\; f</span>}}_{\mathrm{<span\; class="notranslate">\; SR</span>}}<span\; class="notranslate">\; =</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&pi;</span>}\sqrt{{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; eq</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; eq</span>}}}<span\; class="notranslate">\; )</span>}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Among them, L _eq and C _eq are equivalent inductance value and capacitance value respectively.

Contents of the invention

The purpose of the present invention is to propose a method for designing multi-PN junction substrate isolation on-chip inductance with standard CMOS technology.

The method that the present invention proposes to design multi-PN junction isolation chip inductance with standard CMOS process, at first utilize the double well or single well process of standard complementary metal oxide semiconductor process (i.e. standard CMOS process) to form stacked three or double PN junction substrate isolation structure, thereby effectively reducing the substrate equivalent capacitance of the inductor, thereby increasing the self-excited oscillation frequency of the inductor, and reducing the mirror current loss of the inductor; the interlaced PN junction depletion layer structure plays a role in the resistance of the eddy current The effect is to reduce the eddy current loss of the inductor substrate, thereby increasing the Q value of the inductor.

The steps to design the PN junction substrate isolation layer of the on-chip inductor using the standard CMOS process are as follows:

(1) For the single well process, impurity with opposite polarity to the well ions is implanted on the well, specifically for the P-type substrate, an N well is formed on the P-type substrate, and then P ⁺ diffusion is performed on the N well; For an N-type substrate, a P well is formed on the N-type substrate, and then N ⁺ is diffused on the P well to form a double PN junction perpendicular to the silicon wafer.

For the deep well process, a well of the opposite type to the deep well ion is formed on the deep well, such as forming a deep N well on a P-type substrate, and then forming a P well on the deep N well, which will also form a vertical direction to the silicon wafer. Double PN junction;

(2) On the basis of the formation of the double PN junction, the impurity opposite to its ion is diffused on the top well to form another PN junction, thus forming a triple-layer PN junction. For example, a deep N well is formed on a P-type substrate, a P well is formed on the deep N well, and N ⁺ is diffused on the P well. In this way, a vertically connected triple sum PN junction is formed.

The equivalent parasitic capacitance of the substrate of the inductor is equal to the series connection of multiple PN junction capacitances and the oxide layer capacitances C _ox and C _sub in series, which further reduces the substrate capacitance of the inductor and the capacitive coupling substrate loss.

In the present invention, the horizontal direction of the structure of multiple PN junctions is not designed to be a complete plane, but a structure that is separated or integrally connected and partially separated. Specifically, the stacked PN junctions can be designed in a line shape and perpendicular to the inductance The metal coil is discharged in a radial shape, similar to the form of a metal ground shield. But here it is not used for ground shielding, but to reduce the loss of eddy current when the depletion layer of the PN junction and the resistance of the insulating layer between the PN junction value the movement of the eddy current on the surface of the substrate. Using a separated PN junction makes the thickness (THR) of the high resistance region of the substrate no longer the thickness of the depletion layer of the PN junction, but the depth from the PN junction formed by the lowest layer well to the oxide layer.

Utilize the method that the present invention proposes to make radial PN junction substrate isolation chip inductance with standard CMOS technology, utilize the double well of standard CMOS technology or single well technology to design three or double PN junction substrate isolation structure, without increasing cost Effectively reduce the substrate equivalent capacitance of the inductor under the premise, thereby increasing the self-excited oscillation frequency of the inductor and reducing the mirror current loss of the inductor; the interleaved PN junction depletion layer structure plays a role in the resistance of the eddy current, reducing the inductor substrate The eddy current loss increases the Q value of the inductor.

Design of PN junction isolation inductor working at self-oscillation frequency:

The previous design of inductance is to increase the self-excited oscillation frequency of the inductance as much as possible, but the present invention makes the inductance work at the self-excited oscillation frequency, which means that a large inductance value and a large parasitic capacitance are required, which can be achieved by increasing the width of the metal coil and The parasitic resistance of the inductor can be reduced by connecting multi-layer metal interconnection lines in parallel; the inductance value can be increased by using stacked series structure and multi-turn inductor, and the self-excited oscillation frequency of the inductor can be reduced to the working frequency.

An increase in the ratio of the inductance value to the parasitic resistance connected in series means that the stored energy increases and the energy loss decreases, thereby increasing the quality factor of the inductance and improving the performance of the circuit accordingly.

Adjusting the reverse bias voltage of the single or multiple PN junction substrate isolation layer laid under the on-chip inductor can adjust the PN junction capacitance, and then control the parasitic capacitance of the inductor, while the inductance value is basically unchanged, and the change of the parasitic capacitance means that the self- The oscillation frequency changes. That is to say, by adjusting the PN junction reverse bias voltage of the substrate isolation layer, the self-excited oscillation frequency of the inductor can be adjusted to make it equal to the operating frequency of the inductor, so as to eliminate the influence of process deviation and design deviation, and at the same time achieve a certain range of frequency tuning.

The self-oscillating inductor replaces the traditional inductor-capacitor parallel resonance circuit topology, such as LC VCO.

Description of drawings

Figure 1 shows the standard CMOS hierarchical relationship of four-layer metal interconnection lines;

Figure 2 is a vertical PN junction series structure of a single well process;

Figure 3 is a vertical PN junction series structure of a double well process;

Figure 4 is a schematic diagram of a double PN junction radial substrate isolation structure

In the figure: 21 is the substrate, 22 is the depletion layer of the PN junction, 23 is the ion diffusion or ion implantation, 24 is the depletion layer of the PN junction, 25 is the diffusion or implantation of ions, 26 is the capacitor, and 27 is the PN junction , 28 is the PN junction, 29 is the depth of the depletion layer, 31 is the substrate, 33 is the deep well, 32, 34, 38 are the depletion layers of the PN junction, 35 is the deep well, 36 is the capacitor, 37 is the ion implantation, 39, 310, 311 are three PN junctions connected in series, 312 is the thickness of the high resistance layer; 41 is the N well, 42 is the P ⁺ , and 43 is the gap.

Detailed ways

The present invention is further specifically described below in conjunction with the accompanying drawings.

Figure 1 shows the standard CMOS hierarchical relationship of four-layer metal interconnection lines; the inductance is formed by winding interconnection lines, and the connections between different layers are connected by through holes. The PN junction is completed by ion implantation of the active layer.

Fig. 2 is a vertical PN junction series structure of a single well process. 21 is a substrate, and 23 is ion diffusion or implantation opposite to the substrate to form a well, so that a PN junction 27 is formed between 21 and 23 . Ions 25 of opposite polarity are diffused or implanted on 23 , so that a PN junction 28 is formed between 25 and 23 . 22 and 24 in the figure are the depletion layers of the PN junction, and there is no free mobile charge, so the high-resistance depth formed by the PN junction is no longer the depletion layer of the simple PN junction, but the depth of the lowest depletion layer 29 . The two PN junctions are connected in series with the oxide capacitor 26 in the direction perpendicular to the substrate. In this way, the parasitic capacitance of the inductor is greatly reduced. For example, the N well is diffused on the P-type substrate, and P ⁺ implantation is performed on the N well, so that two series-connected PN junctions (P ⁺ NP) are formed between the P ⁺ and N well and between the N well and the P substrate.

FIG. 3 is a vertical PN junction series structure of a double well process. Among them, 31 is the substrate, 33 is a deep well with opposite polarity to the substrate, and 35 is a well formed by particles with opposite polarity to the deep well, and a series connection of double PN junctions is formed between 31 and 33, 33 and 35 .

Ions 37 of opposite polarity to the trap ions are implanted on the trap. In this way, three series-connected PNs are respectively formed between 31 and 33, 33 and 35, and 35 and 37: 39, 310, 311, the PN junction and the oxide layer capacitor 36 are connected in series. 32, 34, 38 are the depletion layers of the PN junction, and 312 is the thickness of the equivalent high resistance layer of the PN junction.

For example, a deep N well is formed on the P substrate, and a P well is formed on the deep N well, so that two series PN junctions (PNP) are formed between the P well and the deep N well and between the deep N well and the P substrate. . N ⁺ is diffused on the P well, so that the PN junction formed between N ⁺ and the P well is connected in series with the two capacitors formed earlier to form a three-PN junction (NPNP) in series.

In this way, the equivalent parasitic capacitance of the substrate of the inductor is equal to the series connection of multiple PN junction capacitances connected in series with C _ox and C _sub , which further reduces the substrate capacitance of the inductor and the capacitive coupling substrate loss.

The series connection of the PN junction and the capacitance of the oxide layer under the metal is connected in series, that is to say, the capacitance between the inductance and the substrate is in series relationship, and the overall equivalent capacitance of the inductance is greatly reduced, and the capacitive coupling substrate loss is also reduced. . The reduction of the equivalent parasitic capacitance of the inductor substrate can effectively improve the self-excited oscillation frequency of the inductor.

FIG. 4 is a schematic diagram of a radial substrate isolation structure of a double PN junction; wherein 41 and 42 have opposite polarities of particles, and 43 is a gap where no additional ions are implanted. For example, the N well is diffused on the P substrate, and P ⁺ is implanted on the N well to form a vertical series double PN junction. Such a PN junction line is perpendicular to the coil of the inductor, and the equivalent high-resistance thickness is the depth from the lowest layer of the PN junction to the oxide layer, and the depletion layer of the PN junction can resist the flow of eddy current on the surface of the substrate. Reduce the substrate loss of the inductor and improve the quality factor of the inductor.

The formula for the parasitic capacitance of the PN junction is

${\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; =</span>\sqrt{\frac{\mathrm{<span\; class="notranslate">\; q</span>}{\mathrm{<span\; class="notranslate">\; \&epsiv;</span>}}_{\mathrm{<span\; class="notranslate">\; the\; si</span>}}{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; A</span>}}{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&Phi;</span>}}_{\mathrm{<span\; class="notranslate">\; bi</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; A</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}}<span\; class="notranslate">\; )</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\sqrt{\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; \&Phi;</span>}}_{\mathrm{<span\; class="notranslate">\; bi</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; R</span>}}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

Among them, N _A and N _D are the ion concentrations of the two ion regions of the PN junction; q is the electric quantity of the charge; Φ _bi is the built-in potential of the PN junction; _VR is the reverse bias voltage of the PN junction.

When the reverse bias voltage _VR is added to the PN junction, the equivalent parasitic capacitance between the inductor and the substrate will be further reduced by the following formula (1). Note that when biasing, the connection between the voltage and the level of the PN junction should be connected to a larger resistor, such as several thousand ohms. In this way, a certain level of the PN junction is not a ground shielding structure, but plays the role of reducing the parasitic capacitance of the PN inductance substrate and isolating the substrate. In this way, by adjusting the reverse bias voltage of the PN junction, the capacitance of the PN junction changes, which means that the self-excited oscillation frequency of the inductor changes.

The inductor works at the self-excited oscillation frequency, which means that a large inductance value and a large parasitic capacitance are required, so that the parasitic resistance of the inductor can be reduced by increasing the width of the metal coil and connecting multi-layer metal interconnection lines in parallel; the stacked series structure is adopted And methods such as multi-turn inductors increase the inductance value and reduce the self-excited oscillation of the inductor to the operating frequency.

Due to the deviation of the process, it is difficult for such a self-excited oscillation frequency to accurately align with the operating frequency of the circuit. Adjusting the reverse bias voltage of the PN junction and controlling the parasitic capacitance of the inductor, that is, the capacitance of the LC resonant circuit, can control the resonant frequency. In turn, the effect of precise alignment and tuning of the resonant frequency is achieved.

In addition, it should be noted that the depletion layer of the PN junction has no free mobile charges, and it can also be said that the resistance here is infinite, preventing the flow of eddy currents in this layer. The depletion layer of the actual PN junction is very thin, and the reverse PN junction pressure can increase the thickness W _di of the depletion layer,

${\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; di</span>}}<span\; class="notranslate">\; =</span>\sqrt{\frac{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&epsiv;</span>}}_{\mathrm{<span\; class="notranslate">\; the\; si</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; A</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; q</span>}{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; A</span>}}{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}}}}<span\; class="notranslate">\; \&CenterDot;</span>\sqrt{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; R</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; bi</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

Among them, N _A , N _D are the ion concentrations of the two ion regions of the PN junction; q is the amount of charge; Φ _bi is the built-in potential of the PN junction; _VR is the reverse bias voltage of the PN junction; ε _si is the substrate of the dielectric field number.

Using a separated PN junction makes the thickness of the high resistance region (THR) of the substrate no longer the thickness of the depletion layer of the PN junction, but the depth of the PN junction formed by the bottom well and the substrate. The PN depletion layer increases with the increase of the reverse PN junction voltage, which means that the ability of the PN junction to resist the eddy current of the substrate is improved, and the Q value of the inductor is further improved.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention without limitation. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be The schemes are modified or equivalently replaced without departing from the spirit and scope of the technical schemes of the present invention, and all of them shall be covered by the scope of the claims of the present invention.

Claims (4)

1, a kind of method with standard CMOS technology design many PN junction substrate isolation on-chip inductances, it is characterized in that at first utilizing the single well of CMOS technology or double well technology to form stacked three or double PN junction substrate isolation structure; Wherein (1) For the single well process, impurity with opposite polarity to the well ions is implanted on the well to form a double PN junction perpendicular to the silicon wafer; For the deep well process, a well of the opposite type to the deep well ion is formed on the deep well to form a PN junction perpendicular to the silicon wafer; (2) On the basis of the formation of the double PN junction, the impurity opposite to its ion is diffused on the top well to form another PN junction; thereby forming a triple-layer PN junction. 2. The design method according to claim 1, characterized in that: the horizontal direction of the multi-PN junction structure is a structure that is separated or integrally connected and partially separated, and the stacked PN junctions are designed in a line shape, and vertical Discharge from the metal coil of the inductor, showing a radial shape; 3. The design method according to claim 2, wherein the self-excited oscillation frequency of the inductor is made to be the working frequency of the inductor. 4. The design method according to claim 3, characterized in that the reverse bias voltage of the single or multiple PN junction substrate isolation layer laid under the on-chip inductor is adjusted, the parasitic capacitance of the inductor is controlled, and then the self-excited oscillation frequency of the inductor is adjusted to the operating frequency of the inductor.

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