CN1665018A - A Small-area, High-Performance Stacked Structure Differential Inductor - Google Patents

Abstract

The invention belongs to the field of micro electronic technique, concretely relating to a high performance stacked differential symmetrical inductance designed by standard IC process piece. The invention implements the single-circle series connection between different metallic interconnected coils and keeps the symmetry of two signal ports of the inductance, and implements high performance small-area differential inductance. The inductance of the invention can implement a large inductance by a small area. The parasitic capacitors between the stacked coils are connected in series and the AC voltage of the lowest layer is the lowest and has the smallest voltage difference from the substrate, meaning the further reduction of the parasitic capacitance of the inductance.

Description

A Small-area, High-Performance Stacked Structure Differential Inductor

technical field

The invention belongs to the technical field of microelectronics, and specifically relates to a small-area high-performance on-chip lamination structure differentially driven symmetrical inductor designed by standard integrated circuit technology.

Background technique

With the rapid development of semiconductor technology, monolithic integrated circuits have become possible. Due to a series of advantages inherent in monolithic integrated circuits, such as low power consumption, high performance, low cost, and high yield, the on-chip implementation of the original off-chip components (such as inductors, etc.) has become a research hotspot.

On-chip inductors in standard integrated circuits are wound using multiple layers of metal interconnection wires. The research of the inductor mainly focuses on improving the quality factor (Q) and the self-excited oscillation frequency (f _sR ) of the inductor and the establishment of the model.

The basic definition of the quality factor of an inductor is the ratio of stored energy to lost energy in a cycle:

The broadest definition of Q is:

${\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&omega;</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; Im</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; y</span>}\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; Re</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; y</span>}\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&omega;</span>}<span\; class="notranslate">\; \&CenterDot;</span>\frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; E.</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}^{\mathrm{<span\; class="notranslate">\; av</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; E.</span>}}_{\mathrm{<span\; class="notranslate">\; e</span>}}^{\mathrm{<span\; class="notranslate">\; av</span>}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; l</span>}}^{\mathrm{<span\; class="notranslate">\; av</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

Among them, E _m ^av , E _e ^av , P _l ^av respectively represent the average stored magnetic energy, electric energy and loss of the inductor in one cycle. The self-excited oscillation frequency (f _SR ) of the inductor is defined as the second definition of the inductor Q, where Q is the operating frequency of the inductor:

${\mathrm{<span\; class="notranslate">\; f</span>}}_{\mathrm{<span\; class="notranslate">\; SR</span>}}<span\; class="notranslate">\; =</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&pi;</span>}\sqrt{{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; eq</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; eq</span>}}}<span\; class="notranslate">\; )</span>}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Among them, L _eq and C _eq are equivalent inductance value and capacitance value respectively.

It can be seen from (2) and (3) that as long as the parasitic capacitance of the inductor is reduced, the Q and f _SR of the inductor can be improved.

With the continuous progress of the technology, the size of the components is reduced in proportion. However, the area of the inductor is too large to be reduced in proportion, and the performance is not very good. One of the main reasons is that the coupling coefficient between different coils of the planar inductor is very low, which means that the loss caused by magnetic field energy storage and series resistance decreases as the number of inductor turns increases. However, in order to achieve a relatively large inductance while saving a certain area, people have to adopt a multi-turn inductance form instead of a single-turn large-radius structure.

With the progress of the technology, the number of layers of the interconnection lines gradually increases, and the through holes connecting different metal layers also use the same metal as the interconnection lines, which reduces the resistance of the through holes. For this reason, a laminated inductor is designed, that is, the inductors between different layers are connected in series, but such structures are all single-ended, that is, one port of the inductor is grounded for the AC signal, and the other end is connected to the AC signal. It is not suitable for the needs of differential circuits, and two single-ended inductors have to be used, which causes a waste of chip area. For the design of RF integrated circuits, in order to suppress DC offset and signal isolation, differential circuit topology is generally used. People have come up with a method of combining two differential inductors, and designed a differential inductor using multi-layer metal interconnection lines, which is the two inductors. The signals input by each port are equal in magnitude and opposite in magnitude, and the inductance is centrosymmetric. The geometric center of the inductance coil is a virtual ground, so the differential inductance is a patchwork of two independent single-ended inductances, which saves area and reduces Inductor to substrate parasitic capacitance. The capacitance of the planar differential inductor in differential use is a quarter of that of the inductor in single-ended use.

P _lav ^includes substrate loss and metal series loss of the inductor. The substrate loss includes substrate eddy current loss and substrate electric field coupling loss. In a small-radius inductor, the penetration depth of the substrate is relatively shallow compared to a large-radius inductor, which means that the losses in the substrate are also low. However, with the use of laminated inductors, since the coupling coefficient is relatively large, the radius of the inductor is relatively small, and the corresponding substrate loss is also low. But the differential inductance of the stack has not been reported yet.

Contents of the invention

The object of the present invention is to propose a high-performance on-chip lamination structure differentially driven symmetrical inductor designed by standard integrated circuit technology.

The high-performance inductance designed by the standard integrated circuit technology proposed by the present invention adopts a laminated differential drive symmetrical structure, wherein a single-turn inductance structure is adopted in the same metal interconnection layer, and a series connection form is adopted between different layers.

In the present invention, the connection between the upper and lower layers adopts a Z-shaped groove, and the width of the groove meets the requirements of the design rules. The two horizontal lines of the Z are basically perpendicular to the edge of the coil; the slash of the Z is basically parallel to the edge of the coil, and is located at the center of the width of the coil. The slotting directions of the Z-shaped horizontal bars on the upper and lower interconnection layers are opposite to ensure the consistency of the current direction of different inductance coils. The Z-shaped part is connected to the upper and lower layers through through holes. The so-called standard integrated circuit process here is a standard CMOS multilayer metal interconnection process.

The laminated inductor improves the performance of the inductor by increasing the coupling coefficient between the inductor coils and increasing the ratio of the inductance value to the series resistance of the metal coil. The coupling coefficient between the vertically stacked inductors connected in series is about 0.9. When the inductance value of each circle is the same, the inductance value is approximately equal to the square of the number of layers (n) of the stacked inductor, and the proximity effect is neglected. Under normal circumstances, the series resistance of the inductor is approximately equal to the sum of the series resistance of each layer of inductor coils, which is proportional to n, that is to say, the inductance value increases by n ² times, while the resistance value increases by n times. This increases the performance of the inductor.

Since the coupling coefficient between adjacent coils of the same layer is small, in the differential structure, the voltage difference between adjacent coils is relatively large, resulting in relatively large parasitic capacitance of the inductor. In the present invention, the inductor adopts a single-turn structure on the same metal layer, and then connects downwards through the through holes between different metal layers until the bottom layer; it can also be connected in parallel between adjacent layers, and then connected with other parallel layers Or a single-layer series connection, which reduces the series parasitic resistance of the single-turn metal; it can also be connected in series by skipping some layers, such as the single-turn inductance of the metal layer 5 is connected in series with the metal layer 3 and the metal layer 1, and the middle Metal layer 2 and metal layer 4 are skipped, thereby increasing the distance between adjacent stacked layers and reducing the parasitic capacitance of adjacent metal coils.

In the stacked structure, the original capacitance between the inductance coil and the substrate becomes a series connection structure of the parasitic capacitance between the inductance coils of different interconnection metal layers and the capacitance between the lowest layer coil and the substrate. Moreover, the central part of the lowest-layer coil is the zero-potential junction of two single-ended inductive alternating currents driven by differential, that is to say, the potential difference between the potential of the lowest-layer inductive coil of this structure and the conventional grounded substrate is the smallest, From the perspective of plate capacitance, it means that the parasitic capacitance between the layer coil and the substrate is very small. Generally speaking, the parasitic capacitance of such an underlying inductance is very small. Compared with planar inductors, under the same inductance value, stacked inductors have a small radius, which means small area and small parasitic capacitance. And this vertical stacked series connection structure reduces the parasitic capacitance between the inductors and between the inductor and the substrate, thereby improving the quality factor and the self-excited oscillation frequency of the inductor.

Description of drawings

Figure 1 shows the standard CMOS hierarchical relationship of four-layer metal interconnection lines;

Figure 2 is the differential inductance of the fourth layer of metal inductance coils connected in series to the first layer of metal inductance coils;

Fig. 3 is the inductance coil of the fourth layer metal of inductance in Fig. 2;

Fig. 4 is the inductance coil of the third layer metal of inductance in Fig. 2;

Fig. 5 is the inductance coil of the inductance second layer metal in Fig. 2;

Fig. 6 is the inductance coil of the first layer metal of the inductance in Fig. 2;

Fig. 7 is the series connection of the inductance coil of the fourth layer metal of the inductance and the inductance coil of the third layer metal in Fig. 2;

Fig. 8 is the series connection of the inductance coil of the third layer of metal and the inductance coil of the second layer of metal in the inductor in Fig. 2;

Fig. 9 is the series connection of the inductance coil of the second layer of metal inductance and the inductance coil of the first layer of metal in Fig. 2;

In the figure: 11 is the substrate layer of the inductor, 12 is the epitaxial layer, 13 is the field oxide layer, 14 is the active area, 15 is polysilicon, 30 is the metal layer ④, 40 is the metal layer ③, 50 is the metal layer ②, 60 is the metal layer ①; 1-8 are dotted lines indicating the direction of the current.

Detailed ways

The present invention is further specifically described below in conjunction with the accompanying drawings.

The monolithic inductor is formed by winding metal interconnection wires. Figure 1 shows the standard CMOS layer relationship of four-layer metal interconnection wires, which are substrate 11, epitaxial layer 12, field oxide layer 13 and organic Source region 14, polysilicon 15, field oxide layer ①, metal layer ①, ... field oxide layer ④ and metal layer ④. Different metal levels can be connected by vias. The following will take this process as an example to introduce the method of designing a single-turn small-area high-performance differential inductor.

Fig. 2 is a block diagram of differential inductance in which the fourth-layer metal inductance coil is connected in series to the first-layer metal inductance coil. The shape and connection relationship of each metal coil will be described in detail below. Fig. 3 is the inductance coil of the fourth layer metal of the inductance in Fig. 2 . Wherein, 30 denotes the fourth-layer metal interconnection wire, 31 is two ports of the differential inductor, and 32 is a zigzag gap of the coil, which divides the fourth-layer metal coil into two parts. Fig. 4 is the inductance coil of the third layer metal of the inductance in Fig. 2 . Wherein 40 represents a third-layer metal interconnection line. 41 and 42 are two inverted Z-shaped gaps that divide the metal coil 3 into two parts. Parts 33 and 34 in FIG. 3 are respectively connected to parts 43 and 44 in FIG. 4 through through holes. Fig. 5 is the inductance coil of the second layer metal of the inductance in Fig. 2 . Wherein 50 represents the second layer metal interconnection line. 51 and 52 are two inverted Z-shaped gaps that divide the metal coil 2 into two parts. Parts 46 and 46 in FIG. 4 are respectively connected to parts 55 and 56 in FIG. 5 through through holes. Fig. 6 is the inductance coil of the first layer metal of the inductance in Fig. 2 . Wherein 60 represents the metal interconnection line of the first layer. 61 is a zigzag slit. Parts 53 and 54 in FIG. 5 are respectively connected to parts 62 and 63 in FIG. 6 through through holes. The two lateral directions of the zigzag gaps in adjacent layers are opposite to ensure the serial connection between the upper and lower layers.

FIG. 7 is a series connection of the inductor coil of the fourth layer metal and the inductor coil of the third layer metal of the inductor in FIG. 2 , where 70 is a through hole connecting the fourth layer metal interconnection line and the third layer metal interconnection line. FIG. 8 is the series connection of the inductor coil of the third layer metal and the inductor coil of the second layer metal of the inductor in FIG. 2 , where 80 is a through hole connecting the third layer metal interconnection line and the second layer metal interconnection line. FIG. 9 is a series connection of the inductance coil of the second-layer metal and the inductance coil of the first-layer metal of the inductor in FIG. 2 , where 90 is a through hole connecting the second-layer metal interconnection line and the first-layer metal interconnection line.

The dotted lines 1-8 with arrows in Figures 3-6 indicate the direction or opposite direction of the current flow. Such a zigzag gap not only ensures the separation of the same layer of coils, but also ensures the serial connection of the upper and lower layers, and the current is in the same direction.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention without limitation. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be Modifications or equivalent replacements of the technical solutions without departing from the spirit and scope of the technical solutions of the present invention shall be covered by the scope of the claims of the present invention.

Claims (2)

1, a kind of small-area high-performance differential inductor with laminated construction with the design of standard integrated circuit technology is characterized in that: the induction structure at same metal interconnecting layer employing individual pen, adopt the polyphone type of attachment between the different layers.

2, inductance according to claim 1 is characterized in that: the zigzag fluting is adopted in bilevel junction, two horizontal basic hanging down as for the edge of coil of Z word; The slash of Z word is basically parallel to the edge of coil, is positioned at the center of coil width; The whippletree of the Z word of two interconnection layers fluting direction is opposite up and down.

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