CN102176453B - Vertical-structure on-chip integrated transformer - Google Patents

Abstract

The invention discloses a vertical-structure on-chip integrated transformer. As the structure of a transformer is made vertical to the horizontal direction of the chip, the occupied chip plane area is greatly reduced, the area of an inductance-covered substrate is reduced, the parasitic capacitance between the transformer and substrate is reduced, the resonance frequency of the transformer is improved, and the structure is suitable for a high-frequency circuit.

Description

A Vertical Structure On-Chip Integrated Transformer

technical field

The invention belongs to the technical field of microelectronics, relates to an on-chip transformer, in particular to a transformer with an integrated spiral structure. the

Background technique

With the maturity of silicon process technology, wireless communication has achieved revolutionary breakthroughs, such as personal communication systems, wireless local area networks, satellite communications, and global positioning systems, which further lead to the manufacture technology and characteristic analysis of radio frequency integrated circuits (RFICs). hotspot. Due to the existence of mutual inductance, the working efficiency of the on-chip helical transformer is higher than that of the on-chip integrated inductor. Therefore, the on-chip helical transformer has been widely used in the design process of radio frequency integrated circuits and analog front-end circuits. For example, impedance transformation, impedance matching, DC isolation, and signal coupling in radio frequency integrated circuits. Over the past decade, a lot of experimental and theoretical work has been done on how to design high-performance helical transformers with high quality factor, high resonant frequency, and minimal chip area. In order to effectively improve the quality factor of the spiral transformer, scholars have proposed many process or shape optimization schemes, such as suspended vertical structure, differential drive mode, using high-resistance silicon as a substrate, and inserting a lattice ground shield (PGS), etc. . Furthermore, the area occupied by the chip is also one of the important factors affecting the performance of the chip. How to increase the resonant frequency of the transformer while reducing the area occupied by the chip is also a problem that designers should pay attention to. the

Contents of the invention

The purpose of the present invention is to reduce the plane area of the chip and at the same time reduce the area of the substrate covered by the inductance, increase the resonant frequency of the transformer, and make it suitable for high-frequency circuits. the

In order to achieve the above object, the present invention adopts the following technical solutions:

A transformer with a vertical structure integrated on a chip, including a primary coil, a secondary coil, the first one lead (11) and the first two leads (12) of the primary coil, the first three leads (13) and the first four leads of the secondary coil The lead wire (14), the primary coil passes through the seventh metal layer (1) respectively through the second one through hole (V21), the second one metal layer (21), the second two through holes (V22), the second two metal layer ( 22), the second three through holes (V23), the second three metal layers (23), the second four through holes (V24), the second four metal layers (24), the second five through holes (V25) are connected to the first One end of the third metal layer (31) and the other end of the third metal layer (31) are respectively connected through the fourth through hole (V41), the fourth first metal layer (41), and the fourth second through hole (V42) To one end of the fifth first metal layer (51), the other end of the fifth first metal layer (51) is connected to one end of the eighth metal layer (6) through the fifth first through hole (V51), the eighth metal layer (6) The other end of the fifth and second metal layer (52) is connected to one end of the fifth and second metal layer (52) through the fifth and second through holes (V52), and the other end of the fifth and second metal layer (52) respectively passes through the fourth and third through holes (V43), the fourth and second The metal layer (42), the fourth and fourth through holes (V44) are connected to one end of the third and second metal layers (32), and the other end of the third and second metal layers (32) passes through the seventh and fifth through holes (V75), the seventh The fifth metal layer (75), the seventh and fourth vias (V74), the seventh and fourth metal layers (74), the seventh and third vias (V73), the seventh and third metal layers (73), the seventh and second vias (V72 ), the seventh and second metal layers (72), the seventh and first through holes (V71) connected to one end of the ninth metal layer (8); the secondary coil passes through the first and third metal layers (13) and passes through the fifth three-way The hole (V53) is connected to one end of the first fifth metal layer (15), and the other end of the first fifth metal layer (15) passes through the second sixth via hole (V26), the second sixth metal layer (26), the second The seven through holes (V27), the second and seventh metal layers (27), the second and eighth through holes (V28) are connected to the second and eighth metal layers (28), and the other end of the second and eighth metal layers (28) passes through the fifth and fourth Vias (V54), fifth and fourth metal layers (54), fifth and fifth through holes (V55), fifth and fifth metal layers (55), fifth and sixth through holes (V56) are connected to the first and sixth metal layers (16 ), the other end of the first sixth metal layer (16) is connected to the first fourth metal layer (14) through the fifth and seventh via holes (V57)

formed by one end;

The first and first leads (11) are connected to the seventh metal layer (1), the first and second leads (12) are connected to the ninth metal layer (8), and the first and third leads (13) pass through the fifth and third through holes ( V53) is connected to one end of the first fifth metal layer (15), and the first fourth lead (14) is connected to one end of the first sixth metal layer (16) through the fifth and seventh through holes (V57);

The seventh metal layer (1) and the ninth metal layer (8) belong to the first metal layer and are insulated from each other, the fifth metal layer (15), the sixth metal layer (16), the second metal layer (21) and the seventh and second metal layers (72) belong to the second metal layer and are insulated from each other, the second and second metal layers (22), the second and sixth metal layers (26), the fifth and fifth metal layers (55), the The eighth metal layer (6) and the seventh and third metal layers (73) belong to the third metal layer and are insulated from each other, the second and third metal layers (23), the second and seventh metal layers (27), the fifth and first metal layers (51 ), the fifth and second metal layers (52), the fifth and fourth metal layers (54) and the seventh and fourth metal layers (74) belong to the fourth metal layer and are insulated from each other, the second and fourth metal layers (24), the second and eighth The metal layer (28) and the seventh and fifth metal layers (75) belong to the fifth metal layer and are insulated from each other, and the third and first metal layers (31) and the third and second metal layers (32) belong to the sixth metal layer and are insulated from each other ;

The fifth first metal layer (51) and the fifth second metal layer (52), the fourth first metal layer (41) and the fourth second metal layer (42), the third first metal layer (31) and the third second metal layer The metal layer (32) is centrosymmetric;

The central axis of the first metal layer, the central axis of the second metal layer, the central axis of the third metal layer, the central axis of the fourth metal layer, the central axis of the fifth metal layer, and the central axis of the sixth metal layer Located in the same plane, and the plane is perpendicular to the upper and lower surfaces of the chip;

The primary coil and the secondary coil are insulated from each other.

As an optional solution, the first, second, third, fourth, fifth and sixth metal layers are composed of 6 metal layers from top to bottom in a standard CMOS process. the

As an optional solution, the first metal layer has a thickness of 4um, the second metal layer has a thickness of 3um, the third metal layer has a thickness of 0.5um, the fourth metal layer has a thickness of 0.25um, and the fifth metal layer has a thickness of 0.5um. The thickness is 0.25um, the thickness of the sixth metal layer is 0.25um; the thickness of the via hole between the first metal layer and the second metal layer is 1.5um, the via hole between the second metal layer and the third metal layer Its thickness is 2.1um, the thickness of the via hole between the third metal layer and the fourth metal layer is 0.5um, the thickness of the via hole between the fourth metal layer and the fifth metal layer is 0.245um, the fifth metal layer and the fifth metal layer The via thickness between the six metal layers is 0.245 um. the

The beneficial effect of the present invention is that on the one hand, the structure of the transformer is made perpendicular to the horizontal direction of the chip, and its most obvious advantage is that the plane area of the chip occupied is greatly reduced; As a result, the parasitic capacitance between the transformer and the substrate is reduced, which is conducive to improving the resonant frequency of the transformer. Therefore, this structure is suitable for high-frequency circuits. the

Description of drawings

Figure 1 is a forward perspective view of the integrated transformer;

Figure 2 is a left view of the integrated transformer;

Figure 3 is the front view of the integrated transformer;

Fig. 4 is the L-f relationship simulation figure of the embodiment of the present invention;

Fig. 5 is a simulation diagram of the Q-f relationship of the embodiment of the present invention.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. the

This structure uses a total of six metal layers of IBM standard technology. From top to bottom, the first metal layer has a thickness of 4um, the second metal layer has a thickness of 3um, the third metal layer has a thickness of 0.5um, and the fourth metal layer Its thickness is 0.25um, the thickness of the fifth metal layer is 0.25um, and the thickness of the sixth metal layer is 0.25um. The parallel layers of metal are connected by through holes, and the connection between the first metal layer and the second metal layer The thickness of the through hole is 1.5 um, the thickness of the through hole between the second metal layer and the third metal layer is 2.1 um, the thickness of the through hole between the third metal layer and the fourth metal layer is 0.5 um, the fourth metal layer The thickness of the through hole between the fifth metal layer and the fifth metal layer is 0.245 um, and the thickness of the through hole between the fifth metal layer and the sixth metal layer is 0.245 um. the

As shown in Figure 1, the structural details of the transformer are as follows: Firstly, the primary coil is described, the lead wires 11 and 12 are the two ports of the primary coil of the transformer on the first metal layer, and the metal layer 1 and metal layer 8 are interconnections on the same layer of metal. Connection line; line 2 is a connection line perpendicular to the direction of the chip, and its specific composition from top to bottom is through hole V21, metal layer 21, through hole V22, metal layer 22, through hole V23, metal layer 23, through hole V24, metal layer 24, and through hole V25; metal layer 31 is the interconnection line on the sixth metal layer. Viewed from left to right, its direction is to first build a length along the -x axis direction, and then extend along the y axis direction for a section distance. As shown in Figure 2, the metal layer 41 is the interconnection line on the fifth metal layer; the metal layer 51 is the interconnection line on the fourth metal layer, and its direction is first constructed along the -x axis direction when viewed from left to right A length, and then extend a distance along the -y-axis direction, the extension distance is equal to the length of the metal layer 31 extending in the y-axis direction. Metal layer 6 is the interconnection line on the third metal layer; metal layer 52 and metal layer 51, metal layer 42 and metal layer 41, metal layer 32 and metal layer 31 are center-symmetrical, and will not be described here. The structure of line 7 and line 2 They are the same and symmetrical to the center, and are also lines perpendicular to the direction of the chip. the

The current flow direction of the primary coil is: lead wire 11, metal layer 1, wire 2, metal layer 31, via V41, metal layer 41, via V42, metal layer 51, via V51, metal layer 6, via V52, metal Layer 52, via V43, metal layer 42, via V44, metal layer 32, line 7, metal layer 8, lead 12. the

The structure of the secondary coil is that the lead wire 13 and the lead wire 14 are two ports of the secondary coil of the transformer on the first metal layer, and the metal layer 15 and the metal layer 16 are the interconnection lines on the second metal layer; the line 21 is perpendicular to the chip The connection line in the direction, its specific composition from top to bottom is through hole V26, metal layer 26, through hole V27, metal layer 27, through hole V28; metal layer 28 is the interconnection line on the fifth metal layer; line 71 has the same structure as the line 21, and is also a connection line perpendicular to the direction of the chip, which will not be repeated here. the

The current flow direction of the secondary coil is: lead wire 13 , through hole V53 , metal layer 15 , wire 21 , metal layer 28 , wire 71 , metal layer 16 , through hole V57 , lead wire 14 . the

Embodiment one:

The outer diameter of the primary coil of this transformer is OD_pri=140um, the outer diameter of the secondary coil is OD_sec=60um, the line width W=8um, the length of each through hole along the x direction is also 8um, and the length of the four ports is 20um. As shown in FIG. 4 , the dot curve L11 represents the self-inductance value of the primary coil, and the triangular curve L22 represents the self-inductance value of the secondary coil. The transformation ratio of the primary coil and the secondary coil is about 1.5. At the same time, the self-resonant frequency of the structure is relatively high, and there is no resonance at 60GHz, which shows that it is suitable for high-frequency circuits. FIG. 5 is a simulation diagram of the Q-f relationship of this embodiment. The same dot curve Q11 represents the quality factor Q value of the primary coil, and the triangle point curve Q22 represents the quality factor Q value of the secondary coil. It can be seen from the figure that the maximum value peak Q of the quality factor of the primary coil is about 6, and the maximum value peak Q of the quality factor of the secondary coil is about 12. When the current passes through the transformer coil, the periodic magnetic field generated by the alternating current only generates a magnetic field in the surrounding area of the wire, and the induced current generated in the substrate will be correspondingly small, so the transformer has a high Q value. The frequency when peak Q is reached is higher, and this property also shows that it is suitable for higher frequency circuits.

The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present invention, some improvements and modifications can also be made, and these improvements and modifications should also be considered Within the protection scope of the present invention. the

Claims (3)

1. vertical-structure on-chip integrated transformer, comprise primary coil, secondary coil, the one one lead-in wire (11) of primary coil and the one or two lead-in wire (12), the one or three lead-in wire (13) of secondary coil and the one or four lead-in wire (14), it is characterized in that, primary coil by the 7th metal level (1) respectively through the 21 through hole (V21), the 21 metal level (21), the two or two through hole (V22), the two or two metal level (22), the two or three through hole (V23), the two or three metal level (23), the second four-way hole (V24), the two or four metal level (24), the second five-way hole (V25) is connected to an end of the 31 metal level (31), the other end of the 31 metal level (31) is respectively through the 41 through hole (V41), the 41 metal level (41), the four or two through hole (V42) is connected to an end of metal level on May Day (51), metal level on May Day (51) other end is connected to an end of the 8th metal level (6) through through hole on May Day (V51), the other end of the 8th metal level (6) is connected to an end of the five or two metal level (52) through the five or two through hole (V52), the other end of the five or two metal level (52) is respectively through the four or three through hole (V43), the four or two metal level (42), the 4th four-way hole (V44) is connected to an end of the three or two metal level (32), the three or two metal level (32) other end is respectively through the Seventh Five-Year Plan through hole (V75), the Seventh Five-Year Plan metal level (75), the 7th four-way hole (V74), the seven or four metal level (74), the seven or three through hole (V73), the seven or three metal level (73), the seven or two through hole (V72), the seven or two metal level (72), the end that the through hole July 1st (V71) is connected to the 9th metal level (8) forms; Secondary coil is connected to an end of the one or five metal level (15) through the five or three through hole (V53) by the one or three metal level (13), the other end of the one or five metal level (15) is respectively through the two or six through hole (V26), the two or six metal level (26), the two or seven through hole (V27), the two or seven metal level (27), the two or eight through hole (V28) is connected to the two or eight metal level (28), the other end of the two or eight metal level (28) is through the May 4th through hole (V54), the May 4th metal level (54), the 5th five-way hole (V55), the five or five metal level (55), the five or six through hole (V56) is connected to an end of the one or six metal level (16), and the other end of the one or six metal level (16) is connected to the one or four metal level (14) through the five or seven through hole (V57)

An end become;

Described the one one lead-in wire (11) links to each other with the 7th metal level (1), the one or two lead-in wire (12) links to each other with the 9th metal level (8), the one or three lead-in wire (13) links to each other with an end of the one or five metal level (15) through the five or three through hole (V53), and the one or four lead-in wire (14) links to each other with an end of the one or six metal level (16) through the five or seven through hole (V57);

Described the 7th metal level (1) and the 9th metal level (8) belong to the first metal layer and mutually insulated, the one or five metal level (15), the one or six metal level (16), the 21 metal level (21) and the seven or two metal level (72) belong to the second metal level and mutually insulated, the two or two metal level (22), the two or six metal level (26), the five or five metal level (55), the 8th metal level (6) and the seven or three metal level (73) belong to the 3rd metal level and mutually insulated, the two or three metal level (23), the two or seven metal level (27), metal level on May Day (51), the five or two metal level (52), the May 4th metal level (54) and the seven or four metal level (74) belong to the 4th metal level and mutually insulated, the two or four metal level (24), the two or eight metal level (28) and the Seventh Five-Year Plan metal level (75) belong to the 5th metal level and mutually insulated, and the 31 metal level (31) and the three or two metal level (32) belong to the 6th metal level and mutually insulated;

Described metal level on May Day (51) and the five or two metal level (52), the 41 metal level (41) and the four or two metal level (42), the 31 metal level (31) becomes Central Symmetry with the three or two metal level (32);

The axis of the axis of the axis of the axis of the axis of the axis of described the first metal layer, the second metal level, the 3rd metal level, the 4th metal level, the 5th metal level, the 6th metal level is positioned at same plane, and this plane is perpendicular to the chip upper and lower surface;

Described primary coil and secondary coil mutually insulated.

2. a kind of vertical-structure on-chip integrated transformer according to claim 1 is characterized in that, described the first, second, third, fourth, the 5th, the 6th metal level is made of from top to down 6 layers of metal level in the standard CMOS process.

3. a kind of vertical-structure on-chip integrated transformer according to claim 1, it is characterized in that, its thickness of described the first metal layer is that 4um, its thickness of the second metal level are that 3um, its thickness of the 3rd metal level are that 0.5um, its thickness of the 4th metal level are that 0.25um, its thickness of the 5th metal level are that 0.25um, its thickness of the 6th metal level are 0.25um; Through hole thickness between described the first metal layer and the second metal level is that its thickness of through hole between 1.5 um, the second metal level and the 3rd metal level is that through hole thickness between 2.1um, the 3rd metal level and the 4th metal level is that through hole thickness between 0.5 um, the 4th metal level and the 5th metal level is that through hole thickness between 0.245 um, the 5th metal level and the 6th metal level is 0.245 um.

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