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CN100352038C - SOC chip preparing method - Google Patents

SOC chip preparing method Download PDF

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Publication number
CN100352038C
CN100352038C CNB2005101307446A CN200510130744A CN100352038C CN 100352038 C CN100352038 C CN 100352038C CN B2005101307446 A CNB2005101307446 A CN B2005101307446A CN 200510130744 A CN200510130744 A CN 200510130744A CN 100352038 C CN100352038 C CN 100352038C
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polysilicon
soc
electrode
front electrode
soc chip
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CN1815713A (en
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杨利
廖怀林
黄如
张兴
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Peking University
Semiconductor Manufacturing International Beijing Corp
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Peking University
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Abstract

本发明提供一种SOC芯片制备方法,在芯片制备过程中,衬底的位于电路一面上设置一正面电极,该正面电极的形状根据衬底上要生成的多孔硅结构不同而不同,其中,电极材料可使用高掺杂多晶硅多晶硅或P+注入层。针对SOC串扰隔离,多晶硅电极或P+注入层设计为条状;针对射频集成电感,正面电极呈低阻导电带相间隔状。本发明可以实现多孔硅背向选择性的可控生长,而不必变更常规的CMOS工艺步骤,易于实现。

The invention provides a method for preparing an SOC chip. In the chip preparation process, a front electrode is arranged on the circuit side of the substrate, and the shape of the front electrode is different according to the porous silicon structure to be generated on the substrate. Wherein, the electrode The material can use highly doped polysilicon polysilicon or P+ implanted layer. For SOC crosstalk isolation, polysilicon electrodes or P+ injection layers are designed as strips; for RF integrated inductors, the front electrodes are in the shape of low-resistance conductive strips. The invention can realize the controllable growth of porous silicon backside selectivity without changing the conventional CMOS process steps, and is easy to realize.

Description

The SOC chip preparation method
Technical field
The invention belongs to the application of integrated circuit SOC (system level chip System on Chip), be specifically related to a kind of SOC chip preparation method.
Background technology
SOC is meant a product, is an integrated circuit that application-specific target is arranged, and wherein comprises holonomic system and the full content of embedded software is arranged.SOC also has and is called " System on Chip/SoC is integrated ", refers to that it is a kind of technology, divides to software/hardware from determining systemic-function in order to realizing, and finishes the whole process of design.
After first integrated circuit (IC) (nineteen fifty-nine American TI Company) invention, the developing direction of integrated circuit processing technique mainly shows as two aspects: the one, along the raising of the vertical machining accuracy of the horizontal and vertical silicon chip of silicon chip, make device feature size drop to 0.13 μ m from 0.5 μ m of sub-micron, 0.35 μ m of deep-submicron (DSM) always, even 0.1 μ m and following of sub-micro (VDSM), and can form various structures; The 2nd, the expansion of shimming scope makes chip area by 100mm 2Be increased to 200mm 2, 300mm 2Even large scale more.The size of single transistor is being dwindled, and chip area is enlarging, and both products make the CAGR (Commutation Average GrowthRate) of IC integrated level reach 58% every year.Integrated circuit constantly advances according to the Moore law like this.Current microelectronic process technology has reached such degree: all parts that electronic system needs be can on silicon chip, produce, various active and passive components and parts, interconnection line comprised, even mechanical part.Therefore, possessed by the condition of integrated circuit (IC) to the system integration (IS) development.
Simultaneously, IC industrial technology development has experienced that circuit is integrated, function is integrated, technology is integrated, and is integrated based on the knowledge of computer software and hardware up to today.Particularly the appearance of MCU makes the conditional electronic system enter contemporary electronic systems with universal comprehensively.One of target that electronic system is pursued is exactly to simplify circuit design to greatest extent, reaches the reliability, precision of integral product system, quality index such as stable.SOC considers the reliability of Circuits System design, low-power consumption etc. among the IC design, and in the past many problems that need system design to solve are concentrated on solution in the IC design, makes the system engineer energy can be concentrated on all problems in the research object field.SOC naturally becomes the final goal of microelectronic IC design and the optimal selection of contemporary electronic systems.From the above, still be designed capacity and industry demand no matter from the IC process conditions, all SOC has been shifted onto the forward position of technical development.
Because device size constantly reduces by the mole law, the complexity of circuit, operating frequency and integrated level also improve constantly, and the development of SOC is faced with many new challenges.Along with the operating frequency of circuit improves constantly, when frequency near or when surpassing Gigahertz (GHz), crosstalking between substrate coupling and the circuit is more and more obvious to the influence of circuit performance, when Fig. 1 has schematically provided silica-based passive device and has been operated in high frequency, and the situation of substrate coupling and energy loss.In addition, the radio frequency integrated circuit among the SOC needs technology that high-quality passive integrated devices is provided, and the integrated inductor of image height quality especially also is very big challenge to the development of SOC.Nowadays, in the SOC technology to obtain high-quality radio frequency passive device (especially radio frequency plane integrated inductor) and to realize that high-frequency crosstalk is isolated to have become one of focus that current microelectronic pays close attention to.
Isolate about high-frequency crosstalk, people have also proposed multiple technologies and method, triple-well (Triple Well) technology (Redmond as company of Motorola (Motorola), " A GSM/GPRS mixed-signal baseband IC " IEEEInternational Solid-State Circuits Conference (ISSCC), vol.1, pp62-445,2002.), deep trouth (Deep Trench) technology (Tallis Blalack, Youri Leclercq and C.Patrick Yue are at " On-chip RFIsolation Techniques " IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), pp.205-211,2002.), and the guard ring of Ericsson (Ericsson) company or protecting band technology (Guard ring or Guardband) (Van Zeijl, " A Blue-tooth Radio in 0.18um CMOS ", IEEE International Solid-StateCircuits Conference (ISSCC), vol.45, pp86-87,2002.).More than these technology, what have exists the process compatible problem, have only in certain band limits effectively.So need exploitation efficient, low cost, with contemporary CMOS technology mutually compatibility be the developing direction of solution high frequency substrate cross-talk.
About the radio frequency integrated inductor, the quality factor that a lot of methods improve inductance has been proposed in the world, usually can be divided into two big classes: a class is to start with from the wire coil Q value that reduces to improve in the series resistance inductance of starting with, and an other class is to start with from the substrate loss that reduces inductance.The Behzad Rejaei of Holland, (The Delft research team Oct.2002) has reported with selectively deposited smithcraft and has reduced coil resistance Joachim Burghartz and Hugo Schellevis, the method for raising induction quality factor.The Masahiro Yamaguchi of Japan, Makoto Baba, Ken-Ichi Arai is by two-layer insertion ferromagnetic material---the CoNbZr film increases the magnetic flux of inductive current up and down at the planar rectangular spiral inductance, thereby raising inductance value, increase inductance quality factor q (Masahiro Yamaguchi, Makoto Baba, Ken-Ichi Arai, " Sandwich-type Ferromagnetic RF Integrated Inductor; " IEEE Transactions on MicrowaveTheory and Techniques VOL.49, NO.21, Dec.2001).These all belong to first kind method.In order to reduce substrate loss, MEMS technology (M.Ozgur, M.E.Zalloul, and M.Gaitan, " High Q BacksideMicromachined CMOS Inductors; " in Proc.IEEE International Symposium Circuits AndSystems (ISCAS), Vol.II, 1999, pp577-580), shielding (shield) technology (Koji Murata, Taskashi Hoska, and Yasuhiro Sugimoto " Effect of A Ground Shield Of A Silicon On-chip SpiralInductor " Microwave Conference, 2000 Asia-Pacific, 2000, pp177-180.), protonation (Chih-Yuan Lee, Tung-Sheng Chen, Joseph Der-Son Deng, and Chin-Hsing Kao, " A SimpleSystematic Spiral Inductor Design With Perfected Q Improvement for CMOS RFICApplication; " IEEE Transactions on Microwave Theory and Techniques VOL.53, NO.2, Feb.2005, pp.523-528) etc. technology is used for reducing the coupling of substrate.Above method can improve the quality factor of integrated inductor to a certain extent, but because incompatible or cost is too high and the restriction that can not be accepted by industrial quarters with contemporary CMOS technology.
At the challenge in the current SOC technology, we have proposed selectivity and have grown the technical scheme of porous silicon (SBG PS) dorsad with solving the technical barrier that high-quality integrated inductor and substrate cross-talk are isolated among the SOC.It is simple that this technology has method, the advantage of low cost and high efficiency, and wherein selectivity is grown in the porous silicon process dorsad, and the design of front electrode realizes and draws the most keyly that it directly determines the whether compatible mutually problem of conventional cmos technology of this technology.
Summary of the invention
The invention provides a kind of SOC chip preparation method, this method can realize porous silicon controllable growth optionally dorsad, and needn't revise conventional CMOS processing step.
The technology of the present invention content: a kind of SOC chip preparation method, in the chip preparation process, being positioned on the circuit one side of substrate is provided with a front electrode, and this front electrode adopts polysilicon or P+ implanted layer, and its shape is different and different according to the porous silicon structure that will generate on the substrate.
Can also deposit one silicon nitride separator on front electrode.
Crosstalk towards SOC and to isolate and two kinds of application of integrated inductor, front electrode making and draw and be divided into two classes:
(1) at the SOC isolation of crosstalking, polysilicon electrode or P+ implanted layer are designed to strip, the polysilicon strip of its typical plane plan structure as shown in Fig. 2-b, and for concrete application, its shape can be made corresponding change;
(2) at the radio frequency integrated inductor, before making integrated inductor, heavily doped polysilicon or P+ implanted layer are processed into Shields structure as shown in Fig. 3-b, be low-resistance conductive strips shapes separately, can guarantee the formation of front electric field like this, can guarantee that again the introducing of electrode can not influence to some extent to the characteristic of inductance.Low-resistance conductive strips material adopts polysilicon or P+ to inject, and its interval adopts N+ to inject or non-injection body silicon.
With respect to traditional metal electrode manufacture method, polysilicon and P+ injection technology all are the materials of using widely in the integrated circuit manufacturing industry, with the CMOS process compatible, be easy to realize, can not exert an influence to other follow-up active or passive preparation, if adopt metal to do electrode, will produce adverse influence to subsequent technique, metal can only be as the lead-in wire of electrode in this invention.
Electrode for the Shields structure, the Shields itself that highly doped polysilicon or P+ implanted layer form helps the quality factor of integrated inductor to improve, the highly doped polysilicon of full wafer is placed on and makes extraction electrode below the inductance in addition, can have a negative impact to the perception of inductance, make whole inductance than presenting capacitive character under the low frequency.
Description of drawings
Below in conjunction with accompanying drawing, the present invention is made detailed description.
Fig. 1 is under the high frequency situations, and signal is in transmission course, because the loss that causes of substrate and crosstalking of causing thus.
Fig. 2 crosstalks at SOC to isolate designed polysilicon electrode, and a and b are the contrast schematic diagram that has or not polysilicon or P+ implanted layer electrode.
Fig. 3-a integrated inductor planar structure schematic diagram; Fig. 3-b is the schematic diagram of Shields structure electrode; Fig. 3-c is the schematic diagram that adds below the integrated inductor after polysilicon or the P+ implanted layer electrode.
Fig. 4 is to be electrode with polysilicon or P+ implanted layer, and the utilization selectivity porous silicon technology of growing dorsad realizes that the SOC crosstalk signal isolates schematic diagram.Fig. 4-a is that porous silicon is isolated before the formation, has the cross section structure of polysilicon or P+ implanted layer electrode, and Fig. 4-b is the cross section structure after the porous silicon isolation structure forms.
Fig. 5 is to be electrode with Shield structure polysilicon or P+ implanted layer, and the utilization selectivity porous silicon technology of growing dorsad realizes the schematic diagram of high-quality integrated inductor.Fig. 5-a is before porous silicon isolate to form, and has the integrated inductor cross section structure of polysilicon electrode polysilicon or P+ implanted layer, and Fig. 5-b is for after the porous silicon isolation structure forms, the cross section structure schematic diagram of high-quality integrated inductor.
Among the figure, 1-body silicon; 2-silicon dioxide; The 3-metal; The 4-signal pins; The 5-front electrode; 6-isolates silicon nitride layer; The 7-porous silicon.
Embodiment
Realize that with the selectivity porous silicon of growing dorsad high-quality integrated inductor is an example, briefly introduce below that polysilicon electrode is made and the application in the integrated inductor of the high-quality plane of preparation, the manufacture method of P+ implanted layer electrode is similar.Polysilicon electrode and the application of making in the high-quality integrated inductor thereof can be divided into two stages enforcements: (A) making of Shields structure polysilicon electrode; (B) making of plane integrated inductor; (C) realization of high-quality integrated inductor promptly selects to grow dorsad porous silicon.
The present invention is that example describes in detail with underlayer electrode in the fabrication and processing process of planar spiral inductor, and concrete steps are:
The making of A.Shields structure polysilicon electrode
1, cleans original Si substrate slice;
2, oxidation generates SiO 2, thickness is 20nm;
3, LPCVD deposit Si 3N 4Protective layer, thickness are 50nm;
4, photoetching Si 3N 4Protective layer;
6, LPCVD deposit polysilicon, thickness are 400nm;
7, inject phosphonium ion, energy is 60kev, and dosage is 5el5cm -2, form the highly doped polysilicon layer;
8, photoetching, formation Shields structure polysilicon electrode;
B. the making of plane integrated inductor (under the preorder processing step, continuing)
1, LPCVD deposit one deck plays the SiO of buffer action 2, thickness is 500nm;
2, photoetching SiO 2, domain is that the electrode contact hole designs;
3, be used in SiO in the method erosion removal part contact hole 2And Si 3N 4
4, adopt wet etching, corrode the remaining SiO of clean contact hole 2
5, sputter layer of metal Al, thickness are 1000nm;
6, photoetching layer of metal Al, domain is for forming inductance lower floor lead-in wire and contact conductor;
7, dry etching aluminium forms inductance lower floor lead-in wire and contact conductor;
8, annealing to be to form alloy, makes contact conductor and p +Form ohmic contact between the layer, reduce contact resistance;
9, PECVD deposit SiO 2, thickness is 800nm;
10, photoetching through hole;
11, the clean SiO of RIE etching 2
12, splash-proofing sputtering metal Al, thickness are 1500nm;
13, photoetching, domain are the domain of planar spiral inductor;
14, dry etching Al forms the planar spiral inductor coil;
15, annealing makes between one deck Al metal and the Al coil and forms ohmic contact to form alloy, reduces contact resistance;
16, PECVD deposit passivation layer SiO 2, thickness is 1000nm;
17, photoetching pressure welding hole, domain are the pressure welding hole that metal A l coil contacts with pad;
18, first wet method is omited corrosion and passivation layer SiO 2
19, the passivation layer SiO of dry etching fine pressure welding hole 2, finish conventional integrated inductor and make, and the pressure welding extraction electrode.
So far, the polysilicon electrode of previous preparation was interconnected by through hole and external metallization, and additional power source can be by polysilicon electrode at the zone of the selective area growth formation porous silicon necessary electric field of growing.
(C) realization of high-quality integrated inductor
1, sample is encapsulated from the both sides sealing or with back-off weldering mode with anti-HF acid adhesive tape;
2, press HF: C 2H 5OH: H 2O=1: the solution ratio preparation corrosive liquid of 1: 2 (mol ratio);
3, sample is fixed on the porous silicon apparatus for preparation, in etching tank, injects the corrosive liquid for preparing;
4, the controllable growth of constituency porous silicon;
5, corrosion finishes, and sample is carried out dried, increases the steadiness of sample;
6, finish the manufacturing of high-quality integrated inductor.
Shields structure polysilicon electrode also can adopt other low-resistance conductive strips structure separately as shown in Fig. 3-b.
Polysilicon or P+ implanted layer electrode by this scheme making, in the required structure of the formation of porous, this electrode can become the part of porous silicon, final when polysilicon electrode or P+ implanted layer all disappear the porous silicon growth stop, the porous silicon of this moment reaches the requirement of SOC isolation or high Q inductor just.
Although disclose preferred embodiment of the present invention and accompanying drawing for the purpose of illustration, its purpose is to help to understand content of the present invention and implement according to this, but person skilled in the art, without departing from the spirit and scope of the invention and the appended claims, can do various replacements, variation and retouching.Therefore, the present invention should not be limited to most preferred embodiment and the disclosed content of accompanying drawing, and protection scope of the present invention is as the criterion with the scope that appending claims was defined.

Claims (6)

1、一种SOC芯片制备方法,在芯片制备过程中,在衬底位于电路的一面上设置一正面电极,该正面电极采用多晶硅或P+注入层,其形状根据衬底上要生成的多孔硅结构不同而不同。1, a kind of SOC chip preparation method, in chip preparation process, a front electrode is arranged on the one side that is positioned at circuit on substrate, this front electrode adopts polysilicon or P+ injection layer, and its shape is according to the porous silicon structure that will generate on the substrate It varies from person to person. 2、如权利要求1所述SOC芯片制备方法,其特征在于:针对SOC串扰隔离,该正面电极为一个或多个条状结构。2. The method for fabricating an SOC chip according to claim 1, wherein, for SOC crosstalk isolation, the front electrode is one or more strip structures. 3、如权利要求1所述SOC芯片制备方法,其特征在于:针对射频集成电感,该正面电极呈低阻导电带相间隔状。3. The manufacturing method of the SOC chip according to claim 1, characterized in that: for the radio frequency integrated inductor, the front electrodes are in the shape of low-resistance conductive strips spaced apart. 4、如权利要求1所述SOC芯片制备方法,其特征在于:在正面电极上淀积一氮化硅隔离层。4. The method for manufacturing an SOC chip according to claim 1, wherein a silicon nitride isolation layer is deposited on the front electrode. 5、如权利要求3所述SOC芯片制备方法,其特征在于:针对射频集成电感,正面电极的低阻导电带材料采用多晶硅或P+注入,其间隔处采用N+注入。5. The SOC chip manufacturing method according to claim 3, characterized in that: for radio frequency integrated inductors, polysilicon or P+ implantation is used for the low-resistance conductive band material of the front electrode, and N+ implantation is used for the gap. 6、如权利要求3所述SOC芯片制备方法,其特征在于:针对射频集成电感,正面电极的低阻导电带材料采用多晶硅或P+注入,其间隔处为非注入体硅。6. The SOC chip manufacturing method according to claim 3, characterized in that: for the radio frequency integrated inductor, the low-resistance conductive band material of the front electrode is implanted with polysilicon or P+, and the interval between them is non-implanted silicon.
CNB2005101307446A 2005-12-27 2005-12-27 SOC chip preparing method Expired - Fee Related CN100352038C (en)

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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8058960B2 (en) * 2007-03-27 2011-11-15 Alpha And Omega Semiconductor Incorporated Chip scale power converter package having an inductor substrate
CN102709159A (en) * 2012-06-28 2012-10-03 上海集成电路研发中心有限公司 Soc substrate and manufacturing method thereof
CN102738125B (en) * 2012-06-29 2015-01-28 杭州电子科技大学 New fractal PFS structure
CN111699551B (en) * 2019-01-15 2023-10-17 深圳市汇顶科技股份有限公司 Chip and method for manufacturing chip

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331977B1 (en) * 1998-08-28 2001-12-18 Sharp Electronics Corporation System on chip (SOC) four-way switch crossbar system and method
CN1601707A (en) * 2004-09-30 2005-03-30 北京大学 Processing method of SOC silicon substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331977B1 (en) * 1998-08-28 2001-12-18 Sharp Electronics Corporation System on chip (SOC) four-way switch crossbar system and method
CN1601707A (en) * 2004-09-30 2005-03-30 北京大学 Processing method of SOC silicon substrate

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