CN100352038C - SOC chip preparing method - Google Patents
SOC chip preparing method Download PDFInfo
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- CN100352038C CN100352038C CNB2005101307446A CN200510130744A CN100352038C CN 100352038 C CN100352038 C CN 100352038C CN B2005101307446 A CNB2005101307446 A CN B2005101307446A CN 200510130744 A CN200510130744 A CN 200510130744A CN 100352038 C CN100352038 C CN 100352038C
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- Prior art keywords
- polysilicon
- soc
- electrode
- front electrode
- soc chip
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 229920005591 polysilicon Polymers 0.000 claims abstract description 34
- 229910021426 porous silicon Inorganic materials 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000002360 preparation method Methods 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims abstract description 5
- 238000002347 injection Methods 0.000 claims abstract description 4
- 239000007924 injection Substances 0.000 claims abstract description 4
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims 2
- 238000005516 engineering process Methods 0.000 description 26
- 239000010410 layer Substances 0.000 description 22
- 238000013461 design Methods 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
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Abstract
本发明提供一种SOC芯片制备方法,在芯片制备过程中,衬底的位于电路一面上设置一正面电极,该正面电极的形状根据衬底上要生成的多孔硅结构不同而不同,其中,电极材料可使用高掺杂多晶硅多晶硅或P+注入层。针对SOC串扰隔离,多晶硅电极或P+注入层设计为条状;针对射频集成电感,正面电极呈低阻导电带相间隔状。本发明可以实现多孔硅背向选择性的可控生长,而不必变更常规的CMOS工艺步骤,易于实现。
The invention provides a method for preparing an SOC chip. In the chip preparation process, a front electrode is arranged on the circuit side of the substrate, and the shape of the front electrode is different according to the porous silicon structure to be generated on the substrate. Wherein, the electrode The material can use highly doped polysilicon polysilicon or P+ implanted layer. For SOC crosstalk isolation, polysilicon electrodes or P+ injection layers are designed as strips; for RF integrated inductors, the front electrodes are in the shape of low-resistance conductive strips. The invention can realize the controllable growth of porous silicon backside selectivity without changing the conventional CMOS process steps, and is easy to realize.
Description
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CNB2005101307446A CN100352038C (en) | 2005-12-27 | 2005-12-27 | SOC chip preparing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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CNB2005101307446A CN100352038C (en) | 2005-12-27 | 2005-12-27 | SOC chip preparing method |
Publications (2)
Publication Number | Publication Date |
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CN1815713A CN1815713A (en) | 2006-08-09 |
CN100352038C true CN100352038C (en) | 2007-11-28 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CNB2005101307446A Expired - Fee Related CN100352038C (en) | 2005-12-27 | 2005-12-27 | SOC chip preparing method |
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CN (1) | CN100352038C (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8058960B2 (en) * | 2007-03-27 | 2011-11-15 | Alpha And Omega Semiconductor Incorporated | Chip scale power converter package having an inductor substrate |
CN102709159A (en) * | 2012-06-28 | 2012-10-03 | 上海集成电路研发中心有限公司 | Soc substrate and manufacturing method thereof |
CN102738125B (en) * | 2012-06-29 | 2015-01-28 | 杭州电子科技大学 | New fractal PFS structure |
CN111699551B (en) * | 2019-01-15 | 2023-10-17 | 深圳市汇顶科技股份有限公司 | Chip and method for manufacturing chip |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6331977B1 (en) * | 1998-08-28 | 2001-12-18 | Sharp Electronics Corporation | System on chip (SOC) four-way switch crossbar system and method |
CN1601707A (en) * | 2004-09-30 | 2005-03-30 | 北京大学 | Processing method of SOC silicon substrate |
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2005
- 2005-12-27 CN CNB2005101307446A patent/CN100352038C/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6331977B1 (en) * | 1998-08-28 | 2001-12-18 | Sharp Electronics Corporation | System on chip (SOC) four-way switch crossbar system and method |
CN1601707A (en) * | 2004-09-30 | 2005-03-30 | 北京大学 | Processing method of SOC silicon substrate |
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CN1815713A (en) | 2006-08-09 |
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Free format text: CORRECT: ADDRESS; FROM: 100871 HAIDIAN, BEIJING TO: 100176 DAXING, BEIJING |
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Effective date of registration: 20130523 Address after: 100176 No. 18, Wenchang Avenue, Beijing economic and Technological Development Zone Patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Peking University Address before: 100871 Beijing the Summer Palace Road, Haidian District, No. 5 Patentee before: Peking University |
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