CN1319163C - Semiconductor package with heat sink - Google Patents
Semiconductor package with heat sink Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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Abstract
Description
技术领域technical field
本发明是关于一种具有散热片的半导体封装件,特别是关于一种可稳固粘接散热片以避免其脱落的具有散热片的半导体封装件。The present invention relates to a semiconductor package with a heat sink, in particular to a semiconductor package with a heat sink that can firmly bond the heat sink to prevent it from falling off.
背景技术Background technique
倒装芯片球栅阵列(Flip-Chip Ball Grid Array,FCBGA)半导体封装件是一种同时具有倒装芯片与球栅阵列的封装结构,使至少一芯片的有源表面(Active Surface)通过多个焊点(Solder Bumps)电性连接至基板(Substrate)的一表面上,并在基板的另一表面上植设多个作为输入/输出(I/O)端的焊球(Solder Ball);这种封装结构可大幅缩减体积,同时也去掉了现有焊线(Wire)的设计,可降低阻抗、提高电性,以避免信号在传输过程中衰退,因此已成为芯片与电子组件的主流封装技术。Flip-chip ball grid array (Flip-Chip Ball Grid Array, FCBGA) semiconductor package is a packaging structure with flip chip and ball grid array at the same time, so that the active surface (Active Surface) of at least one chip passes through multiple The solder joints (Solder Bumps) are electrically connected to one surface of the substrate (Substrate), and a plurality of solder balls (Solder Ball) as input/output (I/O) terminals are planted on the other surface of the substrate; this The packaging structure can greatly reduce the volume, and also eliminate the existing wire design, which can reduce impedance and improve electrical properties to avoid signal degradation during transmission. Therefore, it has become the mainstream packaging technology for chips and electronic components.
由于倒装芯片球栅阵列封装的优越特性,使它多用于高集成度(Integration)的多芯片封装件中,以满足这种电子组件的体积与运算需求,但是由于这类电子组件高频率的运算特性,使其在运行过程中产生的热量比一般封装件高,因此,散热效果是否良好成为影响这类封装技术品质优良率的重要关键;现有的倒装芯片球栅阵列封装件是直接将散热片(Heat Sink)粘覆在芯片的无源表面(Non-active Surface)上,而不通过导热性较差的封装胶体(Encapsulant)传递热量,从而形成芯片-胶粘剂-散热片-外界的直接散热路径,达到比其它封装件更好的散热效果。Due to the superior characteristics of flip-chip ball grid array packaging, it is mostly used in highly integrated multi-chip packages to meet the volume and computing requirements of such electronic components, but due to the high frequency of such electronic components The calculation characteristics make it generate more heat than ordinary packages during operation. Therefore, whether the heat dissipation effect is good or not has become an important key to the quality rate of this type of packaging technology; the existing flip-chip ball grid array package is directly Stick the heat sink (Heat Sink) on the non-active surface (Non-active Surface) of the chip, without transferring heat through the poor thermal conductivity encapsulant (Encapsulant), thus forming a chip-adhesive-heat sink-external Direct heat dissipation path to achieve better heat dissipation than other packages.
对于这类封装结构,在现有技术中,是直接以胶粘剂(Adhesive)或焊料(Solder)等胶粘材料将散热片粘接在基板上,并使散热片的面积大于芯片的面积,以达到较佳的散热效果,例如美国专利第5,311,402号案、第5,396,403号案、第5,931,222号案、第5,637,920号案、第5,650,918号案或第6,011,304号案所揭示的;但是,在这种粘置方法中散热片与基板间的实际粘接面积并不大,限制了它的粘接稳固性,尤其当基板上还接置有其它提高其电性效能的被动组件(Passive Component)时,更加缩减了基板与散热片的粘接面积,使散热片极易在后续冲击试验(Shock Test)或其它外力震动时,承受一剪切力而脱落。For this type of packaging structure, in the prior art, the heat sink is directly bonded to the substrate with adhesive materials such as adhesive (Adhesive) or solder (Solder), and the area of the heat sink is larger than the area of the chip, so as to achieve Better heat dissipation, such as those disclosed in U.S. Patent No. 5,311,402, No. 5,396,403, No. 5,931,222, No. 5,637,920, No. 5,650,918 or No. 6,011,304; The actual bonding area between the heat sink and the substrate is not large, which limits its bonding stability, especially when there are other passive components (Passive Components) that improve its electrical performance on the substrate, it is even more reduced. The bonding area between the substrate and the heat sink makes it easy for the heat sink to fall off under a shear force during the subsequent shock test (Shock Test) or other external vibrations.
为解决这种问题,美国专利第6,093,961号案还揭示一种封装件结构,通过机械方式加强散热片的接合稳固性,如图11所示,在散热片50的边缘设计具有弹性的勾状支脚51,以卡接的方式将散热片50卡合在芯片52上,以提高散热片50的接合稳固性,然而,这种设计方式只考虑到散热片50的牢固,却造成封装件更大的破坏,这是由于散热片50与芯片52的热膨胀系数(Coefficient ofThermal Expansion,CTE)相差很大,所以散热片50的接触表面53与勾状支脚51极易在后续高温工序或可靠度测试中,因其与芯片52的热变形差异量而压挤芯片52,进而导致芯片52的破裂(Crack)。To solve this problem, U.S. Patent No. 6,093,961 also discloses a package structure that mechanically strengthens the joint stability of the heat sink. As shown in FIG. 11 , an elastic hook-shaped leg is designed on the edge of the
综上所述,如何在降低散热片与芯片的接触面积的情况下强化该散热片的粘着力,是一重要的研发方向,因此,还有人提出数种用外加固定件定位散热片的连接方法,如图12所示的美国专利第5,396,403号案,即是分别在散热片60与基板61的对应位置上开设定位孔62、63,用螺栓64嵌设其中,以避免散热片60的脱落,美国专利第5,926,371号案也揭示了近似的连接方法;除了上述的螺接方式外,也有用卡合件定位散热片的结构,例如美国专利第6,441,485号案,如图13所示,即是将设置在散热片70边缘的勾状结构71嵌设在基板72上的孔洞73中,以定位散热片70。To sum up, how to strengthen the adhesion of the heat sink while reducing the contact area between the heat sink and the chip is an important research and development direction. Therefore, some people have proposed several connection methods for positioning the heat sink with external fixing parts , the U.S. Patent No. 5,396,403 case shown in Figure 12 is to set up
然而,对上述各种用外加固定件定位散热片的现有结构而言,其共同点是必须在基板上预留面积上开设孔洞,这种设计可减少基板上可利用的线路布局面积,同时也增加了基板制造成本,且如果该孔洞在工序中被外界湿气或污染物侵入,将无法预知封装件的优良率。However, for the above-mentioned existing structures that use external fixing parts to locate the heat sink, the common point is that holes must be opened on the reserved area on the substrate. This design can reduce the available circuit layout area on the substrate, and at the same time It also increases the manufacturing cost of the substrate, and if the hole is invaded by external moisture or pollutants during the process, the good rate of the package cannot be predicted.
因此,相关改良逐渐向改变散热片设计以强化其粘着的方向发展,以避免在固定散热片的同时损及芯片与基板的原有功能,图14即是其中一种设计的封装件剖视图,其特点是在散热片80与基板81接触的表面上开设一道凹槽82,通过胶粘材料83在凹槽82中的填充,增加散热片80与胶粘材料83的接触面积,进而提高散热片80的固着性;然而,这类设计提供的散热片粘着性仅略高于直接将散热片粘覆于基板上的方式,难以应付后续冲击试验与运送过程的震动环境,仍然无法解决散热片脱落的问题,也不符合使用者的需要。Therefore, related improvements are gradually developing toward changing the design of the heat sink to strengthen its adhesion, so as to avoid damaging the original functions of the chip and the substrate while fixing the heat sink. Figure 14 is a cross-sectional view of one of the designed packages. The feature is that a groove 82 is set on the contact surface of the heat sink 80 and the substrate 81, and the filling of the adhesive material 83 in the groove 82 increases the contact area between the heat sink 80 and the adhesive material 83, thereby improving the heat sink 80. However, the adhesion of the heat sink provided by this type of design is only slightly higher than that of directly attaching the heat sink to the substrate, which is difficult to cope with the subsequent impact test and the vibration environment during transportation, and still cannot solve the problem of the heat sink falling off. problem, and does not meet the needs of users.
近期的发展则是针对图14的设计作一改良,如图15所示,将散热片上的凹槽改为一鸠尾槽式凹槽结构91,令其开口端的口径略小于内壁口径,以加强散热片90的附着,这种设计确实提高了散热片90的粘着效果,但仍不能满足量产的需要,这是因为,在现有机械制造的卡具中,要形成口径具有连续变化的渐缩或渐增凹槽是制造上的难题,更何况像半导体封装般的微小尺寸技术领域,因此,图15所示的鸠尾槽结构91虽具有理论上的功效,但是其工序实现起来却极为困难,精度也难以控制,难满足量产规模与其成本需求。The recent development is to improve the design of Figure 14. As shown in Figure 15, the groove on the heat sink is changed to a dovetail groove structure 91, so that the diameter of the opening end is slightly smaller than the diameter of the inner wall to strengthen The attachment of the heat sink 90, this design has indeed improved the adhesion effect of the heat sink 90, but it still cannot meet the needs of mass production. Shrinking or gradually increasing the groove is a difficult problem in manufacturing, not to mention the micro-sized technical field like semiconductor packaging. Therefore, although the dovetail groove structure 91 shown in FIG. 15 has theoretical effects, its process is very difficult to realize. Difficult, the accuracy is also difficult to control, and it is difficult to meet the mass production scale and cost requirements.
通过上述现有技术的改革过程可发现,若针对强化散热片粘着的课题进行改良,在解决现有问题的同时又衍生了其它工序限制,或者虽能克服所有难题,却耗费极高的工序成本,难以进行商业实施,所以始终没有一种能充分符合产业需求的解决方式。Through the reform process of the above-mentioned existing technology, it can be found that if the problem of strengthening the adhesion of the heat sink is improved, other process restrictions will be derived while solving the existing problems, or even though all the problems can be overcome, it will consume extremely high process costs. , It is difficult to carry out commercial implementation, so there has never been a solution that can fully meet the needs of the industry.
综上所述,如何开发出一种具有散热片的半导体封装件,以令散热片不致脱落,同时还可兼顾工序简单与成本低廉的需求,也不致降低芯片与基板的优良率,是相关研发领域需迫切面对的课题。In summary, how to develop a semiconductor package with a heat sink so that the heat sink does not fall off, and at the same time, it can also meet the needs of simple process and low cost, without reducing the good rate of chips and substrates, is a related research and development. urgent issues in the field.
发明内容Contents of the invention
为克服上述现有技术的缺点,本发明的目的在于提供一种可稳固粘接散热片以避免其脱落的具有散热片的半导体封装件。In order to overcome the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a semiconductor package with a heat sink that can be firmly bonded to prevent the heat sink from falling off.
本发明的还一目的在于提供一种工序简单且具有散热片锁固功能的具有散热片的半导体封装件。Another object of the present invention is to provide a semiconductor package with a heat sink that has a simple process and has a heat sink locking function.
本发明的另一目的在于提供一种低成本的具有散热片的半导体封装件。Another object of the present invention is to provide a low-cost semiconductor package with a heat sink.
本发明的再一目的在于提供一种不致影响基板上的线路布局而可稳固粘接散热片的具有散热片的半导体封装件。Another object of the present invention is to provide a semiconductor package with a heat sink that can be firmly bonded to the heat sink without affecting the circuit layout on the substrate.
本发明的又一目的在于提供一种不致造成芯片破裂的具有散热片的半导体封装件。Another object of the present invention is to provide a semiconductor package with a heat sink that does not cause chip cracks.
为达上述及其它目的,本发明提供的具有散热片的半导体封装件包括:具有一第一表面与一相对的第二表面的基板;至少一芯片,接置在基板的第一表面上且电性连接至基板;散热片,具有一平坦部与自该平坦部边缘延伸出的支撑部,通过该支撑部接置在基板的第一表面上,并将芯片包覆在平坦部、支撑部与基板围置成的空间中,其中,支撑部与基板接触的表面上具有凹部,且凹部的表面上具有至少一突起单元;胶粘材料,敷设在散热片的支撑部与基板的第一表面间,以填充入凹部中并包覆该突起单元的周围;以及多个焊球,植接在基板的第二表面上。其中,上述凹部可为凹槽或多个开口。To achieve the above and other objects, the semiconductor package provided by the present invention includes: a substrate having a first surface and an opposite second surface; at least one chip is connected to the first surface of the substrate and electrically The heat sink has a flat part and a support part extending from the edge of the flat part, and the support part is connected to the first surface of the substrate through the support part, and the chip is covered on the flat part, the support part and the In the space surrounded by the substrate, there is a recess on the surface of the support part in contact with the substrate, and at least one protrusion unit is provided on the surface of the recess; the adhesive material is laid between the support part of the heat sink and the first surface of the substrate , to fill into the recess and cover the surrounding of the protruding unit; and a plurality of solder balls, implanted on the second surface of the substrate. Wherein, the above-mentioned concave portion may be a groove or a plurality of openings.
本发明的具有散热片的半导体封装件也可包括:具有一第一表面与一相对的第二表面的基板;至少一芯片,接置在基板的第一表面上且电性连接至基板;一散热片,具有一平坦部与自该平坦部边缘延伸出的支撑部,通过该支撑部接置在基板的第一表面上,并将芯片包覆在平坦部、支撑部与基板围置成的空间中,其中,支撑部未与该基板接触的表面上具有至少一突起单元;一胶粘材料,敷设在散热片的支撑部与基板的第一表面间,以及该支撑部的表面,以包覆在突起单元的周围;以及多个焊球,植接在基板的第二表面上。The semiconductor package with a heat sink of the present invention may also include: a substrate having a first surface and an opposite second surface; at least one chip mounted on the first surface of the substrate and electrically connected to the substrate; The heat sink has a flat portion and a support portion extending from the edge of the flat portion, the support portion is connected to the first surface of the substrate, and the chip is covered by the flat portion, the support portion, and the substrate. In the space, wherein, there is at least one protruding unit on the surface of the support part that is not in contact with the substrate; an adhesive material is laid between the support part of the heat sink and the first surface of the substrate, and the surface of the support part to cover covering around the protruding unit; and a plurality of solder balls planted on the second surface of the substrate.
上述的突起单元可为单一毛刺(Burr)、双勾毛刺、或一整排式毛刺,且其形成于凹槽或开口的两相对内壁表面上,或是形成于支撑部的内壁表面上,并令其突起朝向基板的第一表面,而该突起单元可用尖角冲压头(Punch)冲制(Stamp)成形,也可用水平冲压头刮制成形。The above-mentioned protruding unit can be a single burr, a double-hook burr, or a whole row of burrs, and it is formed on two opposite inner wall surfaces of the groove or opening, or on the inner wall surface of the support portion, and The protrusion faces the first surface of the substrate, and the protrusion unit can be formed by punching (Stamp) with a pointed punch (Punch), or can be formed by scraping with a horizontal punch.
此外,该凹槽或开口也是用冲压头冲制而成,其截面形状根据冲压头的种类而定,可为方形、V字型、半圆形或其它形状。In addition, the groove or opening is also punched by a stamping head, and its cross-sectional shape depends on the type of the stamping head, which can be square, V-shaped, semicircular or other shapes.
因此,通过上述的突起单元设计,即可利用该胶粘材料而将散热片粘置在基板的第一表面上,并施压使胶粘材料填充入凹槽或开口中,以包覆于突起单元周围,或直接包覆于支撑部表面的突起单元周围,进而通过突起单元与胶粘材料的接触,提供锁固散热片的力量,使散热片不致在受震时轻易脱落,且工序简易,成本低廉。同时,其结构设计也不会影响基板上的线路布局及造成芯片破裂。Therefore, through the design of the above-mentioned protruding unit, the adhesive material can be used to stick the heat sink on the first surface of the substrate, and pressure is applied to fill the adhesive material into the groove or opening to cover the protrusion. Around the unit, or directly covering the protruding unit on the surface of the support part, and then through the contact between the protruding unit and the adhesive material, it provides the force to lock the heat sink, so that the heat sink will not fall off easily when it is shaken, and the process is simple. low cost. At the same time, its structural design will not affect the circuit layout on the substrate and cause chip breakage.
附图说明Description of drawings
图1A是本发明的具散热片半导体封装件的较佳实施例剖视图;1A is a cross-sectional view of a preferred embodiment of a semiconductor package with a heat sink of the present invention;
图1B是图1所示的散热片的仰视图;Fig. 1B is a bottom view of the heat sink shown in Fig. 1;
图2A是图1所示的凹槽的成形示意图;Fig. 2A is the forming schematic view of the groove shown in Fig. 1;
图2B是图1所示的突起单元的成形示意图;Fig. 2B is a schematic diagram of forming the protrusion unit shown in Fig. 1;
图3是图1所示的散热片支撑部与基板的粘着示意图;Fig. 3 is a schematic diagram of adhesion between the heat sink supporting part and the substrate shown in Fig. 1;
图4是本发明的突起单元的实施例2示意图,为该散热片的仰视图;Fig. 4 is a schematic diagram of Embodiment 2 of the protruding unit of the present invention, which is a bottom view of the heat sink;
图5A及图5B是本发明的突起单元的实施例3示意图;5A and 5B are schematic diagrams of Embodiment 3 of the protrusion unit of the present invention;
图6A至图6C是本发明的突起单元的实施例4示意图;6A to 6C are schematic diagrams of Embodiment 4 of the protrusion unit of the present invention;
图7A及图7B是本发明的凹槽的其它实施例示意图;7A and 7B are schematic diagrams of other embodiments of the groove of the present invention;
图8A及图8B是本发明的凹槽的其它实施例示意图;8A and 8B are schematic diagrams of other embodiments of the groove of the present invention;
图9A是本发明的具散热片半导体封装件的另一实施例剖视图;9A is a cross-sectional view of another embodiment of the semiconductor package with heat sink of the present invention;
图9B是图9A所示的散热片的仰视图;Fig. 9B is a bottom view of the heat sink shown in Fig. 9A;
图10是本发明的具散热片半导体封装件的再一实施例剖视图;10 is a cross-sectional view of yet another embodiment of a semiconductor package with a heat sink of the present invention;
图11是美国专利第6,093,961号案揭示的封装件剖视图;FIG. 11 is a cross-sectional view of a package disclosed in US Patent No. 6,093,961;
图12是美国专利第5,396,403号案揭示的封装件剖视图;12 is a cross-sectional view of a package disclosed in US Patent No. 5,396,403;
图13是美国专利第6,441,485号案揭示的封装件剖视图;13 is a cross-sectional view of a package disclosed in US Patent No. 6,441,485;
图14是现有的在散热片上开设凹槽的封装件剖视图;以及Figure 14 is a cross-sectional view of a conventional package with grooves on the heat sink; and
图15是现有的在散热片上开设鸠尾槽式凹槽结构的封装件剖视图。FIG. 15 is a cross-sectional view of a conventional package with a dovetail groove structure on the heat sink.
具体实施方式Detailed ways
实施例1Example 1
图1A是本发明的具有散热片半导体封装件的较佳实施例剖视图,它是一倒装芯片球栅阵列封装件1(FCBGA),包括作为芯片承载件(Chip Carrier)的基板10,以凸块11电性连接至基板10且接置在基板10的第一表面10a上的芯片12,填充于凸块11周围的底部填料(Underfill)绝缘材料13,接置在基板10的第一表面10a上的方形散热片14,敷设于散热片14与基板第一表面10a间的胶粘材料15,以及植接于基板10的第二表面10b且与多个凸块11电性连接的多个焊球16;其中,该方形散热片14具有一方形平坦部14a与自该平坦部14a周围向基板10方向延伸的支撑部14b,通过支撑部14b粘接在基板10的第一表面10a上,同时,环状支撑部14b上开设有一封闭式凹槽17,且凹槽17内的两个相对内壁表面上,分别具有多个间隔排列的突起单元18,并令突起单元18的突起朝向基板10的方向。1A is a sectional view of a preferred embodiment of a semiconductor package with a heat sink of the present invention, which is a flip-chip ball grid array package 1 (FCBGA), including a substrate 10 as a chip carrier (Chip Carrier), with a bump The block 11 is electrically connected to the substrate 10 and placed on the chip 12 on the first surface 10a of the substrate 10, the underfill insulating material 13 filled around the bump 11 is placed on the first surface 10a of the substrate 10 The square heat sink 14 on the top, the adhesive material 15 laid between the heat sink 14 and the first surface 10a of the substrate, and a plurality of solders that are implanted on the second surface 10b of the substrate 10 and electrically connected with the plurality of bumps 11 Ball 16; Wherein, this square cooling fin 14 has a square flat part 14a and the support part 14b that extends toward the direction of substrate 10 from the periphery of this flat part 14a, is bonded on the first surface 10a of substrate 10 by support part 14b, simultaneously A closed groove 17 is provided on the annular support portion 14b, and on the two opposite inner wall surfaces in the groove 17, there are respectively a plurality of protruding units 18 arranged at intervals, and the protrusions of the protruding units 18 are directed toward the side of the substrate 10 direction.
散热片14选用镀有镍的铜材料(Ni-Plated-Cu),且其平坦部14a具有约20至40密耳(mil)的厚度;同时,该镀镍铜材料的热膨胀系数也与常用的基板材料(例如环氧树脂、聚酰亚胺、BT树脂或FR4树脂等)相近,所以可使散热片14的支撑部14b与基板10间因温度变化而产生翘曲或脱层的可能性降至最低,其中,支撑部14b的高度可设计成10至40密耳(mil),其数值可根据芯片的厚度或配置层数而定;此外,该散热片14的平坦部14a是利用导热胶19粘接在芯片12的表面上,通过导热胶19将芯片12产生的热量传导至散热片14的平坦部14a并散逸出去。The
图1B所示即为上述散热片的仰视图,本实施例的散热片是一方形散热片14,如图所示,该环状支撑部14b上开设的封闭式凹槽17环绕成方形,且该凹槽17内的两个相对内壁表面上分别具有多个间隔排列的突起单元18,通过该突起单元18加强胶粘材料15对散热片14的粘着力;其中,该凹槽17如图2A所示,用现有方形冲压头21(Punch)冲制(Stamp)而成,以使其截面形状为方形,并分别具有两个平行相对的第一表面17a与第二表面17b,多个突起单元18则如图2B所示,用三角状的尖角冲压头22冲制形成,以使凹槽17的第一、第二表面17a、17b上分别按照预定形成多个间隔相对的单一突起毛刺(Burr),并使该毛刺18的突起朝向基板10的方向,因此,通过这种快速冲压法,即可简易且低成本地制出所需的散热片凹槽17与突起单元18。Figure 1B shows the bottom view of the above-mentioned heat sink. The heat sink of this embodiment is a
图3是散热片粘着在基板后的支撑部放大示意图,其中胶粘材料15预先敷设在基板10的第一表面10a与散热片14的支撑部14b接触的区域,并在受压后遭挤压填入支撑部14b的凹槽17中,在填充一定量后包覆于突起单元18的周围,再经烘烤(Baking)步骤固化,以利用突起单元18达到锁固(Locking)的功效,同时,利用凹槽17的第一、第二表面17a、17b上的突起单元18(如图1B所示)的间隔排列方式,可使胶粘材料15对散热片14的锁固力分布的更均匀,以增加其粘着强度,从而避免散热片14受震后脱落;一般来说,胶粘材料15的填充量越多,对散热片14的粘着性也将越好。本发明的设计中至少需使胶粘材料15在凹槽17内的填充高度高于图3所示的h-h线,使其充分包覆在多个突起单元18的周围,才可达到锁固散热片14的效果。3 is an enlarged schematic view of the supporting portion after the heat sink is adhered to the substrate, wherein the
因此,通过本发明的散热片14上的凹槽17与突起单元18的设计,即可在不改变基板10布局设计的情况下,提高散热片14的粘着力,以避免其受震脱落,同时,由于本发明的散热片14不是利用与芯片12间的接触关系定位,所以不会在后续高温工序中压迫芯片12,导致芯片12破裂;此外,由于凹槽17与突起单元18的设计如上述是用简易的冲压工序成形,所以仅需搭配适当的冲压头即可低成本地大幅量产,不会像现有的鸠尾槽或其它凹槽开设方式一样,耗费大量工序成本,可同时解决所有现有技术的难题。Therefore, through the design of the
实施例2Example 2
本发明的凹槽17与突起单元18设计并非限于上述实施例1,以各突起单元18间的位置排列关系而言,非仅限于图1B所示的间隔相对排列方式,如图4的散热片仰视图,即是其排列方式的另一实施例,其设计使突起单元形成两相对的整排式毛刺28,分别突起在方形凹槽17的第一、第二表面17a、17b上,使胶粘材料15填充在整排式毛刺28的周围,发挥均匀锁固散热片14的功能。The design of the
实施例3Example 3
按照突起单元的成形方式而言,也非仅限于上述用三角形冲压头22进行冲制,且突起单元的突起方向也非仅限于朝向基板10,如图5A、图5B所示的凹槽17表面,即是利用水平冲压头21,以刮制方式削除凹槽17的第一表面17a上的一层材料,制成图5B所示的凸缘毛刺38,同样可在胶粘材料15包覆于其周围后,发挥锁固散热片14的功能。According to the forming method of the protruding unit, it is not limited to punching with the triangular stamping head 22 mentioned above, and the protruding direction of the protruding unit is not limited to facing the
实施例4Example 4
突起单元的形式也非仅限于单一毛刺,也可用多段冲压的方式,制出具有多段突起的毛刺,如图6A、图6B、图6C所示的凹槽17表面,先用三角形尖角冲压头22冲制出一第一毛刺48a,再重复上述动作制出一第二毛刺48b,从而成为图6C所示具有第一毛刺48a与第二毛刺48b的双勾状毛刺48,这种实施例虽具有较高的工序成本,但其锁固作用比上述实施例要好,且使胶粘材料15与凹槽17表面具有较多的接触面积,可根据使用者的成本与粘着性需求而定。The form of the protrusion unit is not limited to a single burr, and multi-stage punching can also be used to produce a burr with multi-stage protrusions, such as the surface of the
上述各实施例都是以方形截面的凹槽17为例,事实上,凹槽的截面形状也非限于上述形状,如图7A、图7B,即是用尖角冲压头23取代上述的水平冲压头21,冲制出一V字型凹槽27,也同样可如图7B在其两个表面上分别形成突起单元18;图8A、图8B则是用圆形冲压头24冲制而成的半圆形凹槽37,同样可发挥本发明的功效。The above-mentioned embodiments all take the
除此,为达到散热片14的稳固粘着,关键在于突起单元18、28、38、48与胶粘材料15的包覆设计,而不是凹槽17、27、37的形式,因此,也可考虑将本发明的凹槽替换成其它设计,如图9A、图9B所示的实施例,即是将凹槽17替换成图示的方形开口40,该八个方形开口40如图9B的散热片14仰视图一样,分别开设在散热片支撑部14b的角缘或边缘上,其开口40内壁表面上也分别形成有突起单元18,以便在胶粘材料15分别填充入每一方形开口40后,均匀包覆在多个突起单元18的周围,并在烘烤固化后发挥锁固散热片14的功能。In addition, in order to achieve the firm adhesion of the
上述开口40的数量与开设位置并无一定限制,但是其位置具有一定的对称性比较好,以使胶粘材料15对散热片14的锁固力分布均匀,从而具有较好的粘着效果;同时,形成于开口40表面上的突起单元18也如上述各实施例,具有各种位置排列关系、成形方式与突起形式,可根据设计者的需求而定,该开口40的截面也非仅限于方形,也可利用不同的冲压头而制成V字型或圆形等其它形状。The number of
如前所述,达到散热片14的稳固粘着的关键是在于突起单元18、28、38、48与胶粘材料15的包覆设计,因此,也可考虑完全减省上述凹槽17、27、37或开口40的设计,如图10所示,直接在散热片14支撑部14b的内壁表面140b上形成多个突起单元18,也就是令突起单元18位列于散热片14包覆芯片12的容设空间141中,同样可达到相同的强化粘着效果,同时也可降低开设凹槽17、27、37或开口40的制造成本,更能满足量产的需要,但是在这种实施例中,至少需使胶粘材料15在容设空间141内的填充高度高于图标的h-h线,使其充分包覆在多个突起单元18的周围,以发挥其锁固功能;图10仅是以上述实施例1中的单一毛刺18为突起单元的说明,但是该突起单元也可为整排式毛刺28、凸缘毛刺38或双勾状毛刺48等各种实施方式。As mentioned above, the key to the stable adhesion of the
综上所述,本发明的具有散热片的半导体封装件,确具有稳固粘着散热片的功效,同时,其结构设计也不致造成对芯片与基板的破坏,进而可发挥其工序简单与成本低廉的优点,达到量产需求。In summary, the semiconductor package with heat sink of the present invention has the effect of stably adhering the heat sink, and at the same time, its structural design will not cause damage to the chip and substrate, and then it can play the advantages of simple process and low cost. Advantages, to meet mass production requirements.
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CN102683221B (en) * | 2011-03-17 | 2017-03-01 | 飞思卡尔半导体公司 | Semiconductor device and its assemble method |
CN104810328B (en) | 2014-01-28 | 2018-07-06 | 台达电子企业管理(上海)有限公司 | Package casing and the power module with the package casing |
CN104934399A (en) * | 2015-06-23 | 2015-09-23 | 日月光封装测试(上海)有限公司 | Semiconductor substrate and method for fabricating same |
TWI618911B (en) * | 2017-05-24 | 2018-03-21 | Excel Cell Electronic Co Ltd | Wafer packaging device and heat sink and heat sink manufacturing method thereof |
CN109037172B (en) * | 2017-06-12 | 2021-03-19 | 百容电子股份有限公司 | Packaging device of chip, heat dissipation member thereof and manufacturing method of heat dissipation member |
TWI706523B (en) * | 2019-09-02 | 2020-10-01 | 矽品精密工業股份有限公司 | Electronic package |
CN114823550B (en) * | 2022-06-27 | 2022-11-11 | 北京升宇科技有限公司 | Chip packaging structure and packaging method suitable for batch production |
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CN1387252A (en) * | 2001-05-21 | 2002-12-25 | 矽品精密工业股份有限公司 | Semiconductor package with heat dissipation structure |
CN2567778Y (en) * | 2002-06-18 | 2003-08-20 | 矽品精密工业股份有限公司 | Semiconductor package with heat dissipation structure |
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US5311402A (en) * | 1992-02-14 | 1994-05-10 | Nec Corporation | Semiconductor device package having locating mechanism for properly positioning semiconductor device within package |
US5926371A (en) * | 1997-04-25 | 1999-07-20 | Advanced Micro Devices, Inc. | Heat transfer apparatus which accommodates elevational disparity across an upper surface of a surface-mounted semiconductor device |
CN1387252A (en) * | 2001-05-21 | 2002-12-25 | 矽品精密工业股份有限公司 | Semiconductor package with heat dissipation structure |
CN2567778Y (en) * | 2002-06-18 | 2003-08-20 | 矽品精密工业股份有限公司 | Semiconductor package with heat dissipation structure |
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