CN100369243C - Semiconductor package with heat dissipation structure - Google Patents

Abstract

The semiconductor package with a heat dissipation structure of the present invention includes: a substrate having a first surface and an opposite second surface; at least one chip, which is arranged on the substrate and electrically connected with the substrate; a plurality of solder balls, which are arranged on the second surface of the substrate; the heat dissipation structure comprises a first heat dissipation sheet with at least one first positioning part and at least one second heat dissipation sheet with at least one second positioning part and one hollow part; the second radiating fin is connected with the surface where the substrate and the chip are connected, the first radiating fin is connected with the second positioning part of the second radiating fin through the first positioning part, and the chip is coated in a space formed by surrounding the hollow parts of the first radiating fin and the second radiating fin and the substrate, so that the semiconductor packaging piece which is low in cost, thin and good in radiating is formed through a radiating structure formed by stacking the radiating fins.

Description

Semiconductor package with heat dissipation structure

technical field

The invention relates to a semiconductor package with a heat dissipation structure, in particular to a semiconductor package with a heat dissipation structure which can reduce the cost and the height of the package.

Background technique

A flip-chip ball grid array (Flip-Chip Ball Grid Array, FCBGA) semiconductor package is a packaging structure that has both a flip chip and a ball grid array. Figure 17 is a cross-sectional view of an existing flip-chip package with a heat sink. , as shown in the figure, the package is such that the active surface (Active Surface) of at least one chip can be electrically connected to one surface of the substrate (Substrate) through a plurality of solder joints (Solder Bumps), and on the other surface of the substrate A plurality of solder balls (Solder Ball) used as input/output (I/O) terminals are planted on one surface; this packaging structure can greatly reduce the volume, and at the same time, the design of the existing wire (Wire) can be subtracted, which can reduce the Impedance, improve electrical quality, and avoid signal attenuation during transmission, so it has become the mainstream packaging technology for chips and electronic components.

Due to the superior characteristics of the flip-chip ball grid array package, it is mostly used in highly integrated multi-chip packages to meet the volume and computing requirements of this electronic component, but this type of electronic component is due to its high The frequency calculation characteristics make it generate more heat than ordinary packages during operation. Therefore, the quality of its heat dissipation effect becomes the key to the quality of this type of package; for the existing flip-chip ball grid array package In other words, it directly sticks the heat sink (Heat Sink) on the non-active surface (Non-active Surface) of the chip, without transferring heat through the poor thermal conductivity encapsulant (Encapsulant), thus forming a chip-adhesive - Heat sink - the direct heat dissipation path to the outside world, which has better heat dissipation effect compared with other heat dissipation methods.

For heat sinks with this type of packaging structure, as shown in Figure 18 in the prior art, the support portion 60b of the heat sink 60 is directly bonded to the substrate 62 with an adhesive material 61, and the flat portion 60a of the heat sink 60 is used for heat conduction. The glue 63 is bonded on the non-active surface 64a of the chip 64, and dissipates the heat of the chip 64 through the exposed flat portion 60a, such as the prior art such as U.S. Patent No. 5,311,402, No. 5,909,474, No. 5,909,057 or No. 5,637,920 patent, Both have disclosed this approximate structure, and gradually developed other ways of positioning the heat sink according to its positioning requirements, such as locking the supporting part of the heat sink on the substrate with bolts or other positioning elements, so as to strengthen the adhesion of the heat sink wait.

However, no matter how the related technology develops, and no matter how it changes the positioning method of the heat sink or how to improve its heat dissipation efficiency, the structural design of the flat part of the heat sink and its surrounding support parts has not changed all the time. In the chip package, the heat sink is covered on the substrate in the form of a cover, and the chip is covered by the accommodation space surrounded by the flat part of the heat sink and its surrounding support parts. Therefore, under the limitation of this structure, The cross-sectional shape of the heat sink must be designed as a concave shape as shown in FIG. 18 , and with the increase of the number of chips and the degree of integration, the volume of the accommodation space and the height of the package should be appropriately increased.

Therefore, the accommodating space design of the recess has gradually become a limitation on the improvement of this type of package, and has become a major obstacle to the development of today's package in the direction of high heat dissipation, low cost and small volume, and it is also the future development of this type of technology. There are obstacles that are difficult to overcome; the reason is that this kind of heat sink is made by forging (Forging), and the accommodation space on the forged heat sink forms a supporting part, such as shown in Figure 18A and Figure 18B For the square heat sink 60, a plate-shaped copper or aluminum material is first placed into a high-temperature mold, and impact force or pressure is applied within the forging temperature range, and then the square concave area 65 is forged out, and can be connected to the substrate 62 When covering the chip 64 in the recessed area 65, this manufacturing method is limited by the operation and equipment cost of the forging machine and the forging hammer (Forging Hammer), which forms a large load on the output, and also makes the manufacturing cost increase with the size of the heat sink. improved by changes.

In addition, due to the limited forming accuracy of the forging hammer, the thickness ratio (AspectRatio, t/T) of the heat sink has a certain upper limit as shown in Figure 18A and Figure 18B, and the total thickness T of the heat sink 60 cannot be reduced. To the height t close to the accommodation space 65, the current forging method can only make the maximum thickness ratio t/T about 0.5, that is, the total thickness T of the heat sink 60 will be affected by the height of the accommodation space 65 to be opened. t influence, if the required height t of accommodating the space 65 is increased to 1mm, then the plate-shaped material made of the heat sink 60 must have a thickness of 2mm at least before the forging process can be carried out; therefore, when the substrate 62 is connected When the thickness of the installed chip 64 or the number of stacks increases to increase the height t of the accommodating space 65 of the heat sink 60, the thickness T of the heat sink 60 obviously needs to be enlarged by an equal multiple, making it difficult to reduce the size of the overall package. The heat sink 60 does not conform to the development trend of light, thin and short, and gradually thickens with the height of the chip 64, which is not conducive to the heat dissipation of the chip 64, and seriously affects the heat dissipation performance of the package.

As shown in the cross-sectional view of the package in Figure 19, when the package adopts a double-chip stack structure, compared with the single-chip package, the overall thickness of the package is not only increased by the thickness of the added chip 66, but also the heat sink 60 is also Because the thickness of the plate is limited by the forging method, the overall thickness of the package increases significantly, which not only increases the cost of the heat sink, but also reduces the heat dissipation efficiency. At the same time, it is difficult to meet the small size development trend of the electronics industry.

In addition, the forging method is also limited by the type and size of the forging hammer, which makes the size and shape of the heat sink inflexible, making it difficult to change its shape and increase the heat dissipation area as required, as shown in Figure 20 The cross-sectional view of the package is to add fins 67 (Fin) on the flat part 60a of the heat sink to increase the contact area between the heat sink 60 and the outside world. It is formed directly above the flat part 60a, and cannot be designed in other directions, which in turn leads to a substantial increase in the thickness of the overall package; in addition, the package may also be shown in FIG. 21 by adding a passive component 68 on the substrate 62 (Passive Component) to improve the electrical performance of the package. At this time, the volume of the accommodating space 65 provided on the heat sink 60 needs to be slightly increased to accommodate the passive component 68. However, due to the forging hammer size of the forging method Due to the limitation of the heat sink 60, the size and shape of the heat sink 60 will not be changed arbitrarily according to the layout changes on the substrate 62, which may increase unnecessary areas and require batch manufacturing of a new size, resulting in gaps in circuit layout and design. contain.

At the same time, this existing manufacturing method uses the instantaneous stamping force of the forging hammer to forge the accommodation space of the heat sink at high temperature. The generation of residual stress (Residual Stress) will cause damage to the lattice composition of the copper or aluminum material. Therefore, after the subsequent reliability test or long-term use of the package connected to the heat sink, it may be as shown in Figure 22 It is shown that cracks 69 caused by residual stress appear at the junction of the flat portion 60a and the supporting portion 60b of the heat sink, and then the cracks extend to destroy the structure of the heat sink.

In addition, the disadvantages of the existing heat sink design and its manufacturing method are not limited to these. When the heat sink is placed on the substrate, it is adhered to the substrate through the support portion surrounding the flat portion, and the flat portion and the support The part is an integrally formed material. Therefore, when the package undergoes a subsequent high-temperature process, the thermal deformation of the flat part of the heat sink will be slightly larger than At this time, because the periphery of the flat part is bound by the support part, it will be difficult to release the thermal strain and cause the deformation as shown in Figure 23, so that the flat part 60a and the chip 64 or the thermally conductive glue 63 will have a delamination 70 and reduce the temperature. The heat dissipation performance even leads to delamination (not shown) between the supporting portion 60 b of the heat sink 60 and the substrate 62 , so that the heat sink 60 falls off when subjected to shock.

It can be seen that for the initial heat dissipation requirements of flip-chip packages, the heat sink design is indeed a suitable solution direction. However, as the electronics industry gradually moves towards high integration, high heat dissipation, low cost and small size, etc. With the development of the trend, this kind of heat sink has become the main obstacle to further development due to the limitation of its structure and manufacturing method. At the same time, it is limited to the bottleneck of the existing forging technology. If there is a problem, this creates a dilemma in industrial upgrading.

To sum up, how to develop a semiconductor package with a heat dissipation structure, so that the new heat dissipation structure does not need to be manufactured by forging, and there is no restriction on the thickness ratio, and at the same time, it can improve the heat dissipation efficiency and increase the flexibility of dimensional changes. And it will not cause stress concentration during the molding process, which is an urgent issue in the related research and development fields.

Contents of the invention

In order to overcome the above disadvantages of the prior art, an object of the present invention is to provide a semiconductor package with a heat dissipation structure that does not require a heat sink manufactured by a forging method and can reduce costs.

Another object of the present invention is to provide a semiconductor package with a heat dissipation structure that can reduce the height of the package.

Another object of the present invention is to provide a semiconductor package with a heat dissipation structure that does not have a thickness ratio limitation.

Another object of the present invention is to provide a semiconductor package with a heat dissipation structure that can increase the heat dissipation area to improve heat dissipation efficiency.

Another object of the present invention is to provide a semiconductor package with a heat dissipation structure that can avoid the stress concentration of the heat sink.

Another object of the present invention is to provide a semiconductor package with a heat dissipation structure that can avoid deformation or delamination of the package.

Another object of the present invention is to provide a semiconductor package with a heat dissipation structure that can improve the adhesion of the heat sink.

Yet another object of the present invention is to provide a semiconductor package with a heat dissipation structure that can increase the flexibility of changing the size and shape of the heat sink.

In order to achieve the above and other purposes, the semiconductor package with a heat dissipation structure provided by the present invention includes: a substrate having a first surface and a second surface opposite to it; at least one is placed on the first surface of the substrate and electrically connected to The chip of the substrate; a heat dissipation structure, including a first heat dissipation fin and a second heat dissipation fin, the first heat dissipation fin has a first positioning portion, and the second heat dissipation fin has at least one second positioning portion and at least one hollow portion; wherein , the second heat sink is placed on the first surface of the substrate, the first heat sink is placed on the second positioning portion of the second heat sink through the first positioning portion, and the chip is wrapped on the first heat sink, In the space surrounded by the hollow part of the second cooling fin and the substrate; and a plurality of solder balls planted on the second surface of the substrate.

The above-mentioned first heat sink and second heat sink are flat heat sinks, and the first heat sink is a top heat sink, and the second heat sink includes a bottom heat sink and at least one interlayer heat sink, formed on the surface The positioning parts on the top are stacked and positioned on the substrate; wherein, the heat sink and the positioning part are stamped by a low-cost stamping method (Stamp), and are respectively formed at the peripheral position of each heat sink, the first positioning part and the second positioning part The two positioning parts are respectively a combination of flanges and concave holes that can be fitted and positioned with each other.

In addition, the heat dissipation structure of the present invention can be implemented in various ways according to the requirements of the package. For example, the inner or outer edges of the first heat dissipation fin and the second heat dissipation fin can be aligned with each other after stacking, or can be aligned after stacking. The inner or outer edges of the interlayer heat sinks are misaligned. At the same time, when there are multiple interlayer heat sinks, the inner or outer edges of each interlayer heat sink can also be stacked on the bottom heat sink in a mutually aligned or mutually misplaced arrangement.

In addition, the area of the first heat sink can be enlarged as needed to improve the heat dissipation performance of the package, and a heat dissipation fan can be added on the first heat sink, or at least one build-up heat sink can be stacked, and the build-up heat sink can At least one hollow part is formed corresponding to the position of the chip to accelerate the heat dissipation of the chip.

A plurality of slots can also be opened by stamping method on the surface of the second heat sink in contact with the substrate, which can be filled with the adhesive material laid on the substrate to improve the adhesion of the second heat sink. The inner wall surface of the slot can be designed as Stepped surface or inclined surface to increase the adhesion area between the adhesive material and the slot, so as to prevent the heat sink from falling off after being shaken.

To sum up, since the cooling fins in the heat dissipation structure of the present invention are all stacked and designed in a flat plate shape, there is no concentration of residual stress inside; at the same time, since each of the stacked cooling fins The heat sinks have a very small thickness, and the number of stacked layers can also be changed according to the needs, so the heat dissipation structure is not limited by the thickness ratio (Aspect Ratio), and the height of the existing package can also be greatly reduced. Therefore, through the heat dissipation structure of the present invention, the existing heat sink and its forging method can be discarded, the development limitations of the existing heat sink space and the forging method are fully resolved, and the requirements of packaging technology for high integration, Demand for high heat dissipation, low cost and small size.

Description of drawings

1 is a cross-sectional view of Embodiment 1 of a semiconductor package with a heat dissipation structure of the present invention;

2A to 2C are schematic diagrams of the top heat sink, interlayer heat sink and bottom heat sink of Embodiment 1 of the present invention;

3A to 3C are schematic diagrams of the forming method of the first positioning part, the second positioning part and the third positioning part according to Embodiment 1 of the present invention;

4 is a sectional view of Embodiment 2 of the semiconductor package with heat dissipation structure of the present invention;

5 is a cross-sectional view of Embodiment 3 of the semiconductor package with heat dissipation structure of the present invention;

6 is a cross-sectional view of Embodiment 4 of the semiconductor package with heat dissipation structure of the present invention;

7 is a cross-sectional view of Embodiment 5 of the semiconductor package with heat dissipation structure of the present invention;

8A and 8B are cross-sectional views of Embodiment 6 of the semiconductor package with heat dissipation structure of the present invention;

9 is a cross-sectional view of Embodiment 7 of the semiconductor package with heat dissipation structure of the present invention;

10 is a cross-sectional view of Embodiment 8 of a semiconductor package with a heat dissipation structure of the present invention;

11A is a cross-sectional view of Embodiment 9 of the semiconductor package with heat dissipation structure of the present invention;

Fig. 11B is a schematic diagram of the interlayer heat sink shown in Fig. 11A;

12A is a cross-sectional view of Embodiment 9 of the semiconductor package with heat dissipation structure of the present invention;

Fig. 12B is a schematic diagram of the interlayer heat sink shown in Fig. 12A;

13 is a cross-sectional view of Embodiment 10 of the semiconductor package with heat dissipation structure of the present invention;

14A and 14B are cross-sectional views of Embodiment 11 of the semiconductor package with heat dissipation structure of the present invention;

Fig. 15 is a cross-sectional view of a package having another embodiment of a heat sink positioning portion of the present invention;

16A to 16C are schematic diagrams of the formation positions of another heat sink positioning part of the present invention;

17 is a sectional view of a conventional flip-chip package with a heat sink;

Fig. 18A is a schematic diagram of the square heat sink shown in Fig. 18;

Fig. 18B is a cross-sectional view of the square heat sink shown in Fig. 18A;

Fig. 19 is a cross-sectional view of a conventional flip-chip package with a double-chip stack structure;

20 is a sectional view of a conventional flip-chip package with heat dissipation fins;

Fig. 21 is a cross-sectional view of a conventional flip-chip package with passive components;

FIG. 22 is a schematic diagram of a crack in the heat sink of a conventional flip-chip package; and

FIG. 23 is a schematic diagram of the delamination of the heat sink of the conventional flip-chip package.

Detailed ways

Example 1

Fig. 1 is the cross-sectional view of the preferred embodiment of the semiconductor package with heat dissipation structure of the present invention, it is a flip-chip ball grid array package (FCBGA), including a substrate 10 as a chip carrier (ChipCarrier), through a bump 11 (Bump) electrically connected to the substrate 10 and placed on the chip 12 on the first surface 10a of the substrate 10, filled with an underfill (Under fill) insulating material 13 around the bump 11, placed on the first surface of the substrate 10 The bottom heat sink 20 on the surface 10a, a plurality of interlayer heat sinks 25 stacked on the bottom heat sink 20, the top layer heat sink 30 stacked on the topmost interlayer heat sink 25, and the second surface of the substrate 10 10b and a plurality of solder balls 14 electrically connected to a plurality of bumps 11; wherein, the bottom heat sink 20 is bonded on the substrate 10 by using the adhesive material 16 laid on the first surface 10a of the substrate, and the top heat sink 30 is bonded to the non-active surface 12a of the chip 12 through the thermally conductive adhesive 15 to dissipate the heat of the chip 12. At the same time, a plurality of interlayer heat sinks 25 and the bottom heat sink 20, as shown in FIG. 26 and the second hollow part 21 define a space on the substrate 10 by means of their stacking relationship, and wrap the chip 12 in a space surrounded by the top heat sink 30 , the first hollow part 26 , the second hollow part 21 and the substrate 10 in the accommodation space.

The top heat sink 30, the interlayer heat sink 25 and the bottom heat sink 20 are flat heat sinks as shown in Fig. 2A, Fig. 2B, and Fig. 2C respectively, and copper or aluminum materials coated with nickel are selected for use to exert their good thermal conductivity. At the same time, the coefficient of thermal expansion of this material is also similar to that of commonly used substrate materials (such as epoxy resin, polyimide, BT resin or FR4 resin, etc.), so it also causes warping between the bottom heat sink 20 and the substrate 10 due to temperature changes. Or the possibility of delamination is minimized; in addition, the thickness of each heat sink is all below 10 mils (mil), to bring into play the effect of thinning and high design flexibility of the present invention, the stacking quantity of interlayer heat sink 25 is then according to Depending on the thickness of the chip 12 or the number of layers, the top heat sink 30 can be evenly adhered to the non-active surface 12 a of the chip 12 .

As can be seen from Fig. 2B and Fig. 2C, the center of the interlayer heat sink 25 and the bottom heat sink 20 are respectively provided with a first hollow part 26 and a second hollow part 21, and the shapes of the first and second hollow parts 26, 21 are square , so that the edges of each hollow portion can be aligned with each other after they are stacked together, and a square space is surrounded on the substrate 10, and the chip 12 is wrapped in the space. At the same time, as shown in FIG. 2B, the interlayer heat sink 25 has two design sizes. When they are stacked with each other, the sandwiching pieces of this size and two sizes are stacked at intervals so that their outer edges are misaligned after stacking and are not aligned with each other, as shown in the cross-sectional view of Figure 1. Typically, the heat dissipation area is increased on each side around the package.

In addition, the four corners of the top heat sink 30, the interlayer heat sink 25 and the bottom heat sink 20 respectively have a first positioning part 32, a second positioning part 27 and a third positioning part 22, wherein the first positioning part 32 is a flange, and the second positioning portion 27 includes a concave hole and a flange corresponding to each other, the third positioning portion 22 is a hole, and the positions and sizes of the above-mentioned flanges, concave holes and holes correspond to each other, when When each cooling fin is stacked, it is mutually fitted and positioned and adhered to each cooling fin; therefore, as shown in the cross-sectional view of FIG. In the holes of the three positioning parts 22, each interlayer heat sink 25 is also stacked and positioned by the mutual fitting relationship between the flange of the second positioning part 27 and the concave hole, and finally, through the first positioning of the top heat sink 30 The flange of the part 32 fits in the concave hole of the second positioning part 27 of the top interlayer heat sink 25, that is, the stack positioning of the heat sink of the present invention is completed.

3A, FIG. 3B, and FIG. 3C show the forming methods of the first positioning portion 32, the second positioning portion 27, and the third positioning portion 22 respectively. (Punch) punch out the required positioning part, as shown in Figure 3C, punch out the hole 22a that runs through the heat sink 20 on the flat bottom heat sink 20 by the horizontal punch head 40, the size of the hole 22a is according to the punch head 40 Depending on the size, by passing through the hole 22a of the heat sink 20, the adhesive material 16 laid between the bottom heat sink 20 and the substrate 10 can also be pressed and filled into the hole 22a of the third positioning part 22, thereby strengthening the bottom layer The adhesiveness of heat sink 20; Simultaneously, Fig. 3B is to stamp the upper surface 25a of interlayer heat sink 25 with horizontal stamping head 40, make its upper surface 25a form the concave hole 27a that does not pass through heat sink 25, the material that is subjected to stamping is then pressed Extruded to form the flange 27b of the lower surface 25b of the heat sink, at this time, the position of the flange 27b will correspond to the position of the concave hole 27a, and its size can just fit in the hole 22a of the bottom heat sink 20; in addition, Fig. 3A 3B, by stamping the upper surface 30a of the top heat sink 30 with a horizontal stamping head 40, a group of corresponding flanges 32b and concave holes 32a can be formed on the top heat sink 30, and the flange 32b Fitted on the concave hole 27a of the top interlayer heat sink 25; it should be noted that since the top heat sink 30, the interlayer heat sink 25 and the bottom heat sink 20 need to be stacked on each other to be positioned on the substrate 10, so the first positioning Part 32, the second positioning part 27 and the third positioning part 22 need a certain precision in punching position, so as to stack and fit, make the first hollow part 26 and the second hollow part of the interlayer heat sink 25 and the bottom heat sink 20 The inner edge of the chip 21 can be properly aligned to enclose the chip 12 therein.

Through the above-mentioned stacked heat sink design and its stamping method, it is possible to avoid the recessed accommodation space of the existing heat sink formed in one piece, and it is not necessary to use forging manufacturing method, and it can be directly produced by low-cost stamping method. There is a heat dissipation structure with high design flexibility; at the same time, since each heat sink 20, 25, 30 of the stacked heat sink has a very small thickness, and the number of stacked layers can also be changed as required (changing the configuration of the interlayer heat sink 25 number), so the heat dissipation structure does not have a limitation on the thickness ratio (Aspect Ratio). As shown in Figure 1, the height T of the overall heat dissipation structure is close to the thickness t of the chip accommodation space, only slightly higher than The thickness of a top-layer heat sink 30 greatly reduces the height of the existing package, which can meet the thinning requirements of the package; in addition, the size or area of each heat sink can be arbitrarily changed according to the chip layout on the substrate 10, so as to maximize The effect of its high design flexibility may moderately improve the heat dissipation performance of the package; moreover, the heat dissipation fins 20, 25, and 30 in the heat dissipation structure of the present invention are all stacked and formed in a flat design without Other processing, so there is no concentration of residual stress inside, and there is no bound area that cannot be freely deformed after placement, so whether it is subjected to subsequent high-temperature processes or various reliability tests, it will not change due to ambient temperature The deformation or delamination fully solves all the shortcomings of the prior art.

Example 2

In addition to the above-mentioned embodiment 1, the heat sink configuration of the present invention also has other designs that can achieve the same effect. For example, the sectional view of embodiment 2 of the present invention shown in FIG. 25, but the inner edges of the first hollows 26 of the plurality of interlayer heat sinks 25 in the above-mentioned embodiment 1 are aligned with each other, so that the outer edges of the heat sinks are arranged in a misaligned manner, and the heat dissipation area on both sides of the package is increased. The design of this embodiment is The outer edges 25c of the plurality of interlayer heat sinks 25 are aligned with each other, and the inner edges 25d of the interlayer heat sinks 25 (that is, the edges of the first hollow portion 26) are mutually misaligned, and the inner edges of each interlayer heat sink 25 in this embodiment Although the edges 25d are arranged in a dislocation manner, each inner edge 25d can still enclose an accommodating space covering the chip 12 , and the inner edges 25d will not contact the two side surfaces of the chip 12 .

Example 3

Embodiment 3 of the present invention is a combination of Embodiment 1 and Embodiment 2 above. As shown in the cross-sectional view of FIG. The design also has better heat dissipation efficiency due to a larger heat dissipation area and more heat dissipation paths.

Example 4

Embodiment 4 of the present invention arranges the heat sinks of the above layers as shown in Figure 6 in cross-sectional view, so that each top heat sink 30, interlayer heat sink 25 and bottom heat sink 20 all have the same size, and make them stacked The inner and outer edges 25d, 25c are completely aligned to form a semiconductor package with a flat periphery, which can also exert the effect of the present invention.

Example 5

Figure 7 is a cross-sectional view of Embodiment 5 of the present invention, which increases the size of the top heat sink 30 to make its area much larger than that of the bottom layer and interlayer heat sinks 20, 25, so as to increase the heat dissipation surface and pass through the heat-conducting adhesive 15. Heat transfer improves the heat dissipation performance of the chip 12. There is no design limitation on the size or shape of the top heat sink 30, which is sufficient to fully meet the maximum demand for heat dissipation. Unlike the prior art, which is limited by the manufacturing process and cannot be changed The area of the surface of the heat sink does not need to be added to the existing heat dissipation fins, which is not conducive to the trend of thin packaging, so that the high design flexibility of the present invention can be fully utilized.

Example 6

In addition to the bottom layer, interlayer, and top layer heat sinks 20, 25, and 30 of the stacked heat sinks of the present invention, a plurality of build-up heat sinks 45 can also be stacked on the top layer heat sink 30 to further improve heat dissipation performance. Embodiment 6 As shown in FIG. 8A , the layer-building fins 45 are plate-shaped fins without hollows, and they are also arranged in a dislocation manner to increase the heat dissipation area; in addition, multiple layer-building fins 45 are also As shown in the cross-sectional view of FIG. 8B , a hollow portion 46 is provided in the center thereof, so that the central position 30c of the top heat sink 30 corresponding to the thermal conductive adhesive 15 (chip 12 ) exposes the hollow portion 46 of the build-up heat sink 45 , to accelerate the speed of heat dissipation of the chip 12.

Example 7

When the heat dissipation structure of the present invention is used in a package with stacked chips, its effect is better than that of the prior art. As shown in Figure 9, the cross-sectional view of Embodiment 7 of the present invention is a package with double-layer stacked chips. At this time, since the stacked heat dissipation structure has no thickness ratio restrictions, the thickness of the top heat sink 30 will not vary depending on the chip. The number of stacks increases and the thickness increases. At the same time, the interlayer heat sink 25 can also change the design of the hollow part 26 according to the size of the stacked chips, and change the shape of the accommodation space as shown in the figure, thereby shortening the heat transfer path of the top chip 120. .

Example 8

In addition, when other passive components are added on the substrate besides the chip, the design flexibility of the heat dissipation structure of the present invention can also be used to achieve the lowest material cost and the best heat dissipation effect. Figure 10 shows Embodiment 8 of the present invention, which changes the size of the hollow part 26 of the interlayer heat sink 25, so that the side area of the heat dissipation structure will not be increased too much due to the passive component 17, and the passive component 17 can also be sufficiently shortened. The heat dissipation path fully solves the problem of the existing heat sink.

Example 9

For a package with a multi-chip design, the heat dissipation structure design of the present invention can also be used to allow multiple chips to be accommodated in the accommodation space surrounded by the hollow part, such as the present invention shown in Figure 11A Embodiment 9 of the invention uses the interlayer heat sink 25 shown in Figure 11B to cover the two chips 12 with its large-area hollow part 26, but the design of the hollow part 26 is not limited to one, and can also be used as 12A and 12B, two hollow parts 26a, 26b are respectively provided on each interlayer heat sink 25 and the bottom heat sink 20 to accommodate the two chips 12 on the substrate 10 respectively, increasing the heat transfer path selection of the chips 12 , to achieve the effect of further improving the heat dissipation speed.

Example 10

In addition, the present invention can also be designed in embodiment 10 as shown in FIG. The forced heat dissipation fan 50 is used to exhaust the heat generated by the chip 12 , and the multiple paths formed by the multi-layer interlayer heat sink 25 can be used to accelerate heat dissipation.

Example 11

The heat dissipation structure of the present invention is not manufactured by the existing forging method, so in addition to the above-mentioned functions, other positioning mechanisms can also be provided on the bottom heat sink to solve the problem that the existing heat sink is easy to fall off after being shaken. Embodiment 11 is On the surface where the bottom heat sink 20 is in contact with the substrate 10, a slot 51 is punched out with a stamping head, so that the adhesive material 16 on the first surface 10a of the substrate is pressed and filled into the slot 51, and the slot 51 can be As shown in the cross-sectional view of Figure 14A, a stepped inner wall surface 51a is formed to increase the adhesion area between the adhesive material 16 and the bottom heat sink 20, and improve the adhesion of the heat sink 20, the groove 51 can also be shown in the cross-sectional view of Figure 14B , the tapered inclined inner wall surface 51b also has the effect of strengthening the adhesion of the heat sink 20 .

Each of the above-mentioned embodiments is based on the design of each layer of flat heat sink, and uses its positioning parts to stack each other to meet the functional requirements of different packages. However, the stacked positioning parts are only described in Example 1 as an example, not the present invention. The only implementation mode of the semiconductor package shown in Figure 15 (taking the structure of Embodiment 1 as an example), the punching direction of the positioning part is opposite to that of the above-mentioned embodiments, but it can also be used in each embodiment of the present invention Among them, the first positioning portion 52 formed on the corner edge of the top heat sink 30 is a hole 52a, and the second positioning portion 47 formed on the interlayer heat sink 25 includes a flange 47a and a concave hole 47b corresponding to each other, forming The third positioning portion 42 of the bottom heat sink 20 is a flange 42a, so as to correspond to each other, and can be fitted and positioned when the heat sinks are stacked; except for the equivalent embodiment of this positioning portion, it is not necessary to use forging All kinds of positioning mechanisms formed on the heat dissipation fins are also applicable to the heat dissipation structure of the present invention.

In addition, the positioning parts of the above-mentioned embodiments are all formed at the corner positions of the heat sinks. This position design can not only cooperate with the design of the hollow parts 26, 21 of the bottom heat sink 20 and the interlayer heat sink 25, but also make the heat sink The positioning force is more uniform and stable, but this position is not the only design of the present invention, as shown in Figure 16A, Figure 16B, and Figure 16C, the positioning parts 22, 27, 32 formed on the edges of the heat sinks 20, 25, 30, Approximate positioning effects can also be brought into play, and can also be used in the present invention.

In summary, the semiconductor package with heat dissipation structure of the present invention does provide a new type of heat dissipation structure, which does not need to be manufactured by forging, can reduce costs, and is not limited by the thickness ratio, and fully meets the thin profile of packaging technology. At the same time, the heat dissipation structure can also change the shape of the heat sink or increase its heat dissipation area according to needs, and can also avoid deformation and delamination, and fully take into account its adhesion stability, which has completely overcome all the above-mentioned existing technical bottlenecks.

Claims (22)

1. the semiconductor package part with radiator structure is characterized in that, this semiconductor package part comprises:

Substrate has a first surface and an opposing second surface;

At least one chip connects to put on the first surface of substrate and with substrate and electrically connects;

Radiator structure, comprise first fin and second fin, this first fin has at least one first location division, and this second fin has at least one second location division and at least one hollow-out parts, this first fin is a top layer fin, this second fin then comprises a bottom fin and at least one interlayer fin, wherein, second fin connects to be put on the first surface of substrate, first fin is borrowed first location division to connect and is put on second location division of second fin, and this chip is coated on this first fin, the hollow-out parts of second fin and substrate enclose in the space that is set to; And

A plurality of soldered balls connect and put on the second surface of substrate.

2. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this first fin and second fin are the tabular fin.

3. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this first location division is a flange, and second location division comprises a shrinkage pool and a flange.

4. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this first location division is a shrinkage pool, and second keeper comprises a flange and a shrinkage pool.

5. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this first location division and second location division form with the staking punch punching out respectively.

6. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this first location division and second location division are formed at the peripheral position of first fin and second fin respectively.

7. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this first fin aligns mutually with the edge of second fin.

8. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, the edge of this first fin and second fin is arranged in the dislocation mode.

9. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, when having a plurality of interlayer fin, it is that the mode storehouse that aligns mutually with the edge is on the bottom fin.

10. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, when having a plurality of interlayer fin, it is that mode storehouse with mutual dislocation is on the bottom fin.

11. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that the area of this first fin is greater than the area of second fin.

12. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this first fin not with surface that second fin contacts on, going back storehouse has at least one layer fin that increase.

13. the semiconductor package part with radiator structure as claimed in claim 12 is characterized in that, this increases on layer fin position that should chip is had at least one hollow-out parts.

14. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this radiator structure comprises that also one connects the radiator fan of putting on first fin surface.

15. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, has a plurality of flutings on the surface of this second fin and substrate contacts.

16. the semiconductor package part with radiator structure as claimed in claim 15 is characterized in that, the inner wall surface of this fluting is a ladder surface.

17. the semiconductor package part with radiator structure as claimed in claim 15 is characterized in that, the inner wall surface of this fluting is an inclined surface.

18. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this chip is the first surface electric connection by conductive projection and substrate.

19. the semiconductor package part with radiator structure as claimed in claim 18 is characterized in that, this semiconductor package part also comprises the insulating material that is filled in around this conductive projection.

20. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this semiconductor package part also comprises the heat-conducting glue of bonding first fin and chip.

21. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that this semiconductor package part also comprises the mucilage materials between the first surface that is filled in second fin and substrate.

22. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this semiconductor package part is the flip chip ball grid array semiconductor package part.

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