CN1280445A - Digital symbol timing recovery network - Google Patents

Abstract

A receiver for processing VSB modulated signals containing terrestrial broadcast high definition television information includes an input analog/digital converter (19) for generating a digital data stream. A symbol timing recovery and segment sync recovery network (24) generates a correctly timed sampling clock for the digitizer (19). The symbol timing recovery includes a phase detector (310) responsive to an output from a segment sync recovery generator (328), which in turn responds to an equalized signal from an adaptive channel equalizer (34) . A controlled oscillator (336) generates a sampling clock for the digitizer. The control network (340, 344, 348) shifts the frequency range of the oscillator to maintain the desired linear operation for enhanced symbol timing acquisition.

Description

Digital symbol timing recovery network

The invention relates to a digital symbol timing recovery network.

Recovery of data from a modulated signal carrying digital information in symbol form requires three functions at the receiver: timing recovery for symbol synchronization, carrier recovery (frequency demodulation to baseband), and channel equalization. Timing recovery is the process by which the receiver's clock (time base) is synchronized with the transmitter clock. This allows the received signal to be sampled at an optimal point in time, thereby reducing clipping errors associated with the decision-directed process of received symbol values. Carrier recovery is a process by which a received RF (radio frequency) signal, after being down-converted to a lower intermediate frequency band (e.g., near baseband), is frequency shifted to baseband so that the modulated baseband information can be recovered . Adaptive channel equalization is a process by which the effects of changing conditions and interference in the signal transmission channel are compensated. This process typically employs filters to remove amplitude and phase distortions due to the frequency-vs-time-varying characteristics of the transmission channel.

In accordance with the principles of the present invention, symbol timing recovery is enhanced by the cooperation of a symbol timing recovery network of segment sync detectors responsive to an output signal from a local channel equalizer.

Fig. 1 is a block diagram of a portion of a high definition television (HDTV) receiver including a timing recovery apparatus according to the principles of the present invention.

Figure 2 shows the data frame format of the VSB modulated signal according to the Grand Alliance (Grand Alliance) HDTV terrestrial broadcasting system in the United States.

Figure 3 shows the segment sync detector and symbol clock timing recovery network in Figure 1 in detail.

Figure 4 shows signal waveforms that are helpful in understanding the operation in Figure 3 .

In FIG. 1, an analog input HDTV signal for terrestrial broadcasting is provided by an input network 14 including a radio frequency (RF) tuning circuit and an IF processor 16 including a double-conversion tuner for producing an intermediate frequency (IF) output signal, and a suitable automatic gain control (AGC) control circuit to handle. In this embodiment, the received signal is a carrier-suppressed multi-level 8-VSB modulated signal proposed by the Grand Union and adopted in the United States. This VSB signal is represented by a one-dimensional constellation of data symbols, where only one coordinate contains the quantized data to be recovered by the receiver. In order to simplify the drawing, the signals determined for the functions shown are not shown.

As described in the Major League HDTV System Specification (April 14, 1994), the VSB transmission system uses a data frame format as shown in FIG. 2 to carry data. A small pilot signal at the suppressed carrier frequency is added to the transmitted signal to aid in carrier lock at the VSB receiver. Referring to FIG. 2, each data frame includes two fields, where each field includes 313 segments of 832 multilevel symbols. The first segment of each field is called the field sync segment, while the remaining 312 segments are called the data segment. Data segments typically contain MPEG compatible data packets. Each data segment consists of four symbol segment sync components followed by 828 data symbols. Each field component consists of a four-symbol segment sync component followed by a field sync component comprising a predetermined 511-symbol pseudo-random number (PN) and three predetermined 63-symbol PN sequences, said 511-symbol pseudo-random number sequence are inverted in successive fields. The last 63PN sequence is followed by a VSB mode control signal (defining the VSB symbol constellation size), which is followed by 96 reserved symbols and 12 symbols copied from the previous field.

Continuing with Figure 1, the passband IF output signal from unit 15 is converted by an analog/digital converter 19 into a digitally symbolic data stream. The output digital data stream from ADC 19 is demodulated by a demodulator/carrier recovery network 22 to baseband. This process is done by the phase locked loop in response to the small reference pilot carrier in the received VSB data stream. Unit 22 generates an output I-phase demodulated symbol data stream. Unit 22 may comprise the type described in the Grand Alliance System Specification, or in co-pending US Patent Application Serial No. 90/140257 (filed August 26, 1998 by T. J. Wang) a demodulator of the type described.

Associated with ADC 19 is a segment sync generator and symbol clock recovery network 24 in accordance with the present invention. The network recovers the repetitive data segment sync component from each data frame of the received random data. This segment sync is used to regenerate an appropriately phased clock, eg, 10.76 Msymbols/sec, which is used to control the sampling of data stream symbols by the analog/digital converter 19 . As discussed above in connection with FIGS. 3 and 4, network 24 uses a four-symbol correlation reference pattern and associated symbol data correlators to detect segment sync.

Unit 28 detects the data field sync component by comparing each received data segment with an ideal reference signal held in the receiver's memory. In addition to the field sync, the field sync signal also provides a training signal for the adaptive channel equalizer 34 . Unit 30 performs NTSC co-channel interference detection and rejection. The signal is then adaptively equalized by an adaptive equalizer 34 operating in closed and subsequent decision-directed modes. Equalizer 34 may be in the major league HDTV system specification and in W. The type described in "VSB Modem Subsystem Design for Grand Alliance Digital Television Receivers," by Bretl et al. (IEEE Transactions on Consumer Electronics, August 1995). Equalizer 34 can also be described in Shiue et al. co-pending US Patent Application No. Types described in 09/102885. The output of equalizer 34 advantageously aids in the operation of network 24 as will be described.

Equalizer 34 corrects for channel distortion, but phase noise rotates randomly around the symbol constellation. Phase tracking network 36 removes residual phase and gain noise in the output signal from equalizer 34, including phase noise not removed by the preceding carrier recovery network in response to the pilot signal. The phase corrected signal is then trellis decoded by unit 40, deinterleaved by unit 42, corrected for Reed-Solomon errors by unit 44, and dequantized by unit 46 using well known procedures. The decoded data stream is then subjected to audio, video and display processing by unit 50. The functional blocks of Fig. 1, except for the timing recovery network modified according to the principles of the present invention, can be used as described in the Grand Alliance HDTV System Specification (April 4, 1994) and in the aforementioned Bretl et al. circuits of the type described above.

The demodulation process in unit 22 is implemented by an automatic phase control (APC) loop to achieve carrier recovery using known techniques. The PLL uses a pilot component as a reference for initial acquisition, and an ordinary phase detector for phase acquisition. The pilot signal is embedded in the received data stream, which contains a pattern representing a similar random noise. Random data is basically ignored through the filtering process of the APC loop of the demodulator. The 10.76 Msymbol/sec input signal to ADC 19 is a near baseband signal with a VSB spectral center at 5.38 MHz and a pilot component at 2.69 MHz. In the demodulated data stream from unit 22, the pilot components are frequency shifted down to DC. The demodulated data stream is provided to a segment synchronization and symbol clock timing recovery network 24 as shown in detail in FIG. 3 . When repetitive data segment sync pulses are recovered from random data patterns in the received data stream, segment sync is used to achieve proper symbol timing by regenerating an appropriately phased symbol rate sampling clock to control the analog/ Sampling operation of digitizer 19.

Figure 4 shows a portion of an eight-level (-7 to +7) data segment with associated data segments for an 8-VSB modulated constellation broadcast signal according to the Grand Alliance HDTV specification. The segment sync is generated at the beginning of each data segment and occupies 4 symbol intervals. The segment sync is defined by a pattern 1-1-11 corresponding to the amplitude levels of the segment sync pulses from +5 to -5.

The four symbol segments are generated synchronously every 832 symbols, but because the data has a random, noise-like character, it is difficult to locate in the demodulated VSB digital data stream. In order to restore segment synchronization in this case, the demodulated I-channel data stream is provided to the input of a data correlator, and the reference pattern with 1-1-11 signature is provided to the input of the correlator for comparison with demodulated data for comparison. The correlator produces an enhancement for every 832 symbols that correspond to the reference pattern. The enhanced data events are accumulated by accumulators associated with the correlators. The interpolated random (unenhanced) correlation disappears relative to the enhanced correlation segment sync component. This procedure is well known. Networks for restoring segment synchronization in this manner are known, for example, from the Major League HDTV specification and from the aforementioned Bretl et al. paper.

Figure 3 shows the segment synchronization and timing recovery network 24 in detail. The output data stream from demodulator 22 is provided to a signal input of phase detector 310 and to switch 318 . Switch 318 can be programmed to carry either the output signal from demodulator 22 or the output signal from equalizer 34 to an 832 symbol correlator 320 on the segment sync recovery path. The other signal input of phase detector 310 receives the output signal from segment sync generator 328 on the segment sync recovery path including correlator 324 . Correlative reference pattern generator 330 is connected to correlator 320 , and segment integrator and accumulator 324 . Reference pattern generator 330 provides a 1-1-11 segment synchronous reference pattern (see FIG. 4).

The output from correlator 320 is integrated and accumulated by unit 324 . Segment sync generator 328 includes a comparator having a predetermined threshold and responds to the output of unit 324 by generating segment sync components at appropriate times in the data stream corresponding to segment sync intervals. This occurs when the accumulation of enhanced data events (generation of segment syncs) exceeds a predetermined threshold. The generation of the segment sync component indicates that the signal has been captured. The event is indicated by data held in registers of generator 328 . This register is monitored by controller 344 to determine whether signal capture has occurred, as described above.

Phase detector 310 performs a timing recovery function. Phase detector 310 compares the phase of the segment sync generated by unit 328 with the phase of the segment sync present in the demodulated data stream from unit 22 and produces an output error signal indicative of symbol timing error. The error signal is low pass filtered by automatic phase control (APC) filter 334 to produce a signal suitable for controlling a 10.76 MHz voltage controlled crystal oscillator (VCXO) 336 . Oscillator 336 provides a 10.76 MHz symbol sampling clock to ADC 19 . The sampling clock exhibits correct timing when the phase error signal is substantially zero through the operation of the APC, indicating that the symbol timing (clock) recovery is complete. The segment sync generated by unit 328 is also provided to other decoding circuits and automatic gain control (AGC) circuits (not shown). The output of filter 334 is provided to the input of detector 340 . An output 331 of the sync generator 328 , which indicates whether the signal lock (capture) has been completed, is provided to an input of the microcontroller 344 .

Switch 318 is optional, but can be programmed to carry either the output of demodulator 22 or the output of equalizer 34 to correlator 320 on the sync recovery path. In the illustrated preferred embodiment, switch 318 is programmed to continuously connect the output of adaptive equalizer 34 to correlator 320 . In another system with different operating requirements, for example, switch 318 could be programmed to initially connect the output of demodulator 322 to correlator 320 when the system is first powered up or reset, and subsequently in a The output of equalizer 34 is connected to correlator 320 after a predetermined event interval.

In the preferred embodiment of FIG. 3, initially, when the system is first powered on or after the system is reset, the VCO 336 is set to run at a predetermined stable frequency. In this instance, the frequency corresponds to an extreme (maximum or minimum) frequency value within the predetermined frequency range. This initial frequency deviates significantly from the desired symbol timing frequency or multiples thereof because it has been observed that the equalizer 34 can converge faster by using such an initial frequency than using very close to the desired timing frequency in the blind mode of operation. . With the equalizer output connected to correlator 320 via switch 318, equalizer 34 is reset and allowed to converge in a predetermined (programmed) amount of time, eg 50 ms. The time interval is chosen corresponding to the time required for the equalizer to operate sufficiently stably. This time interval can be determined empirically based on the requirements of a particular system. At this point, when equalizer operation has stabilized, the phase control network comprising elements 320, 324, 328 and 310 is reset and allowed to control the operation of oscillator 336 via filter 334 and oscillator 336 control voltage input 349. Oscillator 336 is started from the initial (reset) predetermined frequency condition described above.

The described control mechanism improves the performance of the timing recovery network because channel impairments such as multipath patterns of its input data are significantly reduced or eliminated by the equalizer 34 . Specifically, the timing recovery mechanism improves the network's ability to acquire and maintain signals under strong multipath conditions. The ability of the disclosed apparatus to recover segment synchronization under adverse conditions such as multipath enhances the speed and accuracy of the symbol timing recovery process.

Adaptive equalizer 34 operates in a blind mode using a well-known blind equalization algorithm such as the constant modulus algorithm (CMA) when signal acquisition is started. After a period of, eg, 50 ms, the output of the equalizer is considered good enough to contribute to the segment synchronization and timing recovery process for generation of a proper sampling clock by oscillator 336 . After the symbol timing and proper sampling clock of ADC unit 19 have been established, network 24 continues to receive an equalized output signal from equalizer 34 to improve tracking performance under eg strong multipath signal conditions. At this point, equalizer 34 typically operates in a steady-state decision-directed mode.

According to a feature of the arrangement of FIG. 3 , a DC control voltage 349 from unit 348 is used to shift the operating frequency range of oscillator 336 . This is accomplished by a network comprising detector 340 , microcontroller 344 and level shifter 348 . The network improves symbol acquisition performance and frequency acquisition performance described below. The detector monitors the steady state operating condition of the oscillator 336 essentially by sensing a predetermined DC level at the output of the filter 334 . The sync generator 328 provides an output signal 331 which is the signal capture that has been achieved. The controller 344 is responsive to the output signal from the detector 340 and to the output signal 331 from the sync generator 328 to cause the level shifter 348 to generate a control voltage 349 which causes the oscillator to shift its operating frequency range until reaching A steady-state operating frequency. The signal acquisition process is repeated each time the oscillator is moved across the operating frequency range. Repeating the signal acquisition process includes resetting the network elements and setting the VCO 336 to operate at a predetermined initial frequency, as described above.

A voltage-controlled crystal oscillator (VCXO), such as that used by oscillator 336, has a limited frequency range in which the oscillator can have a stable, linear, control voltage-to-output-frequency transfer function, or response curve relationship to work. To increase this linear operating frequency range, the DC control voltage 349 from unit 348 shifts the oscillator transfer function to a different frequency range without changing the desired linearity characteristics if signal acquisition is not achieved within a given time. The frequency range shift capability adjusts the oscillator steady state operating voltage relative to the correct steady state frequency to produce more reliable symbol timing capture.

The configuration of detector 340, microcontroller 344, and level shifter 348 allows for a wider frequency range than is possible in conventional configurations without these elements (i.e., oscillator 336 is controlled solely by the output of filter 334) within to capture symbol timing. In conventional configurations, if the frequency range produced by the oscillator in response to the output of filter 334 does not include the actual symbol frequency of the received symbol, the timing loop will not lock and the samples provided by ADC 19 will suffer. Furthermore, the linear response of the oscillator frequency to the control voltage may deteriorate as the control voltage deviates from its median value. This effect may lead to poor acquisition performance of the timing recovery network when steady state oscillator operation requires the frequency control voltage (from filter 334) to be close to its extreme value (maximum or minimum). The network comprising elements 340, 344, and 348 significantly reduces or eliminates these performance degradations.

The microcontroller 344 maintains the current operating condition when the control signal from the detector 340 and the generator 328 that the received signal has been correctly captured, but moves up and down via the unit 348 when the signal is not captured within a predetermined time Oscillator 336 frequency range.

When the operation of the microcontroller 344 is initialized, for example after being reset, the controller 344 causes the level shifter 348 to output a predetermined, standard DC voltage according to the parameters of the oscillator 336 and the operating parameters of the overall system. This normalized control voltage causes oscillator 336 to center its control voltage to output frequency transfer function at its normalized position. Symbol timing recovery is then attempted via the elements 320 , 324 , 328 and 330 in question. If the recovery process fails because the actual symbol timing frequency is above the oscillator's current frequency range, the controller 344 will direct the unit 348 to generate a different control voltage, resulting in a different frequency covered by the oscillator control voltage versus frequency response scope. This new frequency range may include the actual symbol timing frequency. If signal acquisition is not achieved within a predetermined "time-out" period, the frequency range is shifted. As described above, the controller 344 monitors the output sum of the filter 334 and a register in the sync generator 328 to determine whether signal acquisition has been achieved, i.e., by synchronizing with the segment sync interval recovered by the generator 328 proven. If signal recovery is not achieved during the "time out" period, select a different oscillator frequency and repeat the signal acquisition process as described above. If, after a predetermined time, the output of filter 334, which is oscillator 336, is in a steady state operating condition and the control voltage indicates that segment synchronization has been restored, the frequency range will not shift.

In another embodiment, failure to acquire a signal may be indicated by a high error output from Reed-Solomon error detection and correction unit 44 ( FIG. 1 ), which may be monitored by microcontroller 344 . When the Reed-Solomon error detector indicates negligible error in performance, the signal is captured and the oscillator operation will remain unchanged.

When symbol timing is first acquired for a particular channel, the symbol timing frequency is unknown. Although the transmitter and receiver symbol frequencies should be the same, significant variations can occur at the receiver. In this example, after each signal capture failure, a predetermined search command, or algorithm, will be implemented by the controller 344 to determine the next intermediate control voltage to use, ie, greater or less than the initial value. For example, in a simple example, level shifter 348 provides only two available control voltages in response to instructions from controller 344 . The first time is to use the initial, or default, control voltage. If the attempt to achieve timing lock fails, the second control voltage and associated frequency range will be used in response to instructions from the controller 344 . In more complex systems, the level shifter 348 can provide three or more control voltages and associated frequency ranges.

After the channel symbols have been captured for the first time, detector 340 compares the steady state voltage from filter 344 to a local reference voltage representing the optimum voltage within a small predetermined operating range. Controller 344 maintains in memory the direction in which the oscillator voltage to frequency transfer function should be adjusted to place the control voltage from unit 348 close to a predetermined optimum value. Controller 344 uses this control voltage value as the default value the next time the channel is acquired.

The shifting operation described advantageously extends the range of symbol frequencies that can be acquired. Also, the best estimate can be used after the first acquisition, rather than starting the search for the best oscillator control voltage vs. frequency centered voltage at the same point when a channel was acquired. In addition, the oscillator control voltage is moved towards its optimal value for capture, eliminating the dependence on the accuracy of the time symbol timing frequency and the effect on the oscillator voltage due to implementation tolerances such as component value tolerances. changes in frequency response.

Claims (6)

1. Apparatus in a system for processing a received data stream comprising an image representation signal, the apparatus comprising: a synchronization recovery network for generating a recovered synchronization component in response to the received signal; a symbol timing recovery network for generating a symbol timing signal in response to the received signal and in response to the recovered synchronization component; a channel equalizer (34) for generating an equalized signal in response to the received signal; wherein The synchronization recovery network is additionally responsive to the equalized signal. 2. The apparatus of claim 1, wherein said received signal comprises a vestigial sideband (VSB) modulated signal comprising high definition video data represented by a constellation of symbols, having a data frame format consisting of successive data frames said data includes a field sync component preceding a plurality of data segments having associated segment sync components; and The recovered sync components are said segment sync components. 3. The apparatus of claim 2, further characterized in that an input network comprising an analog/digital converter is responsive to said received signal and to a sampling timing signal, and a demodulator is responsive to output from said converter signal to produce a demodulated signal; and a channel equalizer responding to said demodulated signal to generate an equalized signal; wherein, said synchronization recovery network generates said synchronization component in response to said demodulated signal and additionally in response to said equalized signal; and The symbol timing recovery network generates the sampled timing signal in response to the demodulated signal and in response to the recovered synchronization component. 4. 2. The apparatus of claim 1, wherein said equalized signal is generated by said equalizer operating in a blind mode. 5. A method for processing a received data stream comprising an image representation signal, characterized in that it comprises the steps of: performing channel equalization on the received signal; recovering the synchronous component of the received signal in response to the equalized signal produced by said equalizing step; and A symbol sampling timing signal is generated in response to the recovered sync component produced by said recovering step. 6. The method of claim 5, wherein said received signal comprises a vestigial sideband (VSB) modulated signal comprising high definition video data represented by a constellation of symbols, having a data frame format consisting of successive data frames said data includes a field sync component preceding a plurality of data segments having associated segment sync components; and The recovered sync components are said segment sync components.

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