CN119584624A - Metal oxide semiconductor field effect transistor and preparation method thereof - Google Patents
Metal oxide semiconductor field effect transistor and preparation method thereof Download PDFInfo
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Abstract
本申请公开了一种金属氧化物半导体场效应管及其制备方法，所述金属氧化物半导体场效应管包括依次层叠的漏极金属层、衬底、第一外延层、第二外延层、介质层和源极金属层；第一外延层的上表面包括间隔设置的第一掩埋区；第二外延层包括间隔设置的离子注入层、沟槽区和第二掩埋区；沟槽区包括第一栅极氧化层、第一栅极区、第二栅极氧化层和第二栅极区；第一栅极区、第二栅极氧化层和第二栅极区形成分裂栅结构；介质层包括目标开口，目标开口中填充有接触金属。本申请实施例可以降低金属氧化物半导体场效应管的动态损耗，并提高金属氧化物半导体场效应管的可靠性。
The present application discloses a metal oxide semiconductor field effect transistor and a preparation method thereof, wherein the metal oxide semiconductor field effect transistor comprises a drain metal layer, a substrate, a first epitaxial layer, a second epitaxial layer, a dielectric layer and a source metal layer stacked in sequence; the upper surface of the first epitaxial layer comprises a first buried region arranged at intervals; the second epitaxial layer comprises an ion implantation layer, a groove region and a second buried region arranged at intervals; the groove region comprises a first gate oxide layer, a first gate region, a second gate oxide layer and a second gate region; the first gate region, the second gate oxide layer and the second gate region form a split gate structure; the dielectric layer comprises a target opening, and the target opening is filled with a contact metal. The embodiments of the present application can reduce the dynamic loss of the metal oxide semiconductor field effect transistor and improve the reliability of the metal oxide semiconductor field effect transistor.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a metal oxide semiconductor field effect transistor and a preparation method thereof.
Background
Silicon Carbide (SiC) power trench gate metal oxide semiconductor field effect transistor (U-trench MOSFET) has a low on-resistance and a high channel density due to characteristics such as a high density of cell size and high mobility of a nonpolar surface, and has a wide application prospect.
At present, in the field of power electronics, such as photovoltaic inversion, motor driving, direct Current (DC) -DC conversion, and other application scenarios, a PN body diode needs to be parasitic inside a SiC UMOSFET, so that the PN body diode is used as a reverse recovery diode to form a complete Current path.
However, at present, a parasitic PN-type body diode in the SiC UMOSFET can generate higher dynamic loss, and under the condition that the SiC UMOSFET is in a reverse blocking state, two-dimensional electric field aggregation can exist at the corner of a groove in the SiC UMOSFET, so that the electric field intensity at the bottom of the groove is higher, and the reliability of the device is further reduced.
Disclosure of Invention
The embodiment of the application aims to provide a metal oxide semiconductor field effect transistor and a preparation method thereof, which can solve the problems of high dynamic loss and low reliability of a silicon carbide power trench gate metal oxide semiconductor field effect transistor of an internal parasitic body diode in the related technology.
In a first aspect, an embodiment of the present application provides a metal oxide semiconductor field effect transistor, where the metal oxide semiconductor field effect transistor includes a drain metal layer, a substrate, a first epitaxial layer, a second epitaxial layer, a dielectric layer, and a source metal layer that are sequentially stacked;
The upper surface of the first epitaxial layer comprises first buried regions which are arranged at intervals;
The second epitaxial layer comprises an ion implantation layer, a groove region and a second buried region which are arranged at intervals, wherein the ion implantation layer extends from the upper surface of the second epitaxial layer to the inside of the second epitaxial layer along the direction of the thickness of the metal oxide semiconductor field effect tube;
The trench region comprises a first gate oxide layer, a first gate region, a second gate oxide layer and a second gate region, wherein the first gate oxide layer is laminated on the inner wall of the trench region, and the first gate region, the second gate oxide layer and the second gate region are laminated on the upper surface of the first gate oxide layer in sequence along the direction from the first epitaxial layer to the second epitaxial layer to form a split gate structure;
The dielectric layer comprises a target opening, wherein contact metal is filled in the target opening and used for connecting the second epitaxial layer and the source electrode metal layer.
Optionally, the width of the first gate region is less than or equal to the width of the second gate region, and the width of the first gate region and/or the second gate region is 0.5 μm to 1 μm.
Optionally, the thickness of the first gate region and/or the second gate region is 0.5 μm to 1.5 μm.
Optionally, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.
Optionally, the thickness of the second gate oxide layer is 0.05 μm to 0.12 μm.
Optionally, a minimum value of an included angle between the sidewall of the trench region and the lower surface of the second epitaxial layer is 85 ° to 89 °.
Optionally, the depth of the trench region is 2 μm to 3 μm and the width of the trench region is 0.5 μm to 1.2 μm.
Optionally, the target opening includes a first opening corresponding to the ion implantation layer and a second opening corresponding to a spacing region between the ion implantation layers;
The contact metal comprises an ohmic contact metal and a Schottky contact metal, the first opening is filled with the ohmic contact metal, and the second opening is filled with the Schottky contact metal.
Optionally, the thickness of the ohmic contact metal and/or the schottky contact metal is less than or equal to the thickness of the dielectric layer.
Alternatively, the ohmic contact metal has a thickness of 60nm to 200nm and a width of 0.2 μm to 0.5 μm.
Alternatively, the schottky contact metal has a thickness of 0.2 μm to 0.6 μm and a width of 0.3 μm to 0.8 μm.
In a second aspect, an embodiment of the present application provides a method for preparing a metal oxide semiconductor field effect transistor, where the method includes:
forming a first epitaxial layer and a second epitaxial layer which are sequentially stacked on the upper surface of a substrate, wherein the upper surface of the first epitaxial layer comprises first buried regions which are arranged at intervals;
performing first ion implantation operation on a first target area on the upper surface of the second epitaxial layer to obtain ion implantation layers which are arranged at intervals;
Etching the second epitaxial layer along the longitudinal center line of the ion implantation layer to obtain a target groove penetrating through the ion implantation layer;
Performing a second ion implantation operation on the bottom of the target trench to form a second buried region in the second epitaxial layer, the second buried region being in contact with the bottom of the target trench;
Sequentially preparing a first gate oxide layer, a first gate region, a second gate oxide layer and a second gate region in the target trench to obtain a trench region, wherein the first gate oxide layer is laminated on the inner wall of the trench region, and the first gate region, the second gate oxide layer and the second gate region are sequentially laminated on the upper surface of the first gate oxide layer along the direction from the first epitaxial layer to the second epitaxial layer to form a split gate structure;
Preparing an original dielectric layer on the upper surface of the second epitaxial layer with the groove area;
Preparing a target opening in a second target area of the original dielectric layer, and filling contact metal into the target opening to obtain a dielectric layer;
and preparing a source metal layer on the upper surface of the dielectric layer, and preparing a drain metal layer on the lower surface of the substrate to obtain the metal oxide semiconductor field effect transistor according to any one of the above.
According to the metal oxide semiconductor field effect transistor provided by the embodiment of the application, the trench region is introduced into the second epitaxial layer, the first gate region, the second gate oxide layer and the second gate region in the trench region are sequentially stacked along the direction from the first epitaxial layer to the second epitaxial layer to form the split gate structure, the split gate structure is utilized to divide the gate in the metal oxide semiconductor field effect transistor into two parts, so that the gate drain capacitance of the gate is reduced, and the gate drain capacitance is positively correlated with the switching loss of the metal oxide semiconductor field effect transistor, the dynamic loss of the metal oxide semiconductor field effect transistor can be reduced, and further, under the condition that the metal oxide semiconductor field effect transistor is in a reverse blocking state, the first gate region and the source metal layer at the lower part of the split gate structure are connected with low potential, the PN junction of the body diode formed by the ion implantation layer and the second epitaxial layer is connected with the depletion region formed by the first buried region arranged in the first epitaxial layer, the first gate region can be promoted to be connected with the depletion region formed by the first buried region, the gate region in the metal oxide semiconductor field effect transistor can be more uniformly distributed, the bottom of the trench field effect transistor can be inhibited, and the field effect concentration of the bottom of the trench field effect transistor can be further reduced, and the field effect concentration of the field effect transistor can be further reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
Fig. 1 is a schematic cross-sectional view of a mosfet according to an embodiment of the present application;
Fig. 2 is a flow chart of steps of a method for fabricating a mosfet according to an embodiment of the present application;
FIG. 3 is a schematic diagram showing a cross-sectional structure of a MOSFET according to an embodiment of the present application;
Fig. 4 is a schematic diagram of a cross-sectional structure of a mosfet according to an embodiment of the present application;
fig. 5 is a schematic cross-sectional view of a mosfet according to an embodiment of the present application;
fig. 6 is a schematic diagram showing a cross-sectional structure of a mosfet according to an embodiment of the present application;
fig. 7 is a schematic diagram showing a cross-sectional structure of a mosfet according to an embodiment of the present application;
fig. 8 is a schematic diagram of a cross-sectional structure of a mosfet according to an embodiment of the present application;
fig. 9 is a schematic diagram illustrating a cross-sectional structure of a mosfet according to an embodiment of the present application;
Fig. 10 is a schematic diagram showing a cross-sectional structure of a mosfet according to an embodiment of the present application;
fig. 11 is a schematic cross-sectional view of a mosfet according to an embodiment of the present application.
Reference numerals illustrate:
10-cell, 11-drain metal layer, 12-substrate, 13-first epitaxial layer, 131-first buried region, 14-second epitaxial layer, 141-ion implantation layer, 1411-second ion implantation layer, 1412-first ion implantation layer, 142-trench region, 1421-first gate oxide layer, 1422-first gate region, 1423-second gate oxide layer, 1424-second gate region, 143-second buried region, 15-dielectric layer, 151-target opening, 1511-first opening, 1512-second opening, 15-1-original dielectric layer, 16-source metal layer, 01-target trench.
Detailed Description
The technical solutions of the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present application, fall within the scope of protection of the present application.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
Product examples
The silicon carbide diode provided by the embodiment of the application is described in detail below through specific embodiments and application scenes thereof with reference to the accompanying drawings.
Referring to fig. 1, a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor according to an embodiment of the present application is shown, wherein the schematic cross-sectional structure of the metal oxide semiconductor field effect transistor is a schematic cross-sectional structure along a thickness direction of the metal oxide semiconductor field effect transistor, and the metal oxide semiconductor field effect transistor according to the embodiment of the present application includes at least two cells 10, and each cell 10 is in a parallel relationship after a voltage is applied to the metal oxide semiconductor field effect transistor.
As shown in fig. 1, the metal oxide semiconductor field effect transistor includes a drain metal layer 11, a substrate 12, a first epitaxial layer 13, a second epitaxial layer 14, a dielectric layer 15, and a source metal layer 16, which are sequentially stacked.
Wherein the upper surface of the first epitaxial layer 13 includes first buried regions 131 arranged at intervals.
The second epitaxial layer 14 includes an ion implantation layer 141, a trench region 142 and a second buried region 143 which are disposed at intervals, the ion implantation layer 141 extends from an upper surface of the second epitaxial layer 14 to an inside of the second epitaxial layer 14 in a direction in which a thickness of the metal oxide semiconductor field effect transistor is located, and the trench region 142 penetrates the ion implantation layer 141 along a longitudinal center line of the ion implantation layer 141 and extends to the second buried region 143.
The trench region 142 includes a first gate oxide layer 1421, a first gate region 1422, a second gate oxide layer 1423 and a second gate region 1424, wherein the first gate oxide layer 1421 is laminated on the inner wall of the trench region 142, and the first gate oxide layer 1422, the second gate oxide layer 1423 and the second gate region 1424 are laminated on the upper surface of the first gate oxide layer 1421 in sequence along the direction from the first epitaxial layer 13 to the second epitaxial layer 14 to form a split gate structure.
The dielectric layer 15 includes a target opening 151, the target opening 151 being filled with a contact metal for connecting the second epitaxial layer 14 and the source metal layer 16.
Specifically, the drain metal layer 11 may include any one of nickel (Ni), titanium (Ti), and titanium-nickel alloy, and copper (Cu) aluminum (Al) alloy. In some embodiments, the thickness of the drain metal layer 11 is 0.5 μm to 1.5 μm, for example, the thickness of the drain metal layer 11 may be in the range of one or any two of 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, and 1.5 μm. In the embodiment of the application, the drain metal layer 11 is used as a back metal electrode layer connected with the substrate 12, so that good electrical contact is provided for the metal oxide semiconductor field effect transistor, and current can be ensured to smoothly pass through the metal oxide semiconductor field effect transistor.
The substrate 12 is an N-type heavily doped (N+) silicon carbide substrate, the substrate 12 can be any one of a 4H-SiC single crystal substrate, a 6H-SiC single crystal substrate and a 3C-SiC single crystal substrate, the substrate 12 is used as a bottom material of the whole metal oxide semiconductor field effect transistor, physical support is provided for the metal oxide semiconductor field effect transistor, the structural integrity of the metal oxide semiconductor field effect transistor is ensured, and in addition, the silicon carbide substrate has excellent heat conduction and electric conduction performance, so that the substrate 12 can effectively conduct out heat generated inside the metal oxide semiconductor field effect transistor, and meanwhile, the uniformity of current distribution in the metal oxide semiconductor field effect transistor is improved. Wherein the thickness of the substrate 12 is from 100 μm to 150 μm, e.g., the thickness of the substrate 12 is in the range of one or any two of 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, and 150 μm.
The first epitaxial layer 13 is stacked on the upper surface of the substrate 12, and the upper surface of the first epitaxial layer 13 away from the substrate 12 includes at least two first buried regions 131 spaced apart from each other, and the first buried regions 131 are equally spaced apart from each other, and it is understood that the spacing between the first buried regions 131 refers to the minimum distance between two adjacent first buried regions 131 in the upper surface of the first epitaxial layer 13. The spacing between the first buried regions 131 may be 1 μm to 3 μm.
Wherein the first epitaxial layer 13 is an N-type lightly doped (N-) silicon carbide epitaxial layer, the thickness of the first epitaxial layer 13 is from 4 μm to 10 μm, and in some embodiments, the thickness of the first epitaxial layer 13 may be in the range of one or any two of 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, and 10 μm.
The first buried region 131 is a P-type heavily doped (p+) region, and the depth of the first buried region 131 is smaller than the thickness of the first epitaxial layer 13.
In the embodiment of the application, the first buried regions 131 with equal spacing on the upper surface of the first epitaxial layer 13 can increase the voltage withstanding capability of the metal oxide semiconductor field effect transistor, and adjust the electric field uniform distribution in the metal oxide semiconductor field effect transistor, so that the depletion regions of the first doped regions are connected under the condition of applying reverse bias voltage to the metal oxide semiconductor field effect transistor, the schottky region above the metal oxide semiconductor field effect transistor is shielded, the electric field intensity at the corners of the lower part of the trench region 142 and the electric field intensity at the schottky contact position are reduced, and the reliability of the metal oxide semiconductor field effect transistor in application fields such as high temperature, high field and the like is improved.
Referring to fig. 1, the second epitaxial layer 14 is stacked on the upper surface of the first epitaxial layer 13, and the upper surface of the second epitaxial layer 14 far from the first epitaxial layer 13 includes at least two ion implantation layers 141 which are arranged at intervals and extend from the upper surface of the second epitaxial layer 14 to the inside of the second epitaxial layer 14 along the direction of the thickness of the metal oxide semiconductor field effect tube, each ion implantation layer 141 corresponds to one trench region 142 and one second buried layer region 143, and the trench region 142 and the second buried layer region 143 are in one-to-one correspondence.
Specifically, the trench region 142 penetrates the ion implantation layer 141 along a longitudinal center line of the ion implantation layer 141 and extends to a second buried region 143 inside the second epitaxial layer 14.
Wherein, the longitudinal center line of the trench area 142 coincides with the longitudinal center line of the ion implantation layer 141, and the longitudinal center line refers to the center line along the direction of the thickness of the metal oxide semiconductor field effect tube.
In the second epitaxial layer 14, the intervals between the ion implantation layers 141 are equal, and it is understood that the intervals between the ion implantation layers 141 refer to the minimum distance between adjacent two ion implantation layers 141 in the upper surface of the second epitaxial layer 14.
The second epitaxial layer 14 is an N-type lightly doped silicon carbide epitaxial layer, and the thickness of the second epitaxial layer 14 is 4 μm to 10 μm, in some embodiments, the thickness of the second epitaxial layer 14 may be in the range of one or any two of 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, and 10 μm.
In the second epitaxial layer 14, the sum of the depths of the trench region 142 and the second buried region 143 is smaller than the thickness of the second epitaxial layer 14.
In an embodiment of the present application, trench region 142 includes a first gate oxide layer 1421, a first gate region 1422, a second gate oxide layer 1423, and a second gate region 1424.
Wherein, the first gate oxide layer 1421 is stacked on the upper surface of the inner wall of the trench region 142. The first gate region 1422, the second gate oxide 1423, and the second gate region 1424 are sequentially stacked on the upper surface of the first gate oxide along the direction from the first epitaxial layer 13 to the second epitaxial layer 14, so as to form a split gate structure. It is understood that, among the gate regions, a first gate region 1422 is stacked on the bottom of the trench region 142 provided with the first gate oxide layer 1421, a second gate oxide layer 1423 is stacked on the upper surface of the first gate region 1422, and a second gate region 1424 is stacked on the upper surface of the second gate oxide layer 1423.
Note that the first gate oxide layer 1421 and the second gate oxide layer 1423 are made of the same material, specifically, the first gate oxide layer 1421 and the second gate oxide layer 1423 may be silicon dioxide (SiO 2) layers, the first gate oxide layer 1421 is used to separate the first gate region 1422 and the second gate region 1424 from the second epitaxial layer 14, and the second gate oxide layer 1423 is used to separate the first gate region 1422 and the second gate region 1424 to form a split gate structure.
The first and second gate regions 1422 and 1424 are the same material, and in an embodiment of the present application, the first and second gate regions 1422 and 1424 are polysilicon (PolySi).
Further, referring to fig. 1, the ion implantation region 141 includes a first ion implantation layer 1412 and a second ion implantation layer 1411 stacked in this order in the thickness direction of the mosfet, and an upper surface of the second ion implantation layer 1411 coincides with an upper surface of the second epitaxial layer 14.
The first ion implantation layer 1412 is used as a lower layer in the ion implantation region 141, the first ion implantation layer 1412 is a P-type lightly doped (P-) layer, the second ion implantation layer 1411 is used as an upper layer in the ion implantation region 141, the second ion implantation layer 1411 comprises a P-type heavily doped region and an N-type heavily doped region, one end of the N-type heavily doped region is connected with the first gate oxide layer 1421 of the trench region 142, and one end of the N-type heavily doped region, which is far away from the trench region 142, is connected with the P-type heavily doped region.
According to the embodiment of the application, the grid electrode in the metal oxide semiconductor field effect transistor is divided into two parts, so that the grid drain capacitance of the grid electrode is reduced, and the grid drain capacitance is positively related to the switching loss of the metal oxide semiconductor field effect transistor, so that the dynamic loss of the metal oxide semiconductor field effect transistor can be reduced, when the metal oxide semiconductor field effect transistor is in a reverse blocking state, namely when reverse bias voltage is applied to the metal oxide semiconductor field effect transistor, the first grid region 1422 positioned at the lower part of the split grid structure is connected with the source electrode metal layer 16 to have a low potential, the PN junction of the body diode formed by the first ion implantation layer 1412 and the second epitaxial layer 14 in the ion implantation layer 141 generates a transverse depletion region, the first grid region 1422 can promote the connection of the transverse depletion region with the depletion region 131 arranged in the middle of the first epitaxial layer 13, so that the electric field distribution in the metal oxide semiconductor field effect transistor is more uniform, the electric field aggregation at the corner at the bottom of the trench region 142 is further suppressed, the electric field strength at the bottom of the trench region 142 is reduced, the electric field strength of the metal oxide semiconductor field effect transistor is improved, and the voltage-resistant property of the metal oxide semiconductor field effect transistor is improved.
Referring to fig. 1, a dielectric layer 15 is laminated on the upper surface of the second epitaxial layer 14, and the dielectric layer 15 is specifically an isolation layer definition (Isolation Layer Definition, ILD) oxide layer, and in an embodiment of the present application, the dielectric layer 15 includes silicon dioxide.
In the embodiment of the present application, the dielectric layer 15 mainly plays a role of isolation and insulation. In addition, the dielectric layer 15 is further used for providing a metal contact position so as to enable electrical connection between the source metal layer 16 and the second epitaxial layer 14 in the metal oxide semiconductor field effect transistor, and specifically, the dielectric layer 15 includes a plurality of target openings 151, and the second epitaxial layer 14 and the source metal layer 16 are connected through contact metal filled in the target openings 151.
The target openings 151 include openings corresponding to P-type heavily doped (p+) regions and N-type heavily doped regions in the second ion implantation layer 1411 and openings corresponding to spaced regions between the ion implantation layers 141. The contact metal comprises ohmic contact metal and Schottky contact metal, and the openings corresponding to the P-type heavily doped region and the N-type heavily doped region in the second ion implantation layer 1411 are filled with ohmic contact metal, and the openings corresponding to the interval regions between the ion implantation layers 141 are filled with Schottky contact metal.
The source metal layer 16 may include copper and/or aluminum, and the thickness of the source metal layer 16 may be 2 μm to 4 μm, specifically, the thickness of the source metal layer 16 may be in a range of values of one or any two of 2 μm, 2.5 μm, 3 μm, 3.5 μm, and 4 μm.
4H-SiC has excellent physical and electrical characteristics, such as high electron saturation drift velocity, high critical breakdown electric field, wide forbidden band and high thermal conductivity, and is suitable for the high-temperature and high-voltage power electronics field. The vertical metal Oxide semiconductor field effect transistor comprises a Double-diffused metal Oxide semiconductor field effect transistor (Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor, DMOSFET) and a power trench gate metal Oxide semiconductor field effect transistor, and the 4H-SiC UMOSFET has a wider application prospect due to the characteristics of a higher density of cell size, high mobility of a nonpolar surface and the like, and smaller on-resistance and larger channel density. In the related art, in the field of power electronics, such as photovoltaic inversion, motor driving, DC-DC conversion, and other application scenarios, a PN body diode needs to be parasitic inside a 4H-SiC UMOSFET, so that the PN body diode is used as a reverse recovery diode to form a complete current path. However, in the related art, a parasitic PN-type body diode in the SiC UMOSFET can generate higher dynamic loss, and under the condition that the SiC UMOSFET is in a reverse blocking state, two-dimensional electric field concentration can exist at the corner of a groove in the SiC UMOSFET, so that the electric field intensity at the bottom of the groove is higher, and the reliability of the device is further reduced. The mosfet provided in the embodiment of the application, firstly, the first buried regions 131 with equal spacing are arranged on the upper surface of the first epitaxial layer 13 at intervals, so that the voltage-withstanding capability of the mosfet can be increased, and the electric field in the mosfet can be regulated to be uniformly distributed, so that the depletion regions of the first doped regions are connected under the condition of applying reverse bias voltage to the mosfet, the schottky region above the mosfet is shielded, the electric field strength at the corners of the lower part of the trench region 142 and the electric field strength at the schottky contact position are reduced, and the mosfet is improved at high temperature, Reliability in high field and other application scenarios. Further, by introducing a trench region 142 into the second epitaxial layer 14, and a first gate region 1422 in the trench region 142, The second gate oxide layer 1423 and the second gate region 1424 are sequentially stacked along the direction from the first epitaxial layer 13 to the second epitaxial layer 14 to form a split gate structure, the split gate structure is utilized to divide the gate electrode in the metal oxide semiconductor field effect transistor into two parts, so that the gate drain capacitance of the gate electrode is reduced, and the gate drain capacitance is positively correlated with the switching loss of the metal oxide semiconductor field effect transistor, the dynamic loss of the metal oxide semiconductor field effect transistor can be reduced, in addition, under the condition that the metal oxide semiconductor field effect transistor is in a reverse blocking state, the first gate region 1422 positioned at the lower part of the split gate structure is connected with the source metal layer 16 to have a low potential, the PN junction of the body diode formed by the first ion implantation layer 1412 and the second epitaxial layer 14 in the ion implantation layer 141 generates a lateral depletion region, the first gate region 1422 can promote the connection of the lateral depletion region and the depletion region formed by the first depletion region 131 arranged in the first epitaxial layer 13, the electric field distribution in the metal oxide semiconductor field effect transistor can be further uniform, the electric field distribution in the metal oxide semiconductor field effect transistor can be further suppressed, the electric field effect of the semiconductor field effect transistor can be further suppressed, the reliability of the semiconductor field effect is improved, and the reliability of the semiconductor field effect is improved.
Optionally, the width of the first gate region 1422 is less than or equal to the width of the second gate region 1424, and the width of the first gate region 1422 and/or the second gate region 1424 is 0.5 μm to 1 μm.
Specifically, the sidewall of the trench region 142 may be an inclined sidewall forming an angle with the lower surface of the second epitaxial layer 14 as shown in fig. 1, such that the width of the opening region of the trench region 142 is greater than the width of the bottom region of the trench region 142, or the sidewall of the trench region 142 may be a sidewall perpendicular to the lower surface of the second epitaxial layer 14, such that the width of the opening region of the trench region 142 is equal to the width of the bottom region of the trench region 142, and the embodiment of the application is not limited to the specific form of the sidewall of the trench region 142.
It will be appreciated that the width of the first gate region 1422 is less than the width of the second gate region 1424 in the case where the sidewalls of the trench region 142 are sloped sidewalls at an angle to the lower surface of the second epitaxial layer 14, and the width of the first gate region 1422 is equal to the width of the second gate region 1424 in the case where the sidewalls of the trench region 142 are sidewalls perpendicular to the lower surface of the second epitaxial layer 14.
In some embodiments, where the width of the first gate region 1422 is less than or equal to the width of the second gate region 1424, the width of the first gate region 1422 may be a range of values for one or any two of 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, and 1 μm, and the width of the second gate region 1424 may be a range of values for one or any two of 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, and 1 μm.
Optionally, the first gate region 1422 and/or the second gate region 1424 has a thickness of 0.5 μm to 1.5 μm. In embodiments of the present application, the thicknesses of the first and second gate regions 1422 and 1424 may be the same or different. Specifically, the thickness of the first gate region 1422 may be in a range of one or any two of 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, and 1.5 μm, and the thickness of the second gate region 1424 may be in a range of one or any two of 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, and 1.5 μm.
Optionally, the thickness of the first gate oxide layer 1421 is greater than the thickness of the second gate oxide layer 1423.
In the embodiment of the application, the split gate structure is utilized to divide the gate electrode in the metal oxide semiconductor field effect transistor into two parts, so that the gate-drain capacitance of the gate electrode is reduced, and meanwhile, the thickness of the first gate oxide layer 1421 is controlled to be larger than that of the second gate oxide layer 1423, so that the thickness of the first gate oxide layer 1421 contacted with the lower surface of the first gate region 1422 is thicker than that of the second gate oxide layer 1423 laminated with the upper surface of the first gate region 1422, and further, the first gate region 1422 can convert a considerable part of gate-drain capacitance into gate-source capacitance, thereby further reducing the gate-drain capacitance and further reducing the dynamic loss of the metal oxide semiconductor field effect transistor.
Alternatively, the thickness of the second gate oxide layer 1423 is 0.05 μm to 0.12 μm. In some embodiments, the thickness of the second gate oxide layer 1423 may be in a range of values of one or any two of 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.10 μm, 0.11 μm, and 0.12 μm.
Alternatively, the thickness of the first gate oxide layer 1421 is 0.08 μm to 0.15 μm. In some embodiments, the thickness of the first gate oxide layer 1421 may be in a range of values of one or any two of 0.08 μm, 0.09 μm, 0.10 μm, 0.11 μm, 0.12 μm, 0.13 μm, 0.14 μm, and 0.15 μm.
It should be noted that, in the embodiment of the present application, the sum of the thicknesses of the first gate region 1422, the second gate region 1424, the first gate oxide layer 1421 and the second gate oxide layer 1423 is equal to the depth of the trench region 142, in other words, the upper surface of the second gate region 1424 is flush with the upper surface of the second epitaxial layer 14.
Optionally, the minimum angle between the sidewalls of the trench region 142 and the lower surface of the second epitaxial layer 14 is 85 ° to 89 °. Specifically, in some embodiments, the minimum value of the angle between the sidewall of the trench region 142 and the lower surface of the second epitaxial layer 14 may be a range of values of one or any two of 85 °, 86 °, 87 °, 88 °, and 89 °.
It will be appreciated that in the case where the minimum value of the angle between the sidewall of the trench region 142 and the lower surface of the second epitaxial layer 14 is 85 ° to 89 °, the angle of ion implantation is advantageously controlled during the preparation of the second buried region 143, and in the case where the minimum value of the angle between the sidewall of the trench region 142 and the lower surface of the second epitaxial layer 14 is 85 ° to 89 °, the opening of the trench region 142 may be enlarged, and the preparation of the first gate oxide layer 1421, the first gate region 1422, the second gate oxide layer 1423, and the second gate region 1424 is advantageously performed.
Alternatively, the depth of the trench region 142 is 2 μm to 3 μm and the width of the trench region 142 is 0.5 μm to 1.2 μm.
Where the depth and width of trench region 142 are the depth and width of the original trench of trench region 142 prior to the fabrication of first gate oxide layer 1421, first gate region 1422, second gate oxide layer 1423, and second gate region 1424. It should be noted that, in the case where the sidewall of the trench region 142 is an inclined sidewall at an angle to the lower surface of the second epitaxial layer 14, the maximum width and the minimum width of the trench region 142 fall within a range of 0.5 μm to 1.2 μm.
In some embodiments, the depth of trench region 142 may be a range of values for one or any two of 2 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm, and 3 μm.
In some embodiments, the width of trench region 142 may be in the range of one or any two of 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, and 1.2 μm.
Alternatively, referring to fig. 1, the target opening 151 includes a first opening 1511 corresponding to the ion implantation layer 141 and a second opening 1512 corresponding to a space region between the ion implantation layers 141.
The contact metal includes an ohmic contact metal and a schottky contact metal, the first opening 1511 is filled with the ohmic contact metal to form a front ohmic contact region between the source metal layer 16 and the semiconductor formed by the second ion implantation layer 1411, and the second opening 1512 is filled with the schottky contact metal to form a schottky contact region between the source metal layer 16 and the second epitaxial layer 14.
Note that the first opening 1511 exposes the upper surfaces of the P-type heavily doped region and the N-type heavily doped region in the second ion implantation layer 1411 at the same time, so as to ensure that the ohmic contact metal filled in the first opening 1511 can form an ohmic contact between the source metal layer 16 and the second ion implantation layer 1411.
In the embodiment of the application, the schottky contact metal filled in the second opening 1512 is used as an anode region in a junction barrier schottky diode (Junction Barrier Schottky Diode, JBS) in the metal oxide semiconductor field effect transistor, a metal system of the schottky contact region is compatible with a metal system of a front ohmic metal contact region, and the schottky contact metal with a low potential barrier is selected to form the schottky metal contact region, so that the source-drain starting voltage of the metal oxide semiconductor field effect transistor in the third quadrant operation is reduced, bipolar conduction degradation caused by a parasitic PN type body diode in the metal oxide semiconductor field effect transistor is eliminated, the unipolar carrier operation capability of the metal oxide semiconductor field effect transistor is improved, the problems of overlarge forward starting voltage drop and long reverse recovery time of the parasitic PN type body diode in the metal oxide semiconductor field effect transistor are solved, the source-drain starting voltage and reverse recovery time of the parasitic PN type body diode in the metal oxide semiconductor field effect transistor are reduced, and the reverse recovery loss of the metal oxide semiconductor field effect transistor is further reduced.
It is understood that in the embodiment of the present application, the boundary between each P-type heavily doped region and each N-type heavily doped region in the second ion implantation layer 1411 corresponds to one first opening 1511, and the interval region between each ion implantation layer 141 corresponds to one second opening 1512.
Optionally, the ohmic contact metal and/or the schottky contact metal comprises any of nickel, titanium, and titanium-nickel alloys, and copper-aluminum alloys.
Optionally, the thickness of the ohmic contact metal and/or the schottky contact metal is less than or equal to the thickness of the dielectric layer 15.
Specifically, the dielectric layer 15 has good electrical stability, and can withstand certain voltage and current without breakdown or failure, and under the condition that the thickness of the ohmic contact metal and/or the schottky contact metal is greater than that of the dielectric layer 15, the electric field intensity on the dielectric layer 15 can be increased, so that the dielectric layer 15 is more prone to breakdown, and further the electrical performance and reliability of the metal oxide semiconductor field effect transistor are affected. In the embodiment of the application, the thickness of the Eum contact metal and/or the Schottky contact metal is smaller than or equal to the thickness of the dielectric layer 15, so that the probability of breakdown or failure of the dielectric layer 15 can be reduced, and the electrical performance and reliability of the metal oxide semiconductor field effect transistor are improved.
Alternatively, the ohmic contact metal has a thickness of 60nm to 200nm and a width of 0.2 μm to 0.5 μm.
Wherein the width of the ohmic contact metal is equal to the width of the first opening 1511.
Specifically, in some embodiments, the thickness of the ohmic contact metal may be in the range of values of one or any two of 60nm, 80nm, 100nm, 120nm, 140nm, 160nm, 180nm, and 200 nm.
In some embodiments, the width of the ohmic contact metal may be in a range of values of one or any two of 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, and 0.5 μm.
Alternatively, the thickness of the schottky contact metal is 0.2 μm to 0.6 μm and the width of the schottky contact metal is 0.3 μm to 0.8 μm.
Wherein the schottky contact metal has a width equal to the width of the second opening 1512.
Specifically, in some embodiments, the thickness of the schottky contact metal may be in a range of values of one or any two of 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, 0.5 μm, 0.55 μm, and 0.6 μm.
In some embodiments, the width of the schottky contact metal may be in the range of one or any two of 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, 0.5 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, and 0.8 μm.
In summary, in the metal oxide semiconductor field effect transistor provided by the embodiment of the application, the trench region 142 is introduced into the second epitaxial layer 14, the first gate region 1422, the second gate oxide layer 1423 and the second gate region 1424 in the trench region 142 are sequentially stacked along the direction from the first epitaxial layer 13 to the second epitaxial layer 14 to form a split gate structure, the split gate structure is utilized to divide the gate in the metal oxide semiconductor field effect transistor into two parts, so that the gate drain capacitance of the gate is reduced, and the gate drain capacitance is positively correlated with the switching loss of the metal oxide semiconductor field effect transistor, the dynamic loss of the metal oxide semiconductor field effect transistor can be reduced, and further, under the condition that the metal oxide semiconductor field effect transistor is in a reverse blocking state, the first gate region 1422 and the source metal layer 16 at the lower part of the split gate structure are connected with each other, the PN junction of the body diode formed by the ion implantation layer 141 and the second epitaxial layer 14 generates a lateral region, the lateral region and the first gate region 1422 can be promoted to be connected with the first epitaxial layer 13 at the middle part to form a first buried region 131, the depletion of the field effect of the semiconductor field effect transistor can be further reduced, and the depletion of the bottom of the metal oxide semiconductor field effect transistor can be further reduced, and the drain field effect of the metal oxide field effect transistor can be further reduced, and the bottom of the drain field oxide field effect transistor can be more uniformly distributed at the bottom.
Method embodiment
Referring to fig. 2, a step flow chart of a method for manufacturing a metal oxide semiconductor field effect transistor according to an embodiment of the present application is shown, where the method includes steps S101 to S108:
and step S101, forming a first epitaxial layer and a second epitaxial layer which are sequentially stacked on the upper surface of the substrate, wherein the upper surface of the first epitaxial layer comprises first buried regions which are arranged at intervals.
Specifically, referring to fig. 3, a schematic cross-sectional structure of a mosfet according to an embodiment of the present application is shown, and epitaxial growth is performed on the upper surface of the substrate 12 to obtain a first epitaxial layer 13 stacked on the upper surface of the substrate 12.
Then, referring to fig. 4, a schematic diagram of a cross-sectional structure of a metal oxide semiconductor field effect transistor provided by the embodiment of the application is shown, the upper surface of the first epitaxial layer 13 is cleaned, a layer of plasma enhanced tetraethyl orthosilicate (PLASMA ENHANCED TETRAETHYL Orthosilicate, PETEOS) layer is deposited on the upper surface of the first epitaxial layer 13, then, photoresist is spin-coated on the upper surface of the PETEOS layer, an ion implantation window corresponding to the first buried region 131 is formed through photolithography and etching processes, then, the photoresist is removed, and a third ion implantation operation is performed by using the PETEOS layer as a mask, so as to remove the PETEOS layer and obtain the first epitaxial layer 13 with the upper surface including the first buried regions 131 arranged at intervals. Wherein the third ion implantation operation is an aluminum ion implantation operation, the first buried regions 131 have equal intervals, the first buried regions 131 may have an interval of 1 μm to 3 μm, and the first buried regions 131 have a depth smaller than the thickness of the first epitaxial layer 13.
Finally, referring to fig. 5, a schematic diagram of a cross-sectional structure of a metal oxide semiconductor field effect transistor according to an embodiment of the present application is shown, wherein a sacrificial oxide layer is prepared on the upper surface of the first epitaxial layer 13, so that surface defects introduced on the upper surface of the first epitaxial layer 13 by the third ion implantation operation are removed by using the sacrificial oxide layer, and epitaxial growth is performed on the upper surface of the first epitaxial layer 13, so as to obtain a second epitaxial layer 14 stacked on the upper surface of the first epitaxial layer 13.
Wherein, the substrate 12 is an N-type heavily doped silicon carbide substrate, and the substrate 12 can be any one of a 4H-SiC single crystal substrate, a 6H-SiC single crystal substrate and a 3C-SiC single crystal substrate. In step S101 to step S107, the thickness of the substrate 12 is 200 μm to 300 μm.
The first epitaxial layer 13 is an N-type lightly doped N-silicon carbide epitaxial layer, the doping concentration of the first epitaxial layer 13 is 6×10 15cm-3 to 6×10 16cm-3, and the thickness of the first epitaxial layer 13 is 4 μm to 10 μm.
The second epitaxial layer 14 is an N-type lightly doped silicon carbide epitaxial layer, the doping concentration of the second epitaxial layer 14 is 6×10 15cm-3 to 6×10 16cm-3, and the thickness of the second epitaxial layer 14 is 4 μm to 10 μm.
The first buried region 131 is a P-type heavily doped region, and the doping concentration of the first buried region 131 is 1×10 18cm-3 to 1×10 20cm-3.
And step S102, performing first ion implantation operation on a first target area on the upper surface of the second epitaxial layer to obtain ion implantation layers arranged at intervals.
The first target region is a region where the ion implantation layer 141 is located in the upper surface of the second epitaxial layer 14.
The first ion implantation operation includes a first sub-operation, a second sub-operation, and a third sub-operation. Specifically, referring to fig. 6, a schematic cross-sectional structure of a mosfet provided in an embodiment of the present application is shown, first, the upper surface of the second epitaxial layer 14 is cleaned, and a PETEOS layer is deposited on the upper surface of the second epitaxial layer 14.
And then, spin-coating photoresist on the upper surface of the PETEOS layer, and forming an ion implantation window corresponding to the first target region through photoetching and etching processes.
Then, the photoresist is removed, and the PETEOS layer is used as a mask, and a first sub-operation, which is an aluminum ion implantation operation, is performed, and the PETEOS layer is removed to form a first original ion implantation layer extending from the upper surface of the second epitaxial layer 14 toward the inside of the second epitaxial layer 14.
Then, a PETEOS layer is deposited on the upper surface of the second epitaxial layer 14, photoresist is spin-coated on the upper surface of the PETEOS layer, and an ion implantation window corresponding to the P-type heavily doped region in the second ion implantation layer 1411 is formed through photolithography and etching processes.
Then, removing the photoresist, and using the PETEOS layer as a mask, performing a second sub-operation, and removing the PETEOS layer to form a P-type heavily doped region in the second ion implantation layer 1411, wherein the second sub-operation is an aluminum ion implantation operation.
Then, a PETEOS layer is deposited on the upper surface of the second epitaxial layer 14, photoresist is spin-coated on the upper surface of the PETEOS layer, and an ion implantation window corresponding to the N-type heavily doped region in the second ion implantation layer 1411 is formed through photolithography and etching processes.
Then, removing the photoresist, and using the PETEOS layer as a mask, performing a third sub-operation, and removing the PETEOS layer to form an N-type heavily doped region in the second ion implantation layer 1411, thereby obtaining a second ion implantation layer 1411 comprising a P-type heavily doped region and an N-type heavily doped region, wherein the third sub-operation is a nitrogen ion implantation operation.
It should be noted that, the upper portion of the first original ion implantation layer forms the second ion implantation layer 1411 including two P-type heavily doped regions and one N-type heavily doped region through the second sub-operation and the third sub-operation, and the portion of the first original ion implantation layer other than the second ion implantation layer 1411 is the first ion implantation layer 1412, and the second ion implantation layer 1411 is laminated on the upper surface of the first ion implantation layer 1412, where the thickness of the first original ion implantation layer is equal to the sum of the thicknesses of the second ion implantation layer 1411 and the first ion implantation layer 1412.
In the ion implantation layer 141, both left and right ends of the N-type heavily doped region in the second ion implantation layer 1411 are connected to the P-type heavily doped region, respectively.
The pitches between the respective ion implantation layers 141 in the upper surface of the second epitaxial layer 14 are equal.
In addition, the doping concentrations of the second ion implantation layer 1411 and the first ion implantation layer 1412 in the implantation layer 141 may be determined according to actual requirements, which is not limited in the embodiment of the present application.
And step 103, etching the second epitaxial layer along the longitudinal center line of the ion implantation layer to obtain a target groove penetrating through the ion implantation layer.
Specifically, in the case that the ion implantation layers 141 disposed at intervals on the upper surface of the second epitaxial layer 14 are obtained in step S102, the second epitaxial layer 14 may be etched along the longitudinal center line of each ion implantation layer 141 by etching processes such as growth mask medium, photolithography, dry etching, surface oxidation, selective etching, and the like, so as to obtain the target trench 01 penetrating through the ion implantation layer 141, and referring to fig. 7, a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor according to an embodiment of the present application is shown.
In the embodiment of the present application, for each ion implantation layer 141, the longitudinal center line of the target trench 01 coincides with the longitudinal center line of the ion implantation layer 141.
The sidewall of the target trench 01 may be an inclined sidewall forming an angle with the lower surface of the second epitaxial layer 14 as shown in fig. 7, such that the width of the opening region of the target trench 01 is greater than the width of the bottom region of the target trench 01, or a sidewall perpendicular to the lower surface of the second epitaxial layer 14, such that the width of the opening region of the target trench 01 is equal to the width of the bottom region of the trench region 142, and the specific form of the sidewall of the target trench 01 is not limited in the embodiment of the present application.
In the case where the sidewall of the target trench 01 is an inclined sidewall at an angle to the lower surface of the second epitaxial layer 14, the minimum value of the angle between the sidewall of the target trench 01 and the lower surface of the second epitaxial layer 14 is 85 ° to 89 °.
In the case where the sidewall of the target trench 01 is an inclined sidewall at an angle to the lower surface of the second epitaxial layer 14, after the second epitaxial layer 14 is etched by an etching process such as a growth mask medium, photolithography, dry etching, surface oxidation, selective etching, etc., the sidewall of the target trench 01 needs to be etched by a reactive ion etching (Reactive Ion Etching, RIF) process to obtain the target trench 01 having the sidewall at an angle to the lower surface of the second epitaxial layer 14.
In the embodiment of the present application, the depth of the target trench 01 is 2 μm to 3 μm, and the width of the target trench 01 is 0.5 μm to 1.2 μm.
Step S104, performing a second ion implantation operation on the bottom of the target trench to form a second buried region in the second epitaxial layer, wherein the second buried region is in contact with the bottom of the target trench.
Specifically, in the process of performing the second ion implantation operation on the bottom of the target trench 01, referring to fig. 8, a schematic diagram of a cross-sectional structure of a metal oxide semiconductor field effect transistor according to an embodiment of the present application is shown, where the second ion implantation operation may be performed by means of an oblique angle implantation to form a second buried region 143 in the second epitaxial layer 14 in contact with the bottom of the target trench 01, where the oblique angle of the oblique angle implantation is 0 ° to 30 °.
The second ion implantation operation is an aluminum ion implantation operation.
It is understood that, after step S104, in the second epitaxial layer 14, the target trench 01 penetrates the ion implantation layer 141 and extends to be in contact with the second buried region 143.
Wherein, in the second epitaxial layer 14, the sum of the depths of the target trench 01 and the second buried region 143 is smaller than the thickness of the second epitaxial layer 14.
Step 105, sequentially preparing a first gate oxide layer, a first gate region, a second gate oxide layer and a second gate region in the target trench to obtain a trench region, wherein the first gate oxide layer is laminated on the inner wall of the trench region, and the first gate region, the second gate oxide layer and the second gate region are sequentially laminated on the upper surface of the first gate oxide layer along the direction from the first epitaxial layer to the second epitaxial layer to form a split gate structure.
Specifically, firstly, a sacrificial oxide layer with better quality is formed on the upper surface of the second epitaxial layer 14 after step S104 by adopting a dry-oxygen thermal oxidation method, interface damage caused by ion implantation and ion etching is removed by wet etching the sacrificial oxide layer, then, after the sacrificial oxide layer is removed, referring to fig. 9, a schematic diagram of a cross section structure of a metal oxide semiconductor field effect transistor provided by the embodiment of the application is shown, a first gate oxide layer 1421 with low interface state density and high mobility is grown on the upper surface of the inner wall of the target trench 01 by adopting a dry-oxygen thermal oxidation, deposition and annealing combined method, wherein the temperature of the dry-oxygen thermal oxidation is 1000 ℃ to 1500 ℃, then, a first polysilicon deposition and etching are carried out through a low-pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) deposition process, so as to obtain a first gate region 1422 stacked at the bottom of the target trench 01 provided with the first gate oxide layer 1421, then, a second gate oxide layer 3 is grown on the upper surface of the first gate region 1422, then, the second gate region 1423 is etched on the upper surface of the second gate oxide layer 1423, the second gate region 1424 is etched, the second gate region 1424 is finally, the second gate region 1424 is obtained through the second gate region is etched, and the second gate region is finally, the second gate region 1424 is etched, and the second gate region is obtained through the second gate region is etched.
Among other things, the processes of annealing activation, planarization, photolithography, etching, etc. are beneficial to optimize the surface topography of the first and second gate regions 1422 and 1424, and improve the reliability of the trench region 142.
In the trench region 142, a first gate oxide layer 1421 is stacked on the upper surface of the inner wall of the trench region 142. The first gate region 1422, the second gate oxide 1423, and the second gate region 1424 are sequentially stacked on the upper surface of the first gate oxide 1421 along the direction from the first epitaxial layer 13 to the second epitaxial layer 14, so as to form a split gate structure. It is understood that, among the gate regions, a first gate region 1422 is stacked on the bottom of the trench region 142 provided with the first gate oxide layer 1421, a second gate oxide layer 1423 is stacked on the upper surface of the first gate region 1422, and a second gate region 1424 is stacked on the upper surface of the second gate oxide layer 1423.
Note that the first gate oxide layer 1421 and the second gate oxide layer 1423 are made of the same material, and specifically, the first gate oxide layer 1421 and the second gate oxide layer 1423 may be silicon dioxide layers.
The first gate region 1422 and the second gate region 1424 are made of the same material, and in the embodiment of the present application, the first gate region 1422 and the second gate region 1424 are made of polysilicon, and the doping concentration of polysilicon may be 10 21cm-3 to 2×10 19cm-3.
In an embodiment of the present application, the width of the first gate region 1422 is less than or equal to the width of the second gate region 1424, and the width of the first gate region 1422 and/or the second gate region 1424 is 0.5 μm to 1 μm. The width of the first gate region 1422 is smaller than the width of the second gate region 1424 in the case that the sidewall of the trench region 142 is an inclined sidewall at an angle to the lower surface of the second epitaxial layer 14, and the width of the first gate region 1422 is equal to the width of the second gate region 1424 in the case that the sidewall of the trench region 142 is a sidewall perpendicular to the lower surface of the second epitaxial layer 14.
The thickness of the first and/or second gate regions 1422, 1424 is 0.5 μm to 1.5 μm.
The second gate oxide layer 1423 has a thickness of 0.05 μm to 0.12 μm, the first gate oxide layer 1421 has a thickness of 0.08 μm to 0.15 μm, and the first gate oxide layer 1421 has a thickness greater than the second gate oxide layer 1423.
And S106, preparing an original dielectric layer on the upper surface of the second epitaxial layer with the groove area.
Specifically, an ILD oxide layer is deposited on the upper surface of the second epitaxial layer 14 by a deposition process to obtain an original dielectric layer 15-1, and referring to fig. 10, a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor according to an embodiment of the present application is shown.
And step S107, preparing a target opening in a second target area of the original dielectric layer, and filling contact metal into the target opening to obtain the dielectric layer.
Specifically, first, a first opening 1511 corresponding to the ion implantation layer 141 and a second opening 1512 corresponding to a space region between the ion implantation layers 141 are obtained in a second target region of the original dielectric layer 15-1 through photolithography, etching, and stripping processes, then, ohmic contact metal is formed in the first opening 1511 and schottky contact metal is formed in the second opening 1512 through deposition, metallization processes, and high-temperature annealing processes, so as to obtain the dielectric layer 15, and referring to fig. 11, a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application is shown.
Wherein the first opening 1511 and the second opening 1512 constitute a target opening 151 in the dielectric layer 15, and the ohmic contact metal filled in the first opening 1511 and the schottky contact metal filled in the second opening 1512 constitute a contact metal filled in the target opening 151.
The ohmic contact metal filled in the first opening 1511 forms a front ohmic metal contact region between the source metal layer 16 and the semiconductor formed by the second ion implantation layer 1411, and the schottky contact metal filled in the second opening 1512 forms a schottky metal contact region between the source metal layer 16 and the second epitaxial layer 14.
Note that the first opening 1511 exposes the upper surfaces of the P-type heavily doped region and the N-type heavily doped region in the second ion implantation layer 1411 at the same time, so as to ensure that the ohmic contact metal filled in the first opening 1511 can form an ohmic contact between the source metal layer 16 and the second ion implantation layer 1411.
The interface between each P-type heavily doped region and each N-type heavily doped region in the second ion implantation layer 1411 corresponds to a first opening 1511, and the spacing region between each ion implantation layer 141 corresponds to a second opening 1512.
The ohmic contact metal and/or the schottky contact metal may comprise any of nickel, titanium, and titanium-nickel alloys, and copper-aluminum alloys.
The thickness of the ohmic contact metal and/or the schottky contact metal is less than or equal to the thickness of the dielectric layer 15.
In the embodiment of the application, the thickness of the ohmic contact metal is 60nm to 200nm, the width of the ohmic contact metal is 0.2 μm to 0.5 μm, the thickness of the Schottky contact metal is 0.2 μm to 0.6 μm, and the width of the Schottky contact metal is 0.3 μm to 0.8 μm. It is understood that the ohmic contact metal has a width equal to the width of the first opening 1511 and the schottky contact metal has a width equal to the width of the second opening 1512.
And S108, preparing a source metal layer on the upper surface of the dielectric layer, and preparing a drain metal layer on the lower surface of the substrate to obtain the metal oxide semiconductor field effect transistor.
Specifically, first, a source metal layer 16 is formed on the upper surface of the dielectric layer 15 by sputtering, and then, a thinning process is performed on the lower surface of the substrate 12 by at least one of a mechanical grinding method, a chemical etching method, and an inductively coupled plasma etching (Inductively Coupled PLASMA ETCHING, ICP) technique to thin the thickness of the substrate 12 to 100 μm to 150 μm, and a drain metal layer 11 is formed on the lower surface of the substrate 12 by a sputtering process, referring to fig. 1.
The source metal layer 16 may include copper and/or aluminum, and the source metal layer 16 may have a thickness of 2 μm to 4 μm.
The drain metal layer 11 may include any one of nickel, titanium and titanium-nickel alloy and copper-aluminum alloy, and the drain metal layer 11 has a thickness of 0.5 μm to 1.5 μm.
It can be appreciated that the method for manufacturing a metal oxide semiconductor field effect transistor provided by the embodiment of the present application can be used for manufacturing a metal oxide semiconductor field effect transistor as described in any one of the above, and can achieve the same technical effects, and for avoiding repetition, no further description is given here.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.
Claims (12)
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